DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
1. Amendments filed on have been entered. Claims 1, 4, and 5 have been amended.
Response to Arguments
2. Applicant’s arguments with respect to claim(s) 1-3 and 8-15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claim(s) 1-3 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 2020/0327834) in view of Zhou (US 2018/0330653) and further in view of Kim et al (US 2016/0379906).
As to claim 1, Kim834 teaches a display device, comprising:
a timing controlling circuit (timing controller 210, fig. 3) generating an image data, a data control signal, and a gate control signal ([0080]));
a data driving circuit (data driver 220, fig. 3) generating a data signal using the image data and the data control signal ([0081]);
a gate driving circuit (scan driver 410, fig. 3) generating a gate signal using the gate control signal ([0078]); and
a display panel displaying an image using the data signal and the gate signal ([0081] The data driver 220 converts the digital video data DATA into analog … outputs these data voltages to the data lines DL through the fan-out lines FL. The sub-pixels SP are selected by the scan signals…, and the data voltages are supplied to the selected sub-pixels SP) and including
mux test line (data voltage line 155, fig. 10), a plurality of mux enable transistors (SW11, SW12, SW13 and SW14, fig. 10) connected to the mux test line pr(fig. 10 illustrates that the data voltage line 155 is connected to SW11, SW12, SW13 and SW14, fig. 10), data film lines (fan-out lines FOL1 to FOL4, fig. 10) and mux test line (data voltage line 155) overlap each other (as seen in figure 10).
Kim834 does not teach a plurality of mux test lines a plurality of mux test lines, a plurality of mux enable transistors respectively connected to the plurality of mux test lines, a plurality of mux pads respectively connected to the plurality of mux enable transistors, and a plurality of data pads connected to a plurality of data film lines of a flexible printed circuit to receive the data signal, wherein the plurality of mux test lines and the plurality of data film lines overlap each other as claimed.
However, Zhou teaches a plurality of mux test lines (test signal lines DO and DE, fig. 1B), a plurality of mux enable transistors (transistors T2, fig. 1B) respectively connected to the plurality of mux test lines (Figure 1B illustrates that one of the first or the second electrode of the first T2 is coupled to the test signal line DO and one of the first or the second electrode of the second T2 is coupled to the test signal line DE), a plurality of data film lines (data signal fanout A, fig. 1B) of a flexible printed circuit to receive the data signal ([0054] Flexible Printed Circuit (FPC) Pad arranged in the non-display area, where the driver chip IC includes one terminal electrically connected respectively with the data signal fanout wires Fanout A and the touch signal fanout wires Fanout B, and the other terminal electrically connected with the Flexible Printed Circuit (FPC) Pad through connection wires. The driver chip IC is generally configured to provide signals on the data lines), wherein the plurality of mux test lines (test signal lines DO and DE, fig. 1B) and the plurality of data film lines (data signal fanout A, fig. 1B) overlap each other (as illustrated in figure 1B).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kim834 to teach, the test circuit, as suggested by Zhou. The motivation would have been in order to provide a narrow bezel and improve the display quality ([0003]).
Kim834 and Zhou do not teach a plurality of mux pads respectively connected to the plurality of mux enable transistors, and a plurality of data pads connected to a plurality of data film lines as claimed.
However, Pads or connectors to connect two components are well known in the art (for example, Kim906 in paragraph [0057] discloses that the AP TRs T1 and T2 are connected to input channels of the multiplexer 103 via pads 21 to 25 of a first pad group PAD1. Data lines S1 to S6 are connected to output channels of the multiplexer 103. Kim906 in paragraph [0059] further discloses that the drains of T1 and T2 are connected to the second AP pad 12).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kim834 and Zhou to teach, incorporating pads, as suggested by Kim906. The motivation would have been in order to improve testing method ([0018], [0022]).
As to claim 2, Kim834 in view of Zhou teach the display device, wherein the display panel further includes a plurality of gate lines (Kim834: scan lines SL, fig. 2) and a plurality of data lines (Kim834: data lines DL, fig. 2) crossing each other and define a plurality of subpixels (Kim834: see fig. 2), a plurality of mux link lines (Kim834: fan-out lines FOL1 to FOL4 between inspection unit 150 and demultiplexer unit 160, fig. 10), and a plurality of mux transistors (Kim834: transistors in the demultiplexer unit 160, fig. 10 ) respectively connected between the plurality of mux link lines (Kim834: fan-out lines FOL1 to FOL4 between inspection unit 150 and demultiplexer unit 160, fig. 10) and the plurality of data lines (Kim834: DL1-DL8, fig. 10).
Kim834 in view of Zhou do not teach a plurality of mux link lines respectively connected to the plurality of mux pads as claimed.
However, Pads or connectors to connect two components are well known in the art (for example, Kim906 in paragraph [0057] discloses that the AP TRs T1 and T2 are connected to input channels of the multiplexer 103 via pads 21 to 25 of a first pad group PAD1. Data lines S1 to S6 are connected to output channels of the multiplexer 103. Kim906 in paragraph [0059] further discloses that the drains of T1 and T2 are connected to the second AP pad 12).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kim834 and Zhou to teach, incorporating pads, as suggested by Kim906. The motivation would have been in order to improve testing method ([0018], [0022]).
As to claim 3, Kim834 in view of Zhou teach the display device, wherein the plurality of mux transistors (Kim834: transistors in the demultiplexer unit 160, fig. 10) are switched according to a plurality of mux signals (Kim834: a first demultiplexer control signal CLA and a second demultiplexer control signal CLB, fig. 10).
Kim834 in view of Zhou does not teach the plurality of mux pads as claimed.
However, Pads or connectors to connect two components are well known in the art (for example, Kim906 in paragraph [0057] discloses that the AP TRs T1 and T2 are connected to input channels of the multiplexer 103 via pads 21 to 25 of a first pad group PAD1. Data lines S1 to S6 are connected to output channels of the multiplexer 103. Kim906 in paragraph [0059] further discloses that the drains of T1 and T2 are connected to the second AP pad 12).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kim834 and Zhou to teach, incorporating pads, as suggested by Kim906. The motivation would have been in order to improve testing method ([0018], [0022]).
As to claim 15, Kim834 in view of Zhou teach the display device, wherein gate electrodes of the plurality of mux enable transistors (Zhou: transistors T1, fig. 1B) are connected to receive a mux enable signal (Zhou: CKH R, CKH G and CKH B, fig. 1B), drain electrodes of the plurality of mux enable transistors (Zhou: transistors T1, fig. 1B) are connected to the plurality of mux test lines respectively (fanout lines connecting between transistor T1 and T2, fig. 1B).
Kim834 in view of Zhou teach do not teach mux enable pads and mux pads as claimed.
However, Pads or connectors to connect two components are well known in the art (for example, Kim906 in paragraph [0057] discloses that the AP TRs T1 and T2 are connected to input channels of the multiplexer 103 via pads 21 to 25 of a first pad group PAD1. Data lines S1 to S6 are connected to output channels of the multiplexer 103. Kim906 in paragraph [0059] further discloses that the drains of T1 and T2 are connected to the second AP pad 12).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kim834 and Zhou to teach, incorporating pads, as suggested by Kim906. The motivation would have been in order to improve testing method ([0018], [0022]).
4. Claim(s) 8-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 2020/0327834) in view of Zhou (US 2018/0330653) and further in view of Kim et al (US 2016/0379906) and further in view of BONG et al (US 2021/0201766).
As to claim 8, Kim834 in view of Zhou and further in view of Kim906 do not teach the display device as claimed.
However, BONG teaches the display device, wherein the gate signal includes a first scan signal (GATE1, FIG. 2), a second scan signal (GATE2, FIG. 2), a first emission signal (EMS1, FIG. 2), and a second emission signal (EMS2, FIG. 2), wherein the display panel further includes a plurality of subpixels (PIXELS P, FIG. 1), and wherein each of the plurality of subpixels comprises: a storage capacitor (Cst1, FIG. 2); a first transistor (M1, FIG. 2) switched according to a voltage of a first capacitor electrode of the storage capacitor (Cst1, FIG. 2); a second transistor (M3, FIG. 2) switched according to the second scan signal (GATE2, FIG. 2), the second transistor connected to the data signal (Vdata, FIG. 2) and the first transistor (M1, FIG. 2); a third transistor (M2, FIG. 2) switched according to the first scan signal (GATE1, FIG. 2), the third transistor connected to the storage capacitor (Cst1, FIG. 2) and the first transistor (M1, FIG. 2); a fourth transistor (M6, FIG. 2) switched according to the first scan signal (GATE1, FIG. 2), the fourth transistor connected to the storage capacitor (Cst1, FIG. 2) and an initial signal (Vini, FIG. 2); a fifth transistor (M5, FIG. 2) switched according to the second emission signal (EMS2, FIG. 2), the fifth transistor (M5, FIG. 2) connected to a high-level signal (EVDD, FIG. 2) and the first transistor (M1, FIG. 2); a sixth transistor (M4, FIG. 2) switched according to the first emission signal (EMS1, FIG. 2), the sixth transistor connected to the first transistor (M1, FIG. 2); and a light emitting diode (LED, FIG. 2) connected to the sixth transistor and a low-level signal (EVSS, FIG. 2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kim834 in view of Zhou and further in view of Kim906 to teach, a subpixel, as suggested by BONG. The motivation would have been in order to “improve image quality” ([0002]).
As to claim 9, Kim834 in view of Zhou and further in view of Kim906 and further in view of BONG teaches the display device, wherein at least one of the first transistor to the sixth transistor is an oxide semiconductor thin film transistor (BONG: [0054] at least the second transistor M2 out of the first to sixth transistors M1 to M6 may include oxide semiconductor).
As to claim 10, Kim834 in view of Zhou and further in view of Kim906 and further in view of BONG teaches the display device, wherein the first transistor, the second transistor, the fifth transistor, and the sixth transistor are negative type low temperature polycrystalline silicon thin film transistors (BONG: [0081] the semiconductor layers of the first transistor M1 and the third to sixth transistors M3 to M6 include low-temperature polysilicon), and the third transistor and the fourth transistor are negative type oxide semiconductor thin film transistors (BONG: [0054], [0055] When the first transistor M1 and the third to sixth transistors M3 to M6 include oxide semiconductor, an amount of leakage current further decreases, [0103] At least the second transistor M2 out of the first to sixth transistors M1 to M6 includes oxide semiconductor).
5. Claim(s) 11 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 2020/0327834) in view of Zhou (US 2018/0330653) and further in view of Kim et al (US 2016/0379906) and further in view of Lee et al (US 2024/0071310).
As to claim 11, Kim834 in view of Zhou and further in view of Kim906 do not teach the display device as claimed.
However, Lee teaches the display device, wherein the gate signal includes a first scan signal (Gij, fig. 2), a second scan signal (GWj, fig. 2), a first emission signal (EMaj, fig. 2), and a second emission signal (EMbj, fig. 2), wherein the gate driving circuit includes a first gate driving circuit (300, fig. 1) and a second gate driving circuit (400, fig. 1) disposed at both sides of the display panel (see fig. 1), wherein the first gate driving circuit includes a second scan block (second scan driving circuit 330, fig. 3) generating the second scan signal (GWj, figs. 1 and 3) and a second emission block (emission driving circuit 310, fig. 3) generating the second emission signal (EMbj, figs. 1 and 3), and wherein the second gate driving circuit includes a first scan block (second scan driving circuit 430, fig. 4) generating the first scan signal (Gij, figs 1 and 4) and a first emission block (emission driving circuit 410, fig. 4) generating the first emission signal (EMaj, figs. 1 and 4).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kim834 in view of Zhou and further in view of Kim906 to teach, the first gate driving circuit and the second gate driving circuit, as suggested by Lee. The motivation would have been in order to provide a display device “that operate at various frequencies” ([0004]).
As to claim 12, Kim834 in view of Zhou and further in view of Kim906 and further in view of Lee teaches the display device, wherein the second scan block is farther from the display panel than the second emission block or the second emission block (Lee: 310, fig. 3) is farther from the display panel than the second scan block (Lee: 330, fig. 3), and wherein the first scan block is farther from the display panel than the first emission block or the first emission block (Lee: 410, fig. 4) is disposed farther from the display panel than the first scan block (Lee: 430, fig. 1).
6. Claim(s) 13 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 2020/0327834) in view of Zhou (US 2018/0330653) and further in view of Kim et al (US 2016/0379906) and further in view of Lee et al (US 2024/0071310) and further in view of Kwon et al (US 2014/0139413).
As to claim 13, Kim834 in view of Zhou and further in view of Kim906 and further in view of Lee does not teach the display device as claimed.
However, Kwon teaches the display device, wherein the display panel further includes a plurality of gate link lines (gate link line GLL, fig. 6) connected to the first gate driving circuit (gate PCB 170a, fig. 5) and the second gate driving circuit (gate PCB 170b, fig. 5) and a plurality of gate pads connected to the plurality of gate link lines ([0063] a plurality of gate pads that are connected to both sides of a corresponding gate line DL through a gate link line).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kim834 in view of Zhou and further in view of Kim906 and further in view of Lee to teach, gate link lines and gate pads, as suggested by Kwon. The motivation would have been in order to provide “method for minimizing a drop of the driving voltage supplied to each pixel” ([0015]).
As to claim 14, Kim834 in view of Zhou and further in view of Kim906 and further in view of Lee and further in view of Kwon teaches the display device, wherein the plurality of gate pads are connected to a plurality of gate film lines of a flexible printed circuit which transmit the gate control signal (Kwon: fig. 6 illustrates gate film lines on the gate flexible circuit film 131 are connected to gate link line GLL, [0063] a plurality of gate pads that are connected to both sides of a corresponding gate line DL through a gate link line).
Allowable Subject Matter
7. Claims 16-19 are allowed.
The following is an examiner’s statement of reasons for allowance: The prior art of record alone or in combination, fails to teach or render obvious, “A method of fabricating a display device, comprising: forming a plurality of mux test lines, a plurality of mux enable transistors respectively connected to the plurality of mux test lines, and a plurality of mux pads respectively connected to the plurality of mux enable transistors on a display panel; connecting a plurality of mux test pads of a test substrate to the plurality of mux test lines of the display panel by disposing the test substrate adjacent to the display panel; performing a lighting test of the display panel by turning on the plurality of mux enable transistors and applying a plurality of mux signals from the test substrate to the plurality of mux pads; connecting a plurality of mux film lines of a flexible printed circuit to the plurality of mux pads by attaching the flexible printed circuit to the display panel; and driving the display panel by turning off the plurality of mux enable transistors and applying a plurality of mux signals from the flexible printed circuit to the plurality of mux pads” in combination with the other claimed limitations set forth in claim 16.
8. Claims 4-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMEN W BOGALE whose telephone number is (571)270-1579. The examiner can normally be reached M-F 10:AM-6:PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Nitin Patel can be reached at (571)272-7677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AMEN W BOGALE/ Examiner, Art Unit 2628
/NITIN PATEL/ Supervisory Patent Examiner, Art Unit 2628