DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 to 20 are presented for examination.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 to 3, 6, 10 to 12, 15, 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Gollub et al. (USPAP 20170269979).
Claims 1, 10 and 15:
Gollub substantially teaches the claimed invention. Gollub teaches a method and an apparatus for dynamic random-access memory (DRAM) scrub and error counting, the apparatus comprising: a computer system comprising a memory (106) in communication with a memory controller (104) and a CPU (102) (see fig. 1). Gollub teaches that the memory controller is for reading and storing data in the memory via of an interface (110) (see par. 0018). Gollub teaches that the memory includes an error correction code (ECC) check/correction logic (212) that checks for and correct any bit errors in the read data and ECC bits that are inputted to the ECC check/correct logic (see par. 0021). Gollub teaches that a write logic (208) writes the data and ECC bits to the memory array (see par. 0022). Gollub teaches that the modifying and writing portions of the RWN process are only performed when an error is detected in the read data by the ECC check/correct logic (see par. 0022).
Gollub teaches that a scrub logic (202) cycles through each of the memory locations in the memory array (214) to write corrected data values to the memory array (see par. 0021). Gollub teaches that the scrub logic sends the current address of the memory location to be scrubbed to read logic which reads the data from the memory array at that memory location (“target row”) (see par. 0021). Gollub teaches that when a refresh command is issued for a current location pointed to by the internal address pointer, a scrubbing operation is performed and the pointer is incremented to the next location in the memory (see par. 0023).
Gollub teaches that the use of the specify expected number of bit errors allows a number of errors that are not reported or tracked by the scrub process (see par. 0026). Gollub teaches that if the number of errors exceeds the threshold set for the DRAM, an alert is sent to the memory controller wherein the alert indicates the number of bit errors that were detected in excess of the manufacturer expected number (see par. 0032). Gollub teaches autonomous internal DRAM scrubbing (“self-scrub mode”) of single bit fails wherein an alert signal (“EEA”) or polling can be used to communicate to the memory controller if the error count gets too high (see par. 0035). Gollub further teaches that according to embodiments, all internal locations in the DRAM will be scrubbed atomically (see par. 0035).
Gollub dose not specifically teach the limitation of: “the EEA have a scrub required value and cause the corrected read data to be written back to the target row of the memory cell array;” however, this teaching is obvious to the teachings of Gollub because Gollub teaches that the manufacturer of a DRAM, sets an error threshold wherein an alert results, if the number of errors detected exceeds the threshold in data read from the memory.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method and apparatus of Gollub to include the limitation of: ““the EEA have a scrub required value and cause the corrected read data to be written back to the target row of the memory cell array; because Gollub teaches that to reduce overhead and complexity of DRAM’s includes an autonomous internal DRAM scrubbing when a single bit fails which comprises an alert signal being communicated to the memory controller when a number of bit errors that are detected are in excess of the manufacturer expected number. This modification would have been obvious because a person of ordinary skill in the art would have been motivated to employ a method and an apparatus for reducing overhead and complexity in DRAMS by providing autonomous DRAM scrubbing of single bit failures as taught by Gollub (see par. 0012).
As per claims 2, 11, and 20, Gollub teaches that in both internal and external refresh operations a refresh command (“scrub enable signal”) enables a scrubbing operation of the DRAM (see par. 0014).
As per claims 3 and 12, Gollub teaches that the apparatus includes a mode register that sets the mode register set (MRS) command and provide an internal address pointer to point to the word location in the DRAM for a scrub operation (see par. 0014). Gollub teaches that the memory includes a scrub logic (202)) that performs autonomous internal memory scrubbing using the MRS command to set the memory to scrub mode (see par. 0020).
As per claim 6, Gollub teaches that a first specified value is set that represents an expected number of bit errors (“two or fewer errors”) as determine by the DRAM manufacturer (see par. 0026).
As per claim 18, Gollub teaches that either an alert signal or polling can be used to communicate to a memory controller if the error counts get too high. (see par. 0035). Gollub teaches that the corrected data is written back to the same memory location (see par. 0013).
Allowable Subject Matter
Claims 4 to 5, 7 to 9, 13 to 14, 16 to 17 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hoya (USPAP 2017/0372798) discloses a magnetic memory device and memory system.
Benedict et al. (USPAP 2016/0092306) discloses a platform error correction for a memory system with periodic scrubbing operations.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHELLY A CHASE whose telephone number is (571)272-3816. The examiner can normally be reached Mon-Thu 8:00-5:30, 2nd Friday 8:00-4:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Albert Decady can be reached at 571-272 3819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Shelly A Chase/Primary Examiner, Art Unit 2112
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