DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-5 and 7-15 of U.S. Patent No. 12236867 in view of Zhang et al. (US 2021/0027706 A1).
Claim 1 of the current application is disclosed by claim 1 of US 12236867, but claim 1 of US 12236867 does not explicitly disclose switch configured to render the gate electrode of the driving transistor floating during a reset phase of operation of the pixel driving circuit.
However, Zhang et al. teaches switch (M3 in Fig. in Fig. 3) configured to render the gate electrode of the driving transistor (M0 in Fig. 3) floating during a reset phase of operation of the pixel driving circuit (see Fig. 5A during the reset stage T1, signals SC1 and SC3 are high, which turns off p-type transistors M5 and M3 in Fig. 3, and renders the gate electrode of driving transistor M0 in Fig. 3 floating).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of claim 1 of US 12236867 such that the switch is configured to render the gate electrode of the driving transistor floating during a reset phase of operation of the pixel driving circuit as taught by Zhang et al. in order to provide a display panel with high resolution.
Claim 2 of the current application is disclosed by claim 2 of US 12236867 in view of Zhang et al.
Claim 3 of the current application is disclosed by claim 3 of US 12236867 in view of Zhang et al.
Claim 4 of the current application is disclosed by claim 4 of US 12236867 in view of Zhang et al.
Claim 5 of the current application is disclosed by claims 1 and 5 of US 12236867 in view of Zhang et al.
Claim 6 of the current application is disclosed by claim 1 of US 12236867 in view of Zhang et al.
Claim 7 of the current application is disclosed by claim 1 of US 12236867 in view of Zhang et al.
Claim 8 of the current application is disclosed by claim 7 of US 12236867, but claim 7 of US 12236867 does not explicitly disclose a reset transistor having a first electrode connected to an initialization signal line, a second electrode connected to the first capacitor electrode.
However, Zhang et al. teaches a reset transistor (transistor M1 in Fig. 3) having a first electrode connected to an initialization signal line (VINIT line in Fig. 3), a second electrode connected to the first capacitor electrode (first electrode of capacitor Cst in Fig. 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify device of claim 7 of US 12236867 with a reset transistor having a first electrode connected to an initialization signal line, a second electrode connected to the first capacitor electrode as taught by Zhang et al. in order to provide a display panel with high resolution.
Claim 9 of the current application is disclosed by claim 7 of US 12236867 in view of Zhang et al.
Claim 10 of the current application is disclosed by claim 8 of US 12236867 in view of Zhang et al.
Claim 11 of the current application is disclosed by claim 9 of US 12236867 in view of Zhang et al.
Claim 12 of the current application is disclosed by claim 10 of US 12236867 in view of Zhang et al.
Claim 13 of the current application is disclosed by claim 11 of US 12236867 in view of Zhang et al.
Claim 14 of the current application is disclosed by claim 12 of US 12236867, but claim 12 of US 12236867 does not explicitly disclose a reset transistor having a first electrode connected to an initialization signal line, a second electrode connected to the first capacitor electrode, and wherein the method further comprises rendering, by the switch, the gate electrode of the driving transistor floating during a reset phase of operation of the pixel driving circuit.
However, Zhang et al. teaches a reset transistor (transistor M1 in Fig. 3) having a first electrode connected to an initialization signal line (VINIT line in Fig. 3), a second electrode connected to the first capacitor electrode (first electrode of capacitor Cst in Fig. 3), and wherein the method further comprises rendering, by the switch (M3 in Fig. in Fig. 3), the gate electrode of the driving transistor (M0 in Fig. 3) floating during a reset phase of operation of the pixel driving circuit (see Fig. 5A during the reset stage T1, signals SC1 and SC3 are high, which turns off p-type transistors M5 and M3 in Fig. 3, and renders the gate electrode of driving transistor M0 in Fig. 3 floating).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify device of claim 12 of US 12236867 with a reset transistor having a first electrode connected to an initialization signal line, a second electrode connected to the first capacitor electrode, and rendering, by the switch, the gate electrode of the driving transistor floating during a reset phase of operation of the pixel driving circuit as taught by Zhang et al. in order to provide a display panel with high resolution.
Claim 15 of the current application is disclosed by claim 13 of US 12236867 in view of Zhang et al.
Claim 16 of the current application is disclosed by claim 14 of US 12236867 in view of Zhang et al.
Claim 17 of the current application is disclosed by claim 15 of US 12236867 in view of Zhang et al.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 8 and 13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang et al. (US 2021/0027706 A1).
As to claim 1, Zhang et al. teaches a pixel driving circuit (Fig. 3), comprising:
a storage capacitor (capacitor Cst in Fig. 3) comprising a first capacitor electrode (first electrode of capacitor Cst in Fig. 3) and a second capacitor electrode (second electrode of capacitor Cst in Fig. 3);
a driving transistor (transistor M0 in Fig. 3) configured to generate a driving current ([0056];[0066-0067]: current generated by driving transistor M0);
a switch (transistor M3 in Fig. 3) configured to control connection or disconnection (see Fig. 5A during the reset stage T1, signals SC3 is high, which turns off p-type transistor M3 in Fig. 3. At stage T3, signal SC3 is low, and transistor M3 is conducted) between a gate electrode of the driving transistor (transistor M0 in Fig. 3) and the first capacitor electrode (first electrode of capacitor Cst in Fig. 3), and configured to render the gate electrode of the driving transistor (M0 in Fig. 3) floating during a reset phase of operation of the pixel driving circuit (see Fig. 5A during the reset stage T1, signals SC1 and SC3 are high, which turns off p-type transistors M5 and M3 in Fig. 3, and renders the gate electrode of driving transistor M0 in Fig. 3 floating); and
a reset transistor (transistor M4 in Fig. 3) having a first electrode connected to an initialization signal line (VINIT line in Fig. 3), a second electrode connected to the first capacitor electrode (first electrode of capacitor Cst in Fig. 3: note that the claim does not recite “directly” connected. All of the elements in Fig. 3 are connected to each other);
wherein the switch comprises a transistor (transistor M3 in Fig. 3) comprising a first electrode connected to the first capacitor electrode (first electrode of capacitor Cst in Fig. 3), a second electrode connected to a gate electrode of the driving transistor (transistor M0 in Fig. 3), and a gate electrode connected to a scan line (line SC3 in Fig. 3);
the reset transistor (transistor M4 in Fig. 3) is an n-type transistor ([0080]: transistor M4 is a P-type or an N-type transistor, there is no restriction herein); and
the driving transistor (transistor M0 in Fig. 3) and the transistor of the switch (transistor M3 in Fig. 3) are p-type transistors (Fig. 3 shows transistors M0 and M3 are p-type transistors).
As to claim 2, Zhang et al. teaches the pixel driving circuit of claim 1, wherein the switch (transistor M3 in Fig. 3) is configured to electrically disconnect the gate electrode of the driving transistor (transistor M0 in Fig. 3) from the first capacitor electrode (first electrode of capacitor Cst in Fig. 3) for a first period of time during operation of the pixel driving circuit (see Fig. 5A, at stage T1, signal SC3 is high and transistor M3 is disconnected) and to electrically connect the gate electrode of the driving transistor (transistor M0 in Fig. 3) to the first capacitor electrode (first electrode of capacitor Cst in Fig. 3) for a second period of time during operation of the pixel driving circuit (Fig. 5A shows signal SC3 is low during stage T3 which turns on p-type transistor M3 in Fig. 3).
As to claim 3, Zhang et al. teaches the pixel driving circuit of claim 2, wherein the first period of time comprises at least a portion of the reset phase of operation of the pixel driving circuit ([0090]; Fig. 5A shows during reset phase T1, signal SC3 is 1, which turns off p-type transistor M3 in Fig. 3), and the second period of time comprises at least a portion of a data write phase of the operation (Fig. 5A shows signal SC1 is low during stage T3 which turns on p-type transistor M5 in Fig. 3, and signal SC3 is low during stage T3 which turns on p-type transistor M3 in Fig. 3).
As to claim 4, Zhang et al. teaches the pixel driving circuit of claim 1, wherein the reset transistor (transistor M4 in Fig. 3) is configured to initialize the first capacitor electrode (first electrode of capacitor Cst in Fig. 3) in a reset phase of the operation (Fig. 5A shows during stage T1, signal SC2 is low which turns on transistor M4 directly connected to first electrode of capacitor Cst in Fig. 3); wherein the switch (transistor M3 in Fig. 2) is configured to electrically disconnect ([0090]; Fig. 5A shows signal SC3 is high during stage t1, transistor T3 is disconnected) the gate electrode of the driving transistor (transistor M0 in Fig. 3) from the first capacitor electrode (first electrode of capacitor Cst in Fig. 3; note that the claim does not recite “directly” connected) during at least a portion of a period in which the reset transistor (transistor M4 in Fig. 3) is turned on ([0090]; at stage T1, signal SC2 is low which turns on transistor M4 in Fig. 3) . As to claim 5, Zhang et al. teaches the pixel driving circuit of claim 1, further comprising a data write transistor (transistor M5 in Fig. 3) configured to allow a data signal to pass through in a data write phase of the operation (Fig. 5A, when signal SC1 is low, data signal DA is provided for the gate of the driving transistor M0 by the conducted switching transistor M5 in Fig. 3); wherein a first electrode of the data write transistor (transistor M5 in Fig. 3) is connected to a data line (line of data signal DA in Fig. 3); a gate electrode of the data write transistor (transistor M5 in Fig. 3) is connected to a gate line (line of signal SC1 in Fig. 3) ; and the switch (transistor M3 in Fig. 3) is configured to electrically connect the gate electrode of the driving transistor (transistor M0 in Fig. 3) to the first capacitor electrode (capacitor Cst in Fig. 3) during at least a portion of a period in which the data write transistor (transistor M5 in Fig. 3) is turned on (Fig. 5A shows signal SC1 is low during stage T3 which turns on p-type transistor M5 in Fig. 3, and signal SC3 is low during stage T3 which turns on p-type transistor M3 in Fig. 3). As to claim 6, Zhang et al. teaches the pixel driving circuit of claim 1, further comprising: a data write transistor (transistor M5 in Fig. 3) having a first electrode connected to a data line (line of data signal DA in Fig. 3), and a gate electrode (gate electrode of transistor M5 in Fig. 3) connected to a gate line (line of signal SC1 in Fig. 3); a first transistor (transistor M1 in Fig. 3) having a first electrode connected to a second electrode of the driving transistor (second electrode of transistor M0 in Fig. 3), a gate electrode (gate electrode of transistor M4 in Fig. 3) connected to a light emission control signal line (SC1 line in Fig. 3), and a second electrode (second electrode of transistor M1 in Fig. 3) connected to an anode of a light emitting element (light emitting element L in Fig. 3; Note that the claim does not recite “directly” connected. All of the elements of Fig. 3 are connected to each other); and a second transistor (transistor M2 in Fig. 3) having a first electrode connected to the first capacitor electrode (first electrode of capacitor Cst in Fig. 3; Note that the claim does not recite “directly” connected. All of the elements of Fig. 2 are connected to each other), and a second electrode (second electrode of transistor M2 in Fig. 3) connected to the second electrode of the driving transistor (second electrode of transistor M0 in Fig. 3). As to claim 8, Zhang et al. teaches a display panel (Abstract: display panel), comprising:the pixel driving circuit of claim 1 (see rejection for claim 1) ; anda light emitting element (light emitting element L in Fig. 3) connected to the pixel driving circuit (Fig. 3;[0056]: drive the light emitting device L to emit light). As to claim 13, Zhang et al. teaches the display panel of claim 8, wherein the scan line is a light emission control signal line of a previous stage (line SC3 in Fig. 3; FIG. 5A shows a reset stage T1, a threshold compensation stage T2 and a light emitting stage T3. At reset stage T1, SC3 is equal to 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 2021/0027706 A1) in view of Chaji (US 2013/0300724 A1).
As to claim 14, Zhang et al. teaches a method of driving a display panel (Abstract: display panel), comprising: electrically disconnecting a gate electrode of a driving transistor (transistor M0 in Fig. 3) from a first capacitor electrode of a storage capacitor (first capacitor electrode of transistor Cst) for a first period of time during operation of a pixel driving circuit (see Fig. 5A during the reset stage T1, signal SC3 is high, which turns off p-type transistor M3 in Fig. 3); and electrically connecting the gate electrode of the driving transistor (transistor M0 in Fig. 3) to the first capacitor electrode (first capacitor electrode of transistor Cst) for a second period of time during operation of the pixel driving circuit (see Fig. 5A, at stage T3, signal SC3 is low, transistor M3 is conducted); wherein the pixel driving circuit (Fig. 3) includes: the storage capacitor (capacitor Cst in Fig. 3) comprising the first capacitor electrode (first electrode of capacitor Cst in Fig. 3) and a second capacitor electrode (second electrode of capacitor Cst in Fig. 3);
the driving transistor (transistor M0 in Fig. 3) configured to generate a driving current ([0056];[0066-0067]: current generated by driving transistor M0);
a switch (transistor M3 in Fig. 3) configured to control connection or disconnection (see Fig. 5A during the reset stage T1, signals SC3 is high, which turns off p-type transistor M3 in Fig. 3. At stage T3, signal SC3 is low, and transistor M3 is conducted) between a gate electrode of the driving transistor (transistor M0 in Fig. 3) and the first capacitor electrode (first electrode of capacitor Cst in Fig. 3),and
a reset transistor (transistor M4 in Fig. 3) having a first electrode connected to an initialization signal line (VINIT line in Fig. 3), a second electrode connected to the first capacitor electrode (first electrode of capacitor Cst in Fig. 3; note that the claim does not recite “directly” connected. All of the elements in Fig. 3 are connected to each other);
wherein the switch comprises a transistor (transistor M3 in Fig. 3) comprising a first electrode connected to the first capacitor electrode (first electrode of capacitor Cst in Fig. 3), a second electrode connected to a gate electrode of the driving transistor (transistor M0 in Fig. 3), and a gate electrode connected to a scan line (line SC3 in Fig. 3);
the reset transistor (transistor M4 in Fig. 3) is an n-type transistor ([0080]: transistor M4 is a P-type or an N-type transistor, there is no restriction herein); and
the driving transistor (transistor M0 in Fig. 3) and the transistor of the switch (transistor M3 in Fig. 3) are p-type transistors ([0066]: transistor M0 is p-type transistor; [0076]: transistor M3 is P-type of transistor), wherein the method further comprises rendering, by the switch (transistor M3 in Fig. in Fig. 3), the gate electrode of the driving transistor (transistor M0 in Fig. 3) floating during a reset phase of operation of the pixel driving circuit (see Fig. 5A during the reset stage T1, signals SC1 and SC3 are high, which turns off p-type transistors M5 and M3 in Fig. 3, and renders the gate electrode of driving transistor M0 in Fig. 3 floating), but does not explicitly disclose in a present frame of image display.
However, Chaji et al. discloses in a present frame of image display ([0004]: frame of the video feed being displayed). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Zhang et al. by incorporating a present frame of image display as taught by Chaji et al. in order to display a video feed.
As to claim 15, Zhang et al. in view of Chaji et al. teaches the method of claim 14, wherein the first period of time comprises at least a portion of the reset phase of operation of the pixel driving circuit (Zhang et al., [0090]; Fig. 5A shows during reset phase T1, signal SC3 is 1, which turns off p-type transistor M3 in Fig. 3), and the second period of time comprises at least a portion of a data write phase of the operation (Zhang et al., Fig. 5A shows signal SC1 is low during stage T3 which turns on p-type transistor M5 in Fig. 3, and signal SC3 is low during stage T3 which turns on p-type transistor M3 in Fig. 3).
As to claim 16, Zhang et al. teaches the method as discussed above, but does not explicitly disclose wherein the reset phase comprises a first sub-phase and a second sub-phase, the first sub-phase being earlier in time than the second sub-phase; the first period of time comprises only the first sub-phase; and the second period of time comprises the second sub-phase and at least a portion of the data write phase. However, Chaji et al. teaches wherein the reset phase comprises a first sub-phase (342 in Fig. 4B) and a second sub-phase (344 in Fig. 4B), the first sub-phase (342 in Fig. 4B) being earlier in time than the second sub-phase (344 in Fig. 4B);
the first period of time comprises only the first sub-phase (342 in Fig. 4B); and
the second period of time comprises the second sub-phase (344 in Fig. 4B) and at least a portion of the data write phase ([0070]: data line 22j is set to a reference voltage VREF).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Zhang et al. such that the reset phase comprises
a first sub-phase and a second sub-phase, the first sub-phase being earlier in time than the second sub-phase, the first period of time comprises only the first sub-phase, and the second period of time comprises the second sub-phase and at least a portion of the data write phase as taught by Chaji in order to enhance contrast ratio.
Response to Arguments
Applicant's arguments filed 07/03/2026 have been fully considered but they are not persuasive.
Examiner respectfully disagrees with the applicant’s argument that “a terminal disclaimer regarding U.S. Patent No. 12,236,867 has been submitted herewith” and “accordingly, applicants respectfully request that the rejection be withdrawn.” (pages 6-7 of applicant’s remarks).
Applicant has not submitted a terminal disclaimer regarding U.S. Patent No. 12,236,867. Therefore, claims 1-17 stand rejected on the ground of nonstatutory double patenting as noted in the office action above.
Examiner respectfully disagrees with the applicant’s argument that Zhang does not disclose or suggest a switch configured to render the gate electrode of the driving transistor floating during a reset phase.
Zhnag teaches a switch (transistor M3 in Fig. 3) configured to render the gate electrode of the driving transistor (M0 in Fig. 3) floating during a reset phase of operation of the pixel driving circuit (see Fig. 5A during the reset stage T1, signals SC1 and SC3 are high, which turns off p-type transistors M5 and M3 in Fig. 3, and renders the gate electrode of driving transistor M0 in Fig. 3 floating).
Therefore, Zhang teaches applicant’s claimed invention as noted in the office action above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STACY KHOO whose telephone number is (571)270-3698. The examiner can normally be reached Mon-Fri 8:00 am-5:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Eason can be reached at 571-270-7230. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STACY KHOO/Primary Examiner, Art Unit 2624
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