Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 16-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 16 sets forth “and a through via vertically penetrating at least a portion of the substrate.”
The use of “a through” as a noun and as a separate claim limitation is unclear and does not appear to be defined by the written description. Further clarification is required to understand the meaning of such a term as used in the claim.
Claim 17 is rejected as dependent upon claim 16.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 5, and 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20030159079 A1 (Harima) in view of IN 201824043162 A (Lee, et al., hereinafter Lee).
Regarding claim 1, Harima teaches an integrated circuit package, comprising: (Harima, FIG. 1-6) a substrate; a first semiconductor chip disposed on the substrate (Harima, [0005]: “A semiconductor device according to embodiments of the present invention includes a semiconductor substrate, a first circuit disposed on the semiconductor substrate,”) and configured to output a first clock signal (Harima, [0005]: “and configured to output a first output signal delayed by a first delay time from the first clock signal”) and a first data signal; (Harima, “first output signal”) a delay circuit configured to delay at least one of the first clock signal and the first data signal (Harima, [0005]: “and configured to output a first output signal delayed by a first delay time from the first clock signal,”), and to output a second clock signal (Harima, [0005]: “configured to output a second clock signal delayed from the first clock signal”), and a second data signal based on the first clock signal and the first data signal (Harima, [0030-0031]: “…amplifies the cell data signal CD synchronously with the input clock delay signal CKd. By increasing or decreasing the delay time T1 by the setting circuit 3 of the delay time T1, it is possible to change the timing for detecting the cell data signal CD. The amplified cell data signal CD is output to a register circuit 11 as a data signal D. The register circuit 11 outputs the data signal D to an output buffer 12 synchronously with a clock delay signal having a constant delay time, from the clock signal CK0 by a buffer 16. The output buffer 12 outputs the input data signal D to a pad 19.”)
Harima does not appear to explicitly teach and a second semiconductor chip disposed on the substrate to be horizontally spaced apart from the first semiconductor chip and configured to receive the second clock signal and the second data signal.
Lee cures the deficiencies of Harima. Lee (FIGS. 1-11) teaches a second semiconductor chip (Lee, “first and second semiconductor chips 830a and 830b”) disposed on the substrate to be horizontally spaced apart from the first semiconductor chip (Lee, [0125]: “The first and second semiconductor chips 830a and 830b may be disposed or arranged on the same plane and may be spaced apart from each other.”) and configured to receive the second clock signal and the second data signal. (Lee, [0126]: “The second semiconductor chip 830b may include a single-ended data transmitter 832b and a single-ended data receiver 834b that are formed or disposed in the second region REG2b. Each of the single-ended data transmitters 832a and 832b may be the data transmitter 200 in FIG. 2 or the data transmitter 200a in FIG. 6…”)
Both Harima and Lee are directed to integrated circuits and methods for transmitting and receiving data, including semiconductor packages. It would have been obvious to one of ordinary skill in the art to modify the apparatus of Harima with the second semiconductor chip configured to receive signals of Lee with the motivation of implementing an additional semiconductor chip and increasing functionality of the apparatus.
Regarding claim 5, Harima/Lee teaches the integrated circuit package of claim 1, further comprising: an active interposer disposed between the substrate and the first semiconductor chip and configured to mount the first and second semiconductor chips, wherein the active interposer includes the delay circuit. (Lee, [0130]: “The plurality of semiconductor devices 920 and 930 may be mounted or disposed on the substrate 910. For example, the substrate 910 may be a printed circuit board (PCB) or a flexible PCB (FPCB). The plurality of semiconductor devices 920 and 930 may be connected to each other via the plurality of transmission lines 940.”)
Regarding claim 14, Harima teaches an integrated circuit package, comprising: (Harima, FIG. 1-6) a first semiconductor chip configured to output a first clock signal (Harima, [0005]: “and configured to output a first output signal delayed by a first delay time from the first clock signal”) and a first data signal; (Harima, “first output signal”) and including a delay circuit configured to: delay at least one of the first clock signal and the first data signal, (Harima, [0005]: “and configured to output a first output signal delayed by a first delay time from the first clock signal,”) and output a second clock signal (Harima, [0005]: “configured to output a second clock signal delayed from the first clock signal”) and a second data signal; (Harima, [0030-0031]: “…amplifies the cell data signal CD synchronously with the input clock delay signal CKd…)
Harima does not appear to explicitly teach an active interposer connected to the first semiconductor chip, and a second semiconductor chip disposed on the active interposer to be horizontally spaced apart from the first semiconductor chip, and configured to receive the second clock signal and the second data signal.
Lee cures the deficiencies of Harima. Lee (FIGS. 1-11) teaches an active interposer connected to the first semiconductor chip, (Lee, [0130]: “The plurality of semiconductor devices 920 and 930 may be mounted or disposed on the substrate 910. For example, the substrate 910 may be a printed circuit board (PCB) or a flexible PCB (FPCB). The plurality of semiconductor devices 920 and 930 may be connected to each other via the plurality of transmission lines 940…”)
and a second semiconductor chip disposed on the active interposer to be horizontally spaced apart from the first semiconductor chip, (Lee, [0125]: “The first and second semiconductor chips 830a and 830b may be disposed or arranged on the same plane and may be spaced apart from each other.”) and configured to receive the second clock signal and the second data signal. (Lee, [0126]: “The second semiconductor chip 830b may include a single-ended data transmitter 832b and a single-ended data receiver 834b that are formed or disposed in the second region REG2b. Each of the single-ended data transmitters 832a and 832b may be the data transmitter 200 in FIG. 2 or the data transmitter 200a in FIG. 6…”)
Both Harima and Lee are directed to integrated circuits and methods for transmitting and receiving data, including semiconductor packages. It would have been obvious to one of ordinary skill in the art to modify the apparatus of Harima with the second semiconductor chip configured to receive signals of Lee with the motivation of implementing an additional semiconductor chip and increasing functionality of the apparatus.
Regarding claim 15, Harima/Lee teaches the integrated circuit package of claim 14, further comprising: first and second memory dies disposed perpendicular to each other on the second semiconductor chip, (Lee, [0133]: “Referring to FIG. 12, a storage device 1000 may include a plurality of nonvolatile memory devices 1100 and a controller 1200.”) wherein the first semiconductor chip is a logic chip, (Lee, [0007-0009]) and wherein the second semiconductor chip is a buffer die with respect to the first and second memory dies. (Lee, [0134]: “The controller 1200 may be connected to the nonvolatile memory devices 1100 via a plurality of channels CH1, CH2, CH3, …, CHi. The controller 1200 may include one or more processors 1210, a buffer memory 1220,”)
Claim(s) 6-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20030159079 A1 (Harima) in view of IN 201824043162 A (Lee, et al., hereinafter Lee) in view of US 20180040590 A1 (Chang, et al., hereinafter Chang).
Regarding claim 6, Harima/Lee teaches the integrated circuit package of claim 1, but does not appear to teach further comprising: a bridge chip connected to the first and second semiconductor chips and including the delay circuit, wherein the bridge chip is disposed in a cavity formed on a first surface of the substrate.
Chang cures the deficiencies of Harima/Lee and teaches the structure of such a bridge chip. Chang teaches (Chang, FIG. 1-8) a bridge chip connected to the first and second semiconductor chips and including the delay circuit, wherein the bridge chip is disposed in a cavity formed on a first surface of the substrate. (Chang, [0006]: “Embodiments include a semiconductor package comprising: a substrate including a cavity; a first semiconductor chip disposed in the cavity, the first semiconductor chip including a first pad, a second pad, and a third pad disposed on an upper surface of the first semiconductor chip, wherein the second pad and the third pad different from the first pad; a metal line disposed on the substrate and the first semiconductor chip and electrically connected to the first pad of the first semiconductor chip and the substrate; a second semiconductor chip disposed on the first semiconductor chip and electrically connected to the first semiconductor chip through a first connection terminal connected to the second pad;”)
Both Harima/Lee and Chang are directed to semiconductor packages and methods for fabricating the same. It would have been obvious to one of ordinary skill in the art to modify the teachings of Harima/Lee with the bridge chip structure as set forth by Chang with the motivation of modifying the semiconductor device.
Regarding claim 7, Harima/Lee/Chang teaches the integrated circuit package of claim 6, wherein the first and second semiconductor chips are mounted on the substrate. (Chang, [0006]: “ a second semiconductor chip disposed on the first semiconductor chip and electrically connected to the first semiconductor chip through a first connection terminal connected to the second pad; and a third semiconductor chip disposed on the first semiconductor chip, spaced apart from the second semiconductor chip, and electrically connected to the first semiconductor chip through a second connection terminal connected to the third pad, wherein the metal line does not contact the first connection terminal and the second connection terminal.”)
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20030159079 A1 (Harima) in view of IN 201824043162 A (Lee, et al., hereinafter Lee) in view of US 20230026676 A1 (Cheng, et al., hereinafter Cheng).
Regarding claim 8, Harima/Lee teaches the integrated circuit package of claim 1, but does not appear to explicitly teach wherein each of the first and second semiconductor chips is a chiplet including at least one function block.
However, Cheng teaches wherein each of the first and second semiconductor chips is a chiplet including at least one function block. (Cheng, [0021]: “The integrated chip structure comprises a plurality of chiplets formed by way of a different fabrication processes. The plurality of chiplets are coupled together by way of one or more inter-chiplet interconnects. Respective ones of the plurality of chiplets predominately comprise a single type of device that is different than that of the other chiplets.”)
Both Harima/Lee and Cheng are directed to semiconductor devices. It would have been obvious to one of ordinary skill in the art to modify the teachings of Harima/Lee with the chiplet structure including a function block as taught by Cheng with the motivation of adding functionality to the semiconductor device.
Allowable Subject Matter
Claims 2-4, 9-13, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 2, Harima/Lee teaches the integrated circuit package of claim 1, but does not appear to explicitly teach further comprising: a data checker configured to receive the second clock signal and the second data signal, and perform an operation to check a data-valid section with respect to the second data signal.
Although the concept of a “data checker” is well-known in the art, including an apparatus configured to receive any number of signals, it does not appear to be taught to “perform an operation to check a data-valid section with respect to the second data signal” in combination with all other limitations of the claim.
Claims 3-4 are dependent upon claim 2.
Regarding claim 9, Harima/Lee teaches the integrated circuit package of claim 1, but does not appear to explicitly teach wherein: the first data signal includes a third data signal and a fourth data signal each including 1 bit of data, the second data signal includes a fifth data signal and a sixth data signal output from the delay circuit based on the third and fourth data signals, and the delay circuit includes a first delay circuit configured to output the fifth data signal based on the third data signal, a second delay circuit configured to output the sixth data signal based on the fourth data signal, and a clock delay circuit configured to output the second clock signal based on the first clock signal.
Claims 10-13 are dependent upon claim 9.
Regarding claim 18, Harima/Lee teaches the integrated circuit package of claim 14, but does not appear to teach wherein the active interposer further includes a data checker configured to: receive the second clock signal and the second data signal, and perform an operation to check a data-valid section with respect to the second data signal.
Claims 19-20 allowed.
The prior art of record does not appear to teach an operation method of an integrated circuit package, the operation method comprising: receiving an input/output tuning command from a first semiconductor chip mounted on a substrate; receiving a first clock signal and a first data signal from the first semiconductor chip, in response to the reception of the input/output tuning command; performing an input/output tuning operation by delaying at least one of the first clock signal and the first data signal to output a second clock signal and second data signal; checking a data-valid section with respect to the second data signal, based on the second clock signal and the second data signal; setting a delay setting value with respect to the input/output tuning operation, in response to result of the checking; and outputting the second clock signal and the second data signal, based on the delay setting value.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL J KING whose telephone number is (703)756-1232. The examiner can normally be reached M-F 9am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL JOHN KING/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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