DETAILED ACTION
This action is responsive to the following: The application and information disclosure statement filed on January 25, 2025.
Claims 1-20 are pending. Claims 1, 11, and 16 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on January 25, 2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 6, and 16-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al (US 20130100725 A1).
Regarding Independent Claim 1, Kim teaches A memory device comprising:
a memory cell array (Fig. 2: 200) including a first input/output unit (para 9 “an NVR memory is provided that may have a first array of bitcells (I/O)”) and a second input/output unit (para 9 “and may further have a second I/O”), each of the first input/output unit and the second input/output unit including a first region (fig. 1 and 2: 102) including a plurality of memory cells (Fig. 1: 102) (Fig. 1: 112, 118) and a second region (fig. 1: 104) including dummy memory cells (fig. 1: 136, 138, 140, 142);
a first sensing circuit (para 9 “a first array of bitcells (I/O) having a first reference cell, a first reference cell selectable link from the first reference cell to a first I/O reference line, and a first sense amplifier coupled to the first I/O reference line”) configured to determine data stored in the memory cells (Fig. 1: 102) of the first input/output unit based on a first reference resistance (para 9 “a first sense amplifier coupled to the first I/O reference line”);
a second sensing circuit (para 9 “a second I/O having a second reference cell, a second reference cell selectable link from the second reference cell to a second I/O reference line, and a second sense amplifier (Fig. 1: 130) coupled to the second I/O reference line.”)configured to determine data stored in the memory cells (Fig. 1: 102) of the second input/output unit based on a second reference resistance (para 9 “a second sense amplifier (Fig. 1: 130) coupled to the second I/O reference line.”); and
a control logic circuit (Fig. 9: 904) configured to control a value of the first reference resistance and a value of the second reference resistance,
wherein the value of the first reference resistance and the value of the second reference resistance are different from each other (para 36 “It will also be assumed that the first reference resistance memory element 136 has been set at the magnetization state exhibiting Rlow, and the second reference resistance memory element 138 has been set at the magnetization state exhibiting Rhigh.”).
Regarding Claim 2, Kim teaches the limitations of claim 1. Kim further teaches wherein the first sensing circuit (para 9 “a first array of bitcells (I/O) having a first reference cell, a first reference cell selectable link from the first reference cell to a first I/O reference line, and a first sense amplifier coupled to the first I/O reference line”) includes:
a first current source (fig. 1: 132) configured to generate a first read current;
a second current source (fig. 1: 152, 154) configured to generate a second read current; and
a first sense amplifier (Fig. 1: 130) including a first node (Fig. 1: 130A) connected to a first bit line (Fig. 1: 122) connected to memory cells (Fig. 1: 102) of the first input/output unit and a second node (Fig. 1: 130B) connected to a first reference bit line (Fig. 1: 156) connected to dummy memory cells (fig. 1: 136, 138, 140, 142) of the first input/output unit, and the first sense amplifier (Fig. 1: 130) configured to amplify a difference between a voltage of the first node (Fig. 1: 130A) and a voltage of the second node (Fig. 1: 130B), and
wherein the first read current is applied to the first bit line (Fig. 1: 122) and the second read current is applied to the first reference bit line (Fig. 1: 156).
Regarding Claim 3, Kim teaches the limitations of claim 2. Kim further teaches wherein the second sensing circuit (para 9 “a second I/O having a second reference cell, a second reference cell selectable link from the second reference cell to a second I/O reference line, and a second sense amplifier (Fig. 1: 130) coupled to the second I/O reference line.”)includes:
a third current source (Fig. 1: 132) configured to generate a third read current;
a fourth current source (fig. 1: 152, 154) configured to generate a fourth read current; and
a second sense amplifier (Fig. 1: 130) including a third node (Fig. 1: 130A) connected to a second bit line (Fig. 1: 122) connected to memory cells (Fig. 1: 102) of the second input/output unit and a fourth node (Fig. 1: 130B) connected to a second reference bit line (Fig. 1: 156) connected to dummy memory cells (fig. 1: 136, 138, 140, 142) of the second input/output unit, and the second sense amplifier (Fig. 1: 130) configured to amplify a difference between a voltage of the third node (Fig. 1: 130A) and a voltage of the fourth node (Fig. 1: 130B), and
wherein the third read current is applied to the second bit line (Fig. 1: 122) and the fourth read current is applied to the second reference bit line (Fig. 1: 156).
Regarding Claim 4, Kim teaches the limitations of claim 1. Kim further teaches , further comprising:
a first write driver configured to perform a program operation on memory cells (Fig. 1: 102) of the first region of the first input/output unit under control of the control logic circuit; and
a second write driver configured to perform a program operation on memory cells (Fig. 1: 102) of the first region of the second input/output unit under control of the control logic circuit.
(para 35 “To avoid unnecessary complexity in the figures and unnecessary accompanying description, FIG. 1 omits explicit depiction of the write circuitry for setting the magnetization state of the resistive memory element 112 and the reference resistive memory elements 136 and 138. As known to persons of ordinary skill in the NVR memory art, data is written to an NVR bit cell such as 102 by injecting current according to various parameters, established in part by the particular structure and technology of the resistance memory elements. Such persons, having view of the present disclosure, can readily implement means for writing to, i.e., setting magnetization states of resistive memory elements such as 112, and reference resistive memory elements such as 136 and 138, to practice according to the present embodiments and, therefore, further detailed description is omitted.”)
Regarding Claim 6, Kim teaches the limitations of claim 1. Kim further teaches wherein each of the plurality of memory cells (Fig. 1: 102) includes:
a cell transistor (Fig. 1: 118) including a first end connected to a source line (Fig. 1: 125) and a gate electrode connected to a word line (Fig. 1: 120); and
a magnetic tunneling junction element (Fig. 1: 112; para 31 “a resistive memory element 112 that may be switched into two or more different magnetization states, each having a distinct resistance. The resistive memory element may, for example, be a magnetic tunneling junction (MTJ) element.”) including a first end connected to a second end of the cell transistor (Fig. 1: 118) and a second end connected to a bit line (Fig. 1: 122).
Regarding Independent Claim 16, Kim teaches A memory device comprising:
a memory cell array (Fig. 2: 200) including a plurality of first cell strings (Fig. 2: 204-1, 204-8), a plurality of second cell strings (Fig. 2: 204-1, 204-8), a first dummy cell string (Fig. 4: 418-1), and a second dummy cell string (Fig. 4: 418-2);
a first sense amplifier (Fig. 1: 130) including a first input terminal (Fig. 1: 130a) to which first ends of the plurality of first cell strings (Fig. 2: 204-1, 204-8) are connected and a second input terminal (Fig. 1: 130b) to which a first end of the first dummy cell string is connected through a first reference resistance;
a second sense amplifier (Fig. 1: 130) including a first input terminal (Fig. 1: 130a) to which first ends of the plurality of second cell strings (Fig. 2: 204-1, 204-8) are connected and a second input terminal (Fig. 1: 130b) to which a first end of the second dummy cell string is connected through a second reference resistance;
a first current source (fig. 1: 132) circuit configured to provide a first input current to the first sense amplifier (Fig. 1: 130); and
a second current source (fig. 1: 152, 154) circuit configured to provide a second input current to the second sense amplifier (Fig. 1: 130),
wherein a value of the first reference resistance and a value of the second reference resistance are different from each other (para 36 “It will also be assumed that the first reference resistance memory element 136 has been set at the magnetization state exhibiting Rlow, and the second reference resistance memory element 138 has been set at the magnetization state exhibiting Rhigh.”).
Regarding Claim 17, Kim teaches the limitations of claim 16. Kim further teaches wherein the value of the first reference resistance is obtained based on:
the number of fail bits counted from memory cells (Fig. 1: 102) of the first cell strings and the second cell strings based on a plurality of resistances having different values from each other, and
the number of fail bits counted from memory cells (Fig. 1: 102) of the first cell strings based on a first set of resistances among the plurality of resistances.
Regarding Claim 18, Kim teaches the limitations of claim 16. Claim 18 is rejected for the same reasons as claim 4.
Regarding Claim 19, Kim teaches the limitations of claim 16. Claim 19 is rejected for the same reasons as claim 6.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 20130100725 A1) in view of Ramanan et al (US 20220383925 A1).
Regarding Claim 5, Kim teaches the limitations of claim 4.
Kim fails to teach source line drivers.
Ramanan teaches further teaches further comprising:
a first source line driver (Fig. 2: 254) configured to perform the program operation on the memory cells of the first region of the first input/output unit under control of the control logic circuit; and
a second source line driver (Fig. 2: 258) configured to perform the program operation on the memory cells of the first region of the second input/output unit under control of the control logic circuit.
Ramanan teaches that it useful to use as source line driver in resistive memory because “a source line driver (e.g. 254) couples the source line (e.g. SL00) of the column to the other write voltage of VDD or VSS, depending on the data value being written as determined by the write data lines (WR&D0-WR&DK) and complementary write data lines (WR&*D0-WR&*DK). During the write operation, the select transistor (e.g. 232) is made conductive by assertion of the appropriate word line to provide a voltage differential across the resistive storage element (e.g. 234) whose polarity determines whether a 1 or 0 is written to the cell.” This would therefore represent an obvious improvement if the resistive elements caused for this functionality.
Therefore, it would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Ramanan to the teachings of Kim to produce a memory with source line drivers for performing program operations.
Claims 7-8 and 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 20130100725 A1) in view of Yun et al (US 20250111883 A1).
Regarding Claim 7, Kim teaches the limitations of claim 1. Kim fails to teach counting failed bits.
Yun teaches wherein the value of the first reference resistance is obtained based on a first counting value (Fig. 6B: 613) and a second counting value (Fig 6B: 614),
wherein the first counting value is obtained by performing a fail bit counting operation on memory cells of the memory cell array based on a plurality of resistances having different values from each other (Fig. 9: 910), and
wherein the second counting value is obtained by performing a fail bit counting operation on memory cells of the first input/output unit based on a first set of resistances among the plurality of resistances (Fig. 9: 950).
Pyo states in para 4-5 “Many MRAM devices have a relatively small resistance separation between a high resistive state associated with a data “1” value and a low resistive state associated with a data “0” value. Due to the small resistance separation, setting the reference resistance is very challenging. Some MRAM devices have included trim circuitry to adjust the reference resistance used by the MRAM devices to differentiate between high resistive states and low resistive states of its memory cells. The trim circuitry can receive an external input corresponding to a reference trim, for example, from test engineers, which can adjust the reference resistance that the MRAM devices compares against the resistance values read from its memory cells to determine whether the memory cells stored data “1” values or data “0” values. Test engineers typically determine values for reference trims in MRAM devices through extensive testing over different environmental conditions, such as temperature variations, to identify a full distribution of bit properties for the MRAM device before performing engineering analysis to identify the reference trims. This MRAM device testing has proven costly or impractical in larger MRAM implementations. A memory built-in self-test system may be employed to perform reference trim searching and setting. This process is performed automatically on a chip, requiring minimum external intervention. The reference trim can not only be set right after manufacturing but also be adjusted while being installed in system.” Thus, implementing this test to trim reference resistance values represents an obvious improvement over alternative methods.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Pyo to the teachings of Kim to produce a MRAM memory that uses failed bit counts to determine the values of reference resistances used in sensing.
Regarding Claim 8, Kim teaches the limitations of claim 7. Pyo further teaches wherein the fail bit counting operation on the memory cells of the first input/output unit based on the first set of resistances is performed in a linear search method or a binary search method (para 9 “The search sequence may be a binary search sequence, each step of the binary search sequence determining one bit of the second intermediate boundary value of the reference trim.”).
Regarding Independent Claim 11, Kim teaches a memory device which includes a memory cell array (Fig. 2: 200) including a plurality of input/output units (Fig. 1: 100) and a plurality of memory cells (Fig. 1: 102),
However, Kim fails to teach a method of programming where failed bits are counted and in order to set the reference resistance values.
Yun teaches programming the plurality of memory cells of the memory cell array to a first state (Fig. 8: 801);
first counting fail bits of the memory cells programmed to the first state by using a plurality of resistances having different values from each other and outputting first counting results based on the first counting of fail bits (Fig. 8: 802);
programming the plurality of memory cells of the memory cell array to a second state (Fig. 8: 803);
second counting fail bits of the memory cells programmed to the second state by using the plurality of resistances and outputting second counting results based on the second counting of fail bits (Fig. 8: 804);
selecting a value of a global reference resistance among the plurality of resistances, based on the first counting results and the second counting results;
programming memory cells of a first input/output unit among the plurality of input/output units to the first state (Fig. 8: 805);
third counting fail bits of the memory cells of the first input/output unit programmed to the first state by using a first set of resistances among the plurality of resistances and outputting third counting results based on the third counting of fail bits;
programming the memory cells of the first input/output unit to the second state (Fig. 9: 930);
fourth counting fail bits of the memory cells of the first input/output unit programmed to the second state by using the first set of resistances and outputting fourth counting results based on the fourth counting of fail bits (Fig. 9: 950); and
selecting a value of a local reference resistance among the first set of resistances, based on the third counting results and the fourth counting results (Fig. 9: 970).
Pyo states in para 4-5 “Many MRAM devices have a relatively small resistance separation between a high resistive state associated with a data “1” value and a low resistive state associated with a data “0” value. Due to the small resistance separation, setting the reference resistance is very challenging. Some MRAM devices have included trim circuitry to adjust the reference resistance used by the MRAM devices to differentiate between high resistive states and low resistive states of its memory cells. The trim circuitry can receive an external input corresponding to a reference trim, for example, from test engineers, which can adjust the reference resistance that the MRAM devices compares against the resistance values read from its memory cells to determine whether the memory cells stored data “1” values or data “0” values. Test engineers typically determine values for reference trims in MRAM devices through extensive testing over different environmental conditions, such as temperature variations, to identify a full distribution of bit properties for the MRAM device before performing engineering analysis to identify the reference trims. This MRAM device testing has proven costly or impractical in larger MRAM implementations. A memory built-in self-test system may be employed to perform reference trim searching and setting. This process is performed automatically on a chip, requiring minimum external intervention. The reference trim can not only be set right after manufacturing but also be adjusted while being installed in system.” Thus, implementing this test to trim reference resistance values represents an obvious improvement over alternative methods.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Pyo to the teachings of Kim to produce a MRAM memory that uses failed bit counts to determine the values of reference resistances used in sensing.
Regarding Claim 12, Kim and Yun teach the limitations of claim 11. Yun further teaches wherein the selecting of the value of the global reference resistance includes:
selecting, as the value of the global reference resistance, a value of a resistance corresponding to a smallest summation result among results of summing the first counting results and the second counting results for each of the plurality of resistances (Fig. 6B: 615).
Regarding Claim 13, Kim and Yun teach the limitations of claim 11. Yun further teaches wherein the selecting of the value of the local reference resistance includes:
selecting, as the value of the local reference resistance, a value of a resistance corresponding to a smallest summation result among results of summing the third counting results and the fourth counting results for each of the first set of resistances (Fig. 6B: 615).
Regarding Claim 14, Kim and Yun teach the limitations of claim 13. Yun further teaches comprising:
storing the selected value of the local reference resistance in the memory device (Fig. 9: 990).
Regarding Claim 15, Kim and Yun teach the limitations of claim 11. Kim further teaches wherein each of the plurality of memory cells (Fig. 1: 102) includes a magnetic tunnel junction element (Fig. 1: 112; para 31 “a resistive memory element 112 that may be switched into two or more different magnetization states, each having a distinct resistance. The resistive memory element may, for example, be a magnetic tunneling junction (MTJ) element.”).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 20130100725 A1) in view of Pyo et al (US 20190088322 A1).
Regarding Claim 9, Kim teaches the limitations of claim 1.
Kim fails to teach wherein the first reference resistance includes a plurality of first transistors and a plurality of first resistance elements respectively connected to the plurality of first transistors in parallel, and
wherein the second reference resistance includes a plurality of second transistors and a plurality of second resistance elements respectively connected to the plurality of second transistors in parallel.
Pyo teaches wherein the first reference resistance (Fig. 7B: 130a”) includes a plurality of first transistors (Fig. 7B: N1b-Nmb) and a plurality of first resistance elements (Fig. 7B: R1b-Rmb) respectively connected to the plurality of first transistors in parallel, and
wherein the second reference resistance (Fig. 7B: 130a”) includes a plurality of second transistors (Fig. 7B: N1b-Nmb) and a plurality of second resistance elements (Fig. 7B: R1b-Rmb) respectively connected to the plurality of second transistors in parallel.
Pyo teaches a reference resistance that has a value that can be tuned to desired setting by selecting certain transistors and thereby bypassing resistors in series and changing the effective resistance of the reference resistance. Thus, in tuning a reference in the even that cells are subject to certain external variations such as process or temperatures which might require a different reference value in order to accurately sense. Therefore, this represents an obvious improvement over a standard reference resistance with a fixed value.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Pyo to the teachings of Kim to produce a first and second references resistor consisting of resistance elements in parallel with transistors.
Allowable Subject Matter
Claims 10 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 10, Kim teaches the limitations of claim 9. Kim further teaches further comprising:
a one-time programmable (OTP) memory configured to store the value of the first reference resistance and the value of the second reference resistance.
Regarding Claim 20, Kim teaches the limitations of claim 16. Kim further teaches wherein each of memory cells (Fig. 1: 102) of the first dummy cell string and the second dummy cell string includes:
a cell transistor including a first end connected to a source line, a second end connected to a bit line, and a gate electrode connected to a word line.
Conclusion
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/JOSEPH FIDELIS STORMES/ Examiner, Art Unit 2825
/Donald HB Braswell/ Primary Examiner, Art Unit 2825
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