DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement submitted on 4 Jun 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “second BJT in a diode configuration comprising: an emitter terminal electrically coupled to the negative input terminal of the operational amplifier, the source terminal of the second PMOS” must be shown or the feature(s) canceled from the claim(s). The specification [0072] says, “a second BJT 771 in a diode configuration comprising an emitter terminal 771 e electrically coupled to the negative input terminal 775n of the operational amplifier 775, the drain terminal 777d of the second PMOS 777”, and Fig 7 confirms that the DRAIN of 777 is connected to Q2/771. Additionally, the specification [0084] says, “a second BJT 871…the drain terminal 877d of the second PMOS 877”, and Fig 8 confirms that the DRAIN of 877 is connected to Q2/871. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 1-20 are objected to because of the following informalities:
Claim 1, last line: recites the limitation "the base of the reference BJT". There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, Examiner assumes this means “the base terminal of the reference BJT” as is stated in claim 13.
Claims 7, 12 and 14: the limitation "base terminal" is a generic term that is used as part of multiple transistors. These terminals should have specific names, rather than repeat the exact same terminal name to make it clear that each terminal is distinct.
Claims 7 and 14: the limitation "emitter terminal" is a generic term that is used as part of multiple transistors. These terminals should have specific names, rather than repeat the exact same terminal name to make it clear that each terminal is distinct.
Claims 7, 11-12, and 14: the limitation "collector terminal" is a generic term that is used as part of multiple transistors. These terminals should have specific names, rather than repeat the exact same terminal name to make it clear that each terminal is distinct.
Claims 7: the limitation "output terminal" is a generic term that is used as part of multiple circuits. These terminals should have specific names, rather than repeat the exact same terminal name to make it clear that each terminal is distinct.
Claims 7 and 13-14: the limitation "gate terminal" is a generic term that is used as part of multiple transistors. These terminals should have specific names, rather than repeat the exact same terminal name to make it clear that each terminal is distinct.
Claims 7 and 13-14: the limitation "source terminal" is a generic term that is used as part of multiple transistors. These terminals should have specific names, rather than repeat the exact same terminal name to make it clear that each terminal is distinct.
Claims 7 and 13-14: the limitation "drain terminal" is a generic term that is used as part of multiple transistors. These terminals should have specific names, rather than repeat the exact same terminal name to make it clear that each terminal is distinct.
Claim 14, line 28: the limitation "couple" should be changed to “coupled”.
Claims 2-12 depend from Claim 1 and thus have at least the same defect(s).
Claims 14-18 depend from Claim 13 and thus have at least the same defect(s).
Claim 20 depends from Claim 19 and thus has at least the same defect(s).
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, 10, 12, and 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Motz (US 20220374037 A1).
Regarding Claim 1, Motz discloses a circuit (300, Fig 3) comprising: a reference bipolar junction transistor (BJT) comprising a base terminal, an emitter terminal, and a collector terminal (BJT 212, Fig 3), wherein a ratio of a collector current at the collector terminal and a base current at the base terminal is equal to a beta value ("β-drift effect (β=I.sub.C/I.sub.B denotes a current gain of a bipolar transistor)", [0010]); a resistive element having a first terminal and a second terminal, the second terminal electrically coupled to the emitter terminal of the reference BJT (342's bottom terminal is connected to the emitter of BJT 212, Fig 3); and a beta-compensated current generation circuit (220/222, Fig 3) configured to generate a beta-compensated current ("β-drift effect (β=I.sub.C/I.sub.B denotes a current gain of a bipolar transistor)", [0010]), based on a proportional to absolute temperature (PTAT) current ("In the case of a bandgap reference, it is possible to achieve low temperature drift by adding a proportional-to-absolute-temperature (PTAT) voltage to the base-emitter voltage of a bipolar transistor (BJT).", where amplifier 218 enforces the operation that flows to the resistor R1 and R1 turns the PTAT voltage into a current, Fig 3, [0003]), at the emitter terminal of the reference BJT ("the base currents of the replica bipolar transistors 222, 234 are fed directly into the respective emitter connections of the bipolar transistors 212, 214", [0062]), wherein the beta-compensated current is inversely proportional to the beta value (since I.sub.B of 222 is fed into 212 and β=I.sub.C/I.sub.B, then the base current I.sub.B=I.sub.C/β which is inversely proportional to β, [0003]), wherein a reference voltage is generated based on a voltage difference between the first terminal of the resistive element and the base [terminal] of the reference BJT (node 340 is resistor 342's first terminal and the base of BJT 212 is connected to ground/0V, so following KVL, the reference voltage VBG at node 340 is necessarily the voltage difference between those two points, Fig 1a/3, [0059]).
Regarding Claim 2, Motz discloses all of the limitations of claim 1, and further discloses the beta-compensated current generation circuit further comprising: an input terminal configured to receive the PTAT current (242 is controlled by 218 to deliver PTAT to the emitter of 222, Fig 3, [0060]); and an output terminal configured to supply the beta-compensated current (222's base current is fed to BJT 212's emitter, Fig 3, [0060]), wherein the beta-compensated current is proportional to absolute temperature ("In the case of a bandgap reference, it is possible to achieve low temperature drift by adding a proportional-to-absolute-temperature (PTAT) voltage to the base-emitter voltage of a bipolar transistor (BJT).", where amplifier 218 enforces the operation that flows to the resistor R1 and R1 turns the PTAT voltage into a current, Fig 3, [0003]).
Regarding Claim 3, Motz discloses all of the limitations of claim 2, and further discloses a wherein the PTAT current is received at the first terminal of the resistive element ("the bandgap reference circuit includes a current source that is controlled by the differential amplifier circuit of the bandgap reference core circuit and that is designed to provide a PTAT current" where controlled current source 240 delivers PTAT to R1/342, Fig 3, [0025]).
Regarding Claim 4, Motz discloses all of the limitations of claim 3, and further discloses a the reference voltage comprising: a resistive voltage equivalent to a resistor voltage drop across the resistive element based on a resistive current (node 340 is resistor 342's first terminal and the base of BJT 212 is connected to ground/0V, so following KVL, the reference voltage VBG - 0V = V.sub.BE + I*R1, [0059]); and a base-emitter voltage equivalent to a base-emitter voltage drop from the emitter terminal to the base terminal of the reference BJT based on an emitter current ("a differential amplifier circuit that is configured to control first and second emitter currents through the first and second bipolar transistors, respectively, such that a sum of the second base-emitter voltage and a voltage drop across the resistor approximates the first base-emitter voltage.", abstract).
Regarding Claim 5, Motz discloses all of the limitations of claim 4, and further discloses a wherein the resistive current is equivalent to the PTAT current ("the bandgap reference circuit includes a current source that is controlled by the differential amplifier circuit of the bandgap reference core circuit and that is designed to provide a PTAT current" where controlled current source 240 delivers PTAT to R1/342, Fig 3, [0025]).
Regarding Claim 6, Motz discloses all of the limitations of claim 4, and further discloses a wherein the emitter current is equivalent to the PTAT current plus the beta-compensated current (I.sub.E = I.sub.C + I.sub.B, where I.sub.C is the PTAT current and I.sub.B is the beta-compensated current Fig 4).
Regarding Claim 10, Motz discloses all of the limitations of claim 1, and further discloses wherein the reference BJT is a PNP type BJT ("a first pnp bipolar transistor 212", [0053]).
Regarding Claim 12, Motz discloses all of the limitations of claim 10, and further discloses wherein the reference BJT is configured in a diode configuration, wherein the collector terminal and the base terminal are electrically coupled (212's collector and base are connected to the same ground, Fig 3).
Regarding Claim 19, Motz discloses a method for generating a process, voltage, and temperature invariant reference voltage (bandgap reference circuit 300 compensates for variances in process, voltage, and temperature, Fig 3, [0002-3, 0050-1]), the method comprising: generating a beta-compensated current ("β-drift effect (β=I.sub.C/I.sub.B denotes a current gain of a bipolar transistor)", [0010]) based on a proportional to absolute temperature (PTAT) current ("In the case of a bandgap reference, it is possible to achieve low temperature drift by adding a proportional-to-absolute-temperature (PTAT) voltage to the base-emitter voltage of a bipolar transistor (BJT).", 220, Fig 3, [0003]), wherein the beta-compensated current is inversely proportional to a beta value of a reference bipolar junction transistor (BJT) (since I.sub.B of 222 is fed into BJT 212 and β=I.sub.C/I.sub.B, then the base current I.sub.B=I.sub.C/β which is inversely proportional to β, [0003]); receiving at an emitter terminal of the reference BJT the beta-compensated current (342's bottom terminal is connected to the emitter of 212, Fig 3): wherein the reference BJT comprises a base terminal, the emitter terminal, and a collector terminal (212, Fig 3), and wherein a ratio of a collector current at the collector terminal and a base current at the base terminal is equal to the beta value ("β-drift effect (β=I.sub.C/I.sub.B denotes a current gain of a bipolar transistor)", [0010]); and receiving the PTAT current at a first terminal of a reference resistive element ("In the case of a bandgap reference, it is possible to achieve low temperature drift by adding a proportional-to-absolute-temperature (PTAT) voltage to the base-emitter voltage of a bipolar transistor (BJT).", where amplifier 218 enforces the operation that flows to the resistor R1 and R1 turns the PTAT voltage into a current, Fig 3, [0003]), the reference resistive element (342, Fig 3) comprising: the first terminal; and a second terminal electrically coupled to the emitter terminal of the reference BJT (342's bottom terminal is connected to the emitter of 212, Fig 3), wherein the reference voltage is generated based on a voltage difference between the first terminal of the reference resistive element and the base terminal of the reference BJT (node 340 is resistor 342's first terminal and the base of 212 is connected to ground/0V, so following KVL, the reference voltage VBG at node 340 is necessarily the voltage difference between those two points, Fig 1a/3, [0059]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Motz (US 20220374037 A1) in view of Ivanov (US 10983547 B1) and further in view of Pertijs (US 20080094131 A1).
Regarding Claim 7, Motz discloses all of the limitations of claim 2.
Motz does not disclose wherein the beta-compensated current generation circuit comprises: an operational amplifier comprising a negative input terminal, a positive input terminal, and an output terminal; a first p-type metal-oxide-semiconductor field-effect transistor (PMOS) comprising: a drain terminal electrically coupled to the positive input terminal of the operational amplifier; a gate terminal electrically coupled to the output terminal of the operational amplifier; and a source terminal electrically coupled to a voltage supply; a second PMOS comprising: a drain terminal electrically coupled to the negative input terminal of the operational amplifier; a gate terminal electrically coupled to the output terminal of the operational amplifier and the gate terminal of the first PMOS; and a source terminal electrically coupled to the source terminal of the first PMOS and the voltage supply; a third PMOS comprising: a source terminal electrically coupled to the source terminal of the first PMOS, the source terminal of the second PMOS, and the voltage supply; a gate terminal electrically coupled to the gate terminal of the first PMOS, and the gate terminal of the second PMOS; and a drain terminal configured to output the beta-compensated current; a first BJT in a diode configuration comprising: an emitter terminal configured to receive the proportional to absolute temperature current; a base terminal electrically coupled to an electrical ground reference; and a collector terminal electrically coupled to the base terminal and to the electrical ground reference; a first resistor exhibiting a resistive value and comprising: a first terminal electrically coupled to the emitter terminal of the first BJT and configured to receive the proportional to absolute temperature current; and a second terminal electrically coupled to the drain terminal of the first PMOS and the positive input terminal of the operational amplifier; a second BJT in a diode configuration comprising: an emitter terminal electrically coupled to the negative input terminal of the operational amplifier, the source terminal of the second PMOS, and configured to receive the proportional to absolute temperature current; a base terminal; and a collector terminal electrically coupled to the electrical ground reference; a second resistor exhibiting the resistive value and comprising: a first terminal electrically coupled to the base terminal of the second BJT; and a second terminal electrically coupled to the electrical ground reference and the collector terminal of the second BJT.
Ivanov teaches a conventional bandgap reference circuit (see Fig 2) including an operational amplifier comprising a negative input terminal, a positive input terminal, and an output terminal (A1, Fig 2); a first p-type metal-oxide-semiconductor field-effect transistor (PMOS) (M2, Fig 2) comprising: a drain terminal electrically coupled to the positive input terminal of the operational amplifier (M2 drain connected to positive input of A1, Fig 2); a gate terminal electrically coupled to the output terminal of the operational amplifier (M2 gate connected to output of A1, Fig 2); and a source terminal electrically coupled to a voltage supply (M2 source connected to VDD, Fig 2); a second PMOS (M1, Fig 2) comprising: a drain terminal electrically coupled to the negative input terminal of the operational amplifier (M1 drain connected to negative input of A1, Fig 2); a gate terminal electrically coupled to the output terminal of the operational amplifier and the gate terminal of the first PMOS (M1 gate connected to output of A1 and gate of M2, Fig 2); and a source terminal electrically coupled to the source terminal of the first PMOS and the voltage supply (M1 source connected to M2 source and VDD, Fig 2); a third PMOS (M3, Fig 2) comprising: a source terminal electrically coupled to the source terminal of the first PMOS, the source terminal of the second PMOS, and the voltage supply (M3 source connected to M1 source, M2 source, and VDD, Fig 2); a gate terminal electrically coupled to the gate terminal of the first PMOS, and the gate terminal of the second PMOS (M3 gate connected to M2 and M1, Fig 2); and a drain terminal configured to output the beta-compensated current ("The current that is passed through the transistor M3 is proportional to the absolute temperature (PTAT).", Col 5[9-10]); a first BJT in a diode configuration (MB2, Fig 2) comprising: an emitter terminal configured to receive the proportional to absolute temperature current (MB2 emitter receives PTAT current, Fig 2); a base terminal electrically coupled to an electrical ground reference (MB2 base connected to GND, Fig 2); and a collector terminal electrically coupled to the base terminal and to the electrical ground reference (MB2 collector connected to base of MB2 and GND, Fig 2); a first resistor exhibiting a resistive value and comprising (R1, Fig 2): a first terminal electrically coupled to the emitter terminal of the first BJT and configured to receive the proportional to absolute temperature current (R1 bottom terminal connected to MB2, Fig 2); and a second terminal electrically coupled to the drain terminal of the first PMOS and the positive input terminal of the operational amplifier (R1 top terminal connected to drain of M2 and positive terminal of A1, Fig 2); a second BJT in a diode configuration (MB1, Fig 2) comprising: an emitter terminal electrically coupled to the negative input terminal of the operational amplifier, the source terminal of the second PMOS, and configured to receive the proportional to absolute temperature current (MB1 emitter connected to negative input of A1, drain of M1 and receives PTAT current, Fig 2); a base terminal (MB1 base connected to GND, Fig 2); and a collector terminal electrically coupled to the electrical ground reference (MB1 collector connected to GND, Fig 2).
Ivanov does not disclose a second resistor exhibiting the resistive value and comprising: a first terminal electrically coupled to the base terminal of the second BJT; and a second terminal electrically coupled to the electrical ground reference and the collector terminal of the second BJT.
Pertijs teaches a conventional resistor for use in a bandgap voltage reference circuit (, Fig 4) including a second resistor exhibiting the resistive value and comprising (Rbias/m, Fig 4): a first terminal electrically coupled to the base terminal of the second BJT (top terminal of Rbias/m is connected to Q2, Fig 4); and a second terminal electrically coupled to the electrical ground reference and the collector terminal of the second BJT (bottom terminal of Rbias/m is connected to ground and collector of Q2, Fig 4).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the BJT in Motz, as taught by Eberlein, as it provides the advantage of providing improved accuracy ([0010] of Pertijs).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the bandgap reference circuit in Motz, as taught by Ivanov, as it provides the advantage of providing a improved current mirror accuracy.
Regarding Claim 8, the combination of Motz, Ivanov, and Pertijs discloses all of the limitations of claim 7, and further discloses wherein the first BJT and the second BJT exhibit the beta value ("The first replica bipolar transistor emulates an operating point of the first bipolar transistor of the bandgap reference core circuit. In other words, the first replica bipolar transistor has the same emitter current density as the first bipolar transistor of the bandgap reference core circuit… The second replica bipolar transistor emulates an operating point of the second bipolar transistor of the bandgap reference core circuit. In other words, the second replica bipolar transistor has the same emitter current density as the second bipolar transistor", [0008-9] of Motz).
Claims 9, 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Motz (US 20220374037 A1) in view of Coimbra (US 10429879 B1).
Regarding Claim 9, Motz discloses all of the limitations of claim 1.
Motz does not disclose wherein the resistive element is a variable resistor.
Coimbra teaches a conventional variable resistor for use in a bandgap reference voltage circuit (see Fig 5) including wherein the resistive element is a variable resistor (500, Fig 5).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the variable resistor in Motz, as taught by Coimbra, as it provides the advantage of providing a compact, accurate bandgap reference voltage without the need for calibration (Col 1. Lines 48-51 of Coimbra).
Regarding Claim 18, it is rejected for the same reasons as stated above for Claim 9.
Regarding Claim 20, it is rejected for the same reasons as stated above for Claim 9.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Motz (US 20220374037 A1) in view of Eberlein (US 20160026198 A1).
Regarding Claim 11, Motz discloses all of the limitations of claim 2, and further disclose wherein the reference BJT is manufactured using a complementary metal-oxide-semiconductor (CMOS) process ("It is possible to produce bipolar transistors in any CMOS process.", [0047]), such that a collector current at the collector terminal of the reference BJT is inaccessible and the beta value of the reference BJT is less than one.
Motz does not disclose a collector current at the collector terminal of the reference BJT is inaccessible and the beta value of the reference BJT is less than one.
Eberlein teaches a conventional BJT for use in a bandgap reference voltage circuit (see Fig 1) including a collector current at the collector terminal of the reference BJT is inaccessible ("the collector of a parasitic p-type device in a bandgap reference circuit may not be accessed directly", [0036]) and the beta value of the reference BJT is less than one ("β below 3 or even below 1", [0036]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the BJT in Motz, as taught by Eberlein, as it provides the advantage of providing a way to regulate the collector current through the emitter in a p-type device where the collector is not accessible ([0036] of Eberlein).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Motz (US 20220374037 A1) in view of Sakurai (US 7595685 B1).
Regarding Claim 13, Motz discloses a circuit configured to generate a process, voltage, and temperature invariant reference voltage (bandgap reference circuit 300 compensates for variances in process, voltage, and temperature, Fig 3, [0002-3, 0050-1]), the circuit comprising: a beta-compensated current generation circuit comprising: a first PTAT input electrically coupled to the drain terminal of the second PTAT PMOS and configured to receive the PTAT current (342 receives PTAT current at its top terminal fed by current source 240/Sakurai's M5 drain, Fig 3, [0060]); a second PTAT input electrically coupled to the drain terminal of the third PTAT PMOS and configured to receive the PTAT current (344 receives PTAT current at its top terminal fed by current source 240/Sakurai's M8 drain, Fig 3, [0060]); and a beta-compensated current output configured to generate a beta-compensated current ("β-drift effect (β=I.sub.C/I.sub.B denotes a current gain of a bipolar transistor)", [0010]), wherein the beta-compensated current is inversely proportional to a beta value (since I.sub.B of 222 is fed into 212 and β=I.sub.C/I.sub.B, then the base current I.sub.B=I.sub.C/β which is inversely proportional to β, [0003]); a reference bipolar junction transistor (BJT) in a diode configuration (212's collector and base are connected to the same ground, Fig 3) comprising: a base terminal electrically coupled to the electrical ground reference (212's collector is connected to ground, Fig 3); an emitter terminal electrically coupled to the beta-compensated current output of the beta-compensated current generation circuit and configured to receive the beta-compensated current ("the base currents of the replica bipolar transistors 222, 234 are fed directly into the respective emitter connections of the bipolar transistors 212", Fig 3, [0063]); and a collector terminal electrically coupled to the base terminal and the electrical ground reference (212's collector and base are connected to the same ground, Fig 3); wherein a ratio of a collector current at the collector terminal and a base current at the base terminal is equal to the beta value ("β-drift effect (β=I.sub.C/I.sub.B denotes a current gain of a bipolar transistor)", [0010]); and a reference resistor (342, Fig 3) comprising: a first terminal electrically coupled to the drain terminal of the fourth PTAT PMOS and configured to receive the PTAT current (342's top terminal is connected to the fourth PTAT PMOS of Sakurai to receive PTAT current, Fig 3); a second terminal electrically coupled to the beta-compensated current output of the beta-compensated current generation circuit and the emitter terminal of the reference BJT (342's bottom terminal is connected to the emitter of 212, Fig 3), wherein, the reference voltage comprises a voltage difference at the first terminal of the reference resistor and the base terminal of the reference BJT (node 340 is resistor 342's first terminal and the base of BJT 212 is connected to ground/0V, so following KVL, the reference voltage VBG at node 340 is necessarily the voltage difference between those two points, Fig 1a/3, [0059]).
Motz does not disclose a proportional to absolute temperature (PTAT) current source configured to generate a PTAT current that is proportional to absolute temperature, the PTAT current source comprising: a first terminal electrically coupled to an electrical ground reference; and a second terminal; a first PTAT p-type metal-oxide-semiconductor field-effect transistor (PMOS) comprising: a source terminal electrically coupled to a voltage supply; a gate terminal; and a drain terminal electrically coupled to the gate terminal and the second terminal of the PTAT current source; a second PTAT PMOS comprising: a source terminal electrically coupled to the source terminal of the first PTAT PMOS and the voltage supply; a gate terminal electrically coupled to the gate terminal of the first PTAT PMOS; and a drain terminal; a third PTAT PMOS comprising: a source terminal electrically coupled to the source terminal of the first PTAT PMOS, the source terminal of the second PTAT PMOS, and the voltage supply; a gate terminal electrically coupled to the gate terminal of the first PTAT PMOS and the gate terminal of the second PTAT PMOS; and a drain terminal; a fourth PTAT PMOS comprising: a source terminal electrically coupled to the source terminal of the first PTAT PMOS, the source terminal of the second PTAT PMOS, the source terminal of the third PTAT PMOS, and the voltage supply; a gate terminal electrically coupled to the gate terminal of the first PTAT PMOS, the gate terminal of the second PTAT PMOS, and the gate terminal of the third PTAT PMOS; and a drain terminal.
Sakurai teaches a conventional PTAT current source for use in a bandgap reference circuit (see Fig 6) including a proportional to absolute temperature (PTAT) current source configured to generate a PTAT current that is proportional to absolute temperature, the PTAT current source ("PTAT current source 502 generates a PTAT current 504", Fig 6, Col 4[38-9]) comprising: a first terminal electrically coupled to an electrical ground reference ("the PTAT current source 502 comprises a PNP BJT Q1 connected in series with a NMOS M3 and a PMOS M1 and a PNP BJT Q2 connected in series with a NMOS M4 and a PMOS M2. The collector and base of the PNP BJT Q1 is coupled to the ground", Fig 6, Col 5[3-7]); and a second terminal (, Fig 6); a first PTAT p-type metal-oxide-semiconductor field-effect transistor (PMOS) (M2, Fig 6) comprising: a source terminal electrically coupled to a voltage supply (V1, Fig 6); a gate terminal (gate, Fig 6); and a drain terminal electrically coupled to the gate terminal and the second terminal of the PTAT current source (M2's gate and drain are connected, Fig 6); a second PTAT PMOS (M5, Fig 6) comprising: a source terminal electrically coupled to the source terminal of the first PTAT PMOS and the voltage supply (source of M5 connected to the source of M2 and V1, Fig 6); a gate terminal electrically coupled to the gate terminal of the first PTAT PMOS (M5's gate is connected to M2's gate, Fig 6); and a drain terminal (drain of M5, Fig 6); a third PTAT PMOS (M8, Fig 6) comprising: a source terminal electrically coupled to the source terminal of the first PTAT PMOS, the source terminal of the second PTAT PMOS, and the voltage supply (source of M8 connected to the source of M2 and the source of M5 and V1, Fig 6); a gate terminal electrically coupled to the gate terminal of the first PTAT PMOS and the gate terminal of the second PTAT PMOS (M8's gate is connected to M2's gate and M5's gate, Fig 6); and a drain terminal (drain of M8, Fig 6); a fourth PTAT PMOS comprising (M6, Fig 6): a source terminal electrically coupled to the source terminal of the first PTAT PMOS, the source terminal of the second PTAT PMOS, the source terminal of the third PTAT PMOS, and the voltage supply (M6's source is connected to the source of M2 and the source of M5 and the source of M8 and V1, Fig 6); a gate terminal electrically coupled to the gate terminal of the first PTAT PMOS, the gate terminal of the second PTAT PMOS, and the gate terminal of the third PTAT PMOS (M6's gate is connected to M2's gate and to M5's gate and M8's gate, Fig 6); and a drain terminal (drain of M6, Fig 6).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the PTAT current source in Motz, as taught by Sakurai, as it provides the advantage of providing a way to distribute a single PTAT current to multiple downstream branches.
Claims 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Motz (US 20220374037 A1) in view of Sakurai (US 7595685 B1) and further in view of Ivanov (US 10983547 B1) and Pertijs (US 20080094131 A1).
Regarding Claim 14, the combination of Motz and Sakurai discloses all of the limitations of claim 13.
The combination of Motz and Sakurai do not disclose wherein the beta-compensated current generation circuit comprises: an operational amplifier comprising a negative input terminal, a positive input terminal, and an output terminal; a first p-type metal-oxide-semiconductor field-effect transistor (PMOS) comprising: a drain terminal electrically coupled to the positive input terminal of the operational amplifier; a gate terminal electrically coupled to the output terminal of the operational amplifier; and a source terminal electrically coupled to the voltage supply; a second PMOS comprising: a drain terminal electrically coupled to the negative input terminal of the operational amplifier; a gate terminal electrically coupled to the output terminal of the operational amplifier and the gate terminal of the first PMOS; and a source terminal electrically coupled to the source terminal of the first PMOS and the voltage supply; a third PMOS comprising: a source terminal electrically coupled to the source terminal of the second PMOS, the source terminal of the first PMOS, and the voltage supply; a gate terminal electrically coupled to the output terminal of the operational amplifier, the gate terminal of the first PMOS, and the gate terminal of the second PMOS; and a drain terminal configured to output the beta-compensated current; a first BJT in a diode configuration comprising: an emitter terminal configured to receive the PTAT current; a base terminal electrically coupled to the electrical ground reference; and a collector terminal electrically couple to the base terminal and to the electrical ground reference; a first resistor exhibiting a resistive value and comprising: a first terminal electrically coupled to the emitter terminal of the first BJT and configured to receive the PTAT current; and a second terminal electrically coupled to the drain terminal of the first PMOS and the positive input terminal of the operational amplifier; a second BJT in a diode configuration comprising: an emitter terminal electrically coupled to the negative input terminal of the operational amplifier, the drain terminal of the second PMOS, and configured to receive the PTAT current; a base terminal; and a collector terminal electrically coupled to the electrical ground reference; a second resistor exhibiting the resistive value and comprising: a first terminal electrically coupled to the base terminal of the second BJT; and a second terminal electrically coupled to the electrical ground reference and the collector terminal of the second BJT.
Ivanov teaches a conventional bandgap reference circuit (see Fig 2) including wherein the beta-compensated current generation circuit comprises: an operational amplifier comprising a negative input terminal, a positive input terminal, and an output terminal (A1, Fig 2); a first p-type metal-oxide-semiconductor field-effect transistor (PMOS) (M2, Fig 2) comprising: a drain terminal electrically coupled to the positive input terminal of the operational amplifier (M2 drain connected to positive input of A1, Fig 2); a gate terminal electrically coupled to the output terminal of the operational amplifier (M2 gate connected to output of A1, Fig 2); and a source terminal electrically coupled to the voltage supply (M2 source connected to VDD, Fig 2); a second PMOS (M1, Fig 2) comprising: a drain terminal electrically coupled to the negative input terminal of the operational amplifier (M1 drain connected to negative input of A1, Fig 2); a gate terminal electrically coupled to the output terminal of the operational amplifier and the gate terminal of the first PMOS (M1 gate connected to output of A1 and gate of M2, Fig 2); and a source terminal electrically coupled to the source terminal of the first PMOS and the voltage supply (M1 source connected to M2 source and VDD, Fig 2); a third PMOS (M3, Fig 2) comprising: a source terminal electrically coupled to the source terminal of the second PMOS, the source terminal of the first PMOS, and the voltage supply (M3 source connected to M1 source, M2 source, and VDD, Fig 2); a gate terminal electrically coupled to the output terminal of the operational amplifier, the gate terminal of the first PMOS, and the gate terminal of the second PMOS (M3 gate connected to output of A1 and gate of M2 and gate of M1, Fig 2); and a drain terminal configured to output the beta-compensated current ("The current that is passed through the transistor M3 is proportional to the absolute temperature (PTAT).", Col 5[9-10]); a first BJT in a diode configuration (MB2, Fig 2) comprising: an emitter terminal configured to receive the PTAT current (MB2 emitter receives PTAT current, Fig 2); a base terminal electrically coupled to the electrical ground reference (MB2 base connected to GND, Fig 2); and a collector terminal electrically couple to the base terminal and to the electrical ground reference (MB2 collector connected to base of MB2 and GND, Fig 2); a first resistor exhibiting a resistive value and comprising (R1, Fig 2): a first terminal electrically coupled to the emitter terminal of the first BJT and configured to receive the PTAT current (R1 bottom terminal connected to MB2, Fig 2); and a second terminal electrically coupled to the drain terminal of the first PMOS and the positive input terminal of the operational amplifier (R1 top terminal connected to drain of M2 and positive terminal of A1, Fig 2); a second BJT in a diode configuration (MB1, Fig 2) comprising: an emitter terminal electrically coupled to the negative input terminal of the operational amplifier, the drain terminal of the second PMOS, and configured to receive the PTAT current (MB1 emitter connected to negative input of A1, drain of M1 and receives PTAT current, Fig 2); a base terminal (MB1 base connected to GND, Fig 2); and a collector terminal electrically coupled to the electrical ground reference (MB1 collector connected to GND, Fig 2).
Ivanov does not disclose a second resistor exhibiting the resistive value and comprising: a first terminal electrically coupled to the base terminal of the second BJT; and a second terminal electrically coupled to the electrical ground reference and the collector terminal of the second BJT.
Pertijs teaches a conventional resistor for use in a bandgap voltage reference circuit (, Fig 4) including a second resistor exhibiting the resistive value and comprising (Rbias/m, Fig 4): a first terminal electrically coupled to the base terminal of the second BJT (top terminal of Rbias/m is connected to Q2, Fig 4); and a second terminal electrically coupled to the electrical ground reference and the collector terminal of the second BJT (bottom terminal of Rbias/m is connected to ground and collector of Q2, Fig 4).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the BJT in Motz, as taught by Eberlein, as it provides the advantage of providing improved accuracy ([0010] of Pertijs).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the bandgap reference circuit in Motz, as taught by Ivanov, as it provides the advantage of providing a improved current mirror accuracy.
Regarding Claim 15, the combination of Motz, Sakurai, Ivanov, and Pertijs discloses all of the limitations of claim 14, and further discloses wherein the first BJT and the second BJT exhibit the beta value ("The first replica bipolar transistor emulates an operating point of the first bipolar transistor of the bandgap reference core circuit. In other words, the first replica bipolar transistor has the same emitter current density as the first bipolar transistor of the bandgap reference core circuit… The second replica bipolar transistor emulates an operating point of the second bipolar transistor of the bandgap reference core circuit. In other words, the second replica bipolar transistor has the same emitter current density as the second bipolar transistor", [0008-9] of Motz).
Regarding Claim 16, the combination of Motz, Sakurai, Ivanov, and Pertijs discloses all of the limitations of claim 14, and further discloses wherein the reference BJT, the first BJT, and the second BJT are PNP type BJTs (MB2 and MB1 are PNP type BJTs, Fig 2 of Ivanov).
Regarding Claim 17, the combination of Motz, Sakurai, Ivanov, and Pertijs discloses all of the limitations of claim 14, and further discloses wherein the reference BJT, the first BJT, and the second BJT are manufactured using a complementary metal-oxide-semiconductor (CMOS) process ("It is possible to produce bipolar transistors in any CMOS process.", [0047] of Motz).
Conclusion
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/J.C.C./Examiner, Art Unit 2838
/GARY L LAXTON/Primary Examiner, Art Unit 2838 9/18/2026
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