DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
2. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claim(s) 1, 5 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shin et al. (US 11,049,436 B1, hereinafter referred as “Shin”) in view of Kawakami et al. (US 2010/0148869 A1, hereinafter referred as “Kawakami”).
Regarding claim 1, Shin discloses an array substrate comprising a display area and a non-display area that at least partially surrounds the display area (col. 1, lines 44-47 disclose a display device may include a first display substrate which includes a display region in which pixels are disposed and a non-display region NDA disposed adjacent to the display region DA), wherein the non-display area comprises at least two clock signal lines (Figs. 2A, 7A and col. 13, lines 11-16 disclose the display panel DP may include a plurality of clock signal lines CKL1 to CKLn disposed on the first display substrate 100 in region AA’ of the NDA);…
wherein the non-display area further comprises a ground protection line comprising at least one of a first ground protection line arranged on a side of the at least two clock signal lines close to the display area, a second ground protection line arranged between two adjacent clock signal lines, and a third ground protection line arranged on a side of the at least two clock signal lines away from the display area (Fig. 2A, 7A and col. 13, lines 24-26 disclose the first line 1L may be disposed at the outermost region of the non-display region NDA).
Shin doesn’t disclose a spacing between two adjacent …signal lines is greater than a line width of a …signal line of the at least two …signal lines.
However, in the same field of endeavor, Kawakami discloses a spacing between two adjacent …signal lines is greater than a line width of a …signal line of the at least two …signal lines (¶0094 discloses a spacing between the primary inductor wirings 52 and 54 is set as three or more times of the line width of the primary inductor wirings 52 and 54).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Shin so that when the wiring space is increased three times of the line width, a coupling coefficient will be reduced roughly by half compared with a case where the wiring space is very narrow (¶0095).
Regarding claim 5, Shin discloses array substrate according to claim 1, wherein the clock signal line and the ground protection line are arranged on the same layer (col. 14, lines 40-43 disclose the first line 1L, the second line 2L, and the clock signal lines CKL1 to CKLn may be formed of a same material through a same process and disposed on the same layer).
Regarding claim 11, Shin doesn’t disclose the array substrate according to claim 1, wherein a ratio of the spacing between the two adjacent clock signal lines to the line width of the clock signal line is greater than or equal to 3.
However, in the same field of endeavor, Kawakami discloses wherein a ratio of the spacing between the two adjacent clock signal lines to the line width of the clock signal line is greater than or equal to 3 (¶0094 discloses a spacing between the primary inductor wirings 52 and 54 is set as three or more times of the line width of the primary inductor wirings 52 and 54).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Shin so that when the wiring space is increased three times of the line width, a coupling coefficient will be reduced roughly by half compared with a case where the wiring space is very narrow (¶0095).
4. Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shin in view of Kawakami and in further view of Takada et al. (US 2020/0176481 A1, hereinafter referred as “Takada”).
Regarding claim 2, Shin as modified doesn’t disclose the array substrate according to claim 1, wherein the non-display area further comprises at least one shielding electrode connected to the ground protection line through a via hole.
However, in the same field of endeavor, Takada discloses wherein the non-display area further comprises at least one shielding electrode connected to the ground protection line through a via hole (¶0018 and ¶0183 disclose a shield electrode formed in the frame region, the common potential being applied to shield electrode; and a first connection wiring connecting each of the plurality of dummy gate lead-out lines and the shield electrode through a first contact hole made in the frame region).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Shin for the purpose of reducing capacitive/electric-field coupling between neighboring conductors.
5. Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shin in view of Kawakami, in further view of Takada and still in further view of Sawada et al. (US 2015/0301415 A1, hereinafter referred as “Sawada”).
Regarding claim 3, Shin as modified doesn’t disclose the array substrate according to claim 2, wherein the at least one shielding electrode is arranged on a different layer from the ground protection line and is arranged on a different layer from the clock signal line; and an orthographic projection of the at least one shielding electrode on an array substrate plane is at least partially overlapped with an orthographic projection of the ground protection line on the array substrate plane and at least partially overlapped with an orthographic projection of the clock signal line on the array substrate plane.
However, in the same field of endeavor, Sawada discloses wherein the at least one shielding electrode is arranged on a different layer from the ground protection line and is arranged on a different layer from the clock signal line (Figs. 6-7 and ¶0075 disclose the second shield electrode 136 provided above the power supply line 133, and a third shield electrode 139 provided above the clock signal lines 131 and 132; and ¶0039 discloses the power supply line 133 for supplying the power supply voltage VSS); and an orthographic projection of the at least one shielding electrode on an array substrate plane is at least partially overlapped with an orthographic projection of the ground protection line on the array substrate plane (Fig. 6 and ¶0075 disclose the second shield electrode 136 provided above the power supply line 133) and at least partially overlapped with an orthographic projection of the clock signal line on the array substrate plane (Fig. 7 and ¶0075 disclose a third shield electrode 139 provided above the clock signal lines 131 and 132).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Shin for the purpose of providing known suppression of electric-field coupling while reducing lateral substrate area required for shielding.
6. Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shin in view of Kawakami, in further view of Takada and still in further view of Xiao et al. (US 2018/0136528 A1, hereinafter referred as “Xiao”).
Regarding claim 4, Shin as modified doesn’t disclose the array substrate according to claim 2 wherein the display area comprises a common electrode, and the at least one shielding electrode is arranged on the same layer as the common electrode.
However, in the same field of endeavor, Xiao discloses wherein the display area comprises a common electrode, and the at least one shielding electrode is arranged on the same layer as the common electrode (Fig. 4 and ¶0056 discloses the shielding electrode layer 140 is disposed on the same layer, formed of the same material and applied with the same voltage as the common electrode).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Shin for the purpose of readily receiving a stable common/reference potential while reducing manufacturing complexity.
7. Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shin in view of Kawakami, and in further view of Kim et al. (US 2017/0124972 A1, hereinafter referred as “Kim”).
Regarding claim 6, Shin discloses array substrate according to claim 1, …the clock signal line and the ground protection line are arranged on the same layer (col. 14, lines 40-43 disclose the first line 1L, the second line 2L, and the clock signal lines CKL1 to CKLn may be formed of a same material through a same process and disposed on the same layer)…
Shin doesn’t disclose wherein the display area comprises a plurality of data lines, and the clock signal line… are arranged on the same layer as the data lines.
However, in the same field of endeavor, Kim discloses wherein the display area comprises a plurality of data lines, and the clock signal line… are arranged on the same layer as the data lines (¶0076 discloses the source electrode 340 branches off from the data lines; and ¶0084 discloses the plurality of clock signal lines 200 may be formed in the same layer and made of the same material as… the source and drain electrodes 340).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Shin for the purpose of avoiding the need for an additional metallization layer.
8. Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shin in view of Kawakami, and in further view of Zhan et al. (CN 112634802 A, hereinafter referred as “Zhan”).
Regarding claim 7, Shin as modified doesn’t disclose the array substrate according to claim 1, wherein the ground protection line comprises a first ground protection line segment, a second ground protection line segment and a third ground protection line segment which are sequentially connected; the clock signal line comprises a first clock signal line segment, a second clock signal line segment and a third clock signal line segment which are sequentially connected; and the first ground protection line segment and the first clock signal line segment both extend in a first direction and are parallel to each other, the second ground protection line segment and the second clock signal line segment both extend in a second direction and are parallel to each other, and the third ground protection line segment and the third clock signal line segment both extend in the first direction and are parallel to each other.
However, in the same field of endeavor, Zhan discloses wherein the ground protection line comprises a first ground protection line segment, a second ground protection line segment and a third ground protection line segment which are sequentially connected; the clock signal line comprises a first clock signal line segment, a second clock signal line segment and a third clock signal line segment which are sequentially connected (as shown in fig. 12, a section of the clock signal line L1 corresponding to the shift register 210(m) in the direction Y includes first to third line segments LN1 to LN3, wherein the first line segment LN1 and the third line segment LN3 are parallel to the direction Y, and two ends of the second line segment LN2 are respectively connected to the first line segment LN1 and the third line segment LN3 and are not parallel to the direction X and the direction Y, but not limited thereto); and the first ground protection line segment and the first clock signal line segment both extend in a first direction and are parallel to each other, the second ground protection line segment and the second clock signal line segment both extend in a second direction and are parallel to each other, and the third ground protection line segment and the third clock signal line segment both extend in the first direction and are parallel to each other (The configuration of other signal lines (e.g., the clock signal lines L2 to L4, the start signal line SL1, and/or the reference potential signal line VL, etc.) may also be similar to that of the clock signal line L1 described above).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Shin for the purpose of predictably maintaining shielding along substantially the entire routed clock conductor.
9. Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shin in view of Kawakami, and in further view of Tanaka et al. (US 2019/0035848 A1, hereinafter referred as “Tanaka”).
Regarding claim 8, Shin as modified doesn’t disclose the array substrate according to claim 1, wherein the ground protection line comprises the first ground protection line, the second ground protection line and the third ground protection line, and a total number of the ground protection line is greater than a total number of the at least two clock signal lines.
However, in the same field of endeavor, Tanaka discloses wherein the ground protection line comprises the first ground protection line, the second ground protection line and the third ground protection line, and a total number of the ground protection line is greater than a total number of the at least two clock signal lines (Fig. 16 and ¶0156 disclose shield line SL (first shield line) is disposed between the signal lines LC1 and LC2; ¶0157 discloses the signal line LC1 is disposed between the shield line SL1 and the shield line SL and the signal line LC2 is disposed between the shield line SL2 and the shield line SL).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Shin for the purpose of reducing a negative influence applied on the first clock signal by noise other than the clock noise, by the second shield line and to reduce a negative influence applied on the second clock signal by noise other than the clock noise, by the third shield line (0029).
9. Claim(s) 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shin in view of Kawakami, and in further view of McElvain et al. (US 2013/0043569 A1, hereinafter referred as “McElvain”).
Regarding claim 9, Shin as modified doesn’t disclose the array substrate according to claim 1, wherein a ratio of a line width of the ground protection line to the line width of the clock signal line is 0.8 to 1.2.
However, in the same field of endeavor, McElvain discloses wherein a ratio of a line width of the ground protection line to the line width of the clock signal line is 0.8 to 1.2 (¶0062 discloses the width of the signal lines is the same as the width of the shielding lines).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Shin in order to provide a known shielding benefit without unnecessarily enlarging the shielding conductors.
Regarding claim 10, Shin as modified doesn’t disclose the array substrate according to claim 1, wherein the ground protection line comprises the first ground protection line, the second ground protection line and the third ground protection line, and line widths of the first ground protection line, the second ground protection line, and the third ground protection line are equal.
However, in the same field of endeavor, McElvain discloses wherein the ground protection line comprises the first ground protection line, the second ground protection line and the third ground protection line, and line widths of the first ground protection line, the second ground protection line, and the third ground protection line are equal (¶0064 discloses the shielding lines are of the same width).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Shin so that uniform widths simplify conductor layout and provide consistent shielding characteristics.
Allowable Subject Matter
10. Claims 12-20 are allowable.
The closest prior art of Shin at col. 1, lines 44-47 disclose a display device may include a first display substrate which includes a display region in which pixels are disposed and a non-display region NDA disposed adjacent to the display region DA. Figs. 2A, 7A and col. 13, lines 11-16 disclose the display panel DP may include a plurality of clock signal lines CKL1 to CKLn disposed on the first display substrate 100 in region AA’ of the NDA. Fig. 2A, 7A and col. 13, lines 24-26 disclose the first line 1L may be disposed at the outermost region of the non-display region NDA.
However, the prior art alone, or in combination fail to disclose “the at least one dummy trace is discontinuous, and the at least one dummy trace comprises a plurality of dummy trace segments and a discontinuous portion located between two adjacent dummy trace segments,” as recited in claim 12.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRIYANK J SHAH whose telephone number is (571)270-3732. The examiner can normally be reached on 10:00 - 6:00 M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ghebretinsae, Temesghen can be reached on (571) 272-3017. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PRIYANK J SHAH/Primary Examiner, Art Unit 2626
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