Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. US 12212309 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 1 of the current application discloses “and to automatically switch off the transistor switch without additional signaling” and claim 1 of US. Patent No. US 12212309 B2 discloses “and to automatically switch the transistor switch off without additional signaling”.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 15 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 15 recites the limitation “external terminals" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 19 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
Claim 19 recites “collector/drain”. Claim language needs to explicitly state "collector or drain” or "collector and drain” - instead of collector/drain.
Claim 19 recites “emitter/source”. Claim language needs to explicitly state " emitter or source” or “emitter and source” - instead of emitter/source.
Claim 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
Claim 20 recites “current and/or a decrease”. Claim language needs to explicitly state "current or a decrease” or "current and a decrease” - instead of current and/or a decrease.
Claim 20 recites “emitter/source”. Claim language needs to explicitly state " emitter or source” or “emitter and source” - instead of emitter/source.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5-11, 14 and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Fukuda et al. (US 6717785 B2 and Fukuda hereinafter.).
Regarding claim 1, Fukuda discloses a switch module [fig. 1], comprising: a transistor switch [4] including a control terminal [4a], a first load terminal [4d] and a second load terminal [4b]; and a detection circuit [10]. Fukuda discloses further wherein the detection circuit is energized by a voltage between the control terminal and the first load terminal [fig. 1, transistor 13 receiving power from a high-rail on transistor 3a through resistor 5.]. Fukuda does not explicitly disclose the detection circuit as being a short circuit detection circuit configured to detect a short circuit state between the first load terminal and the second load terminal and to automatically switch off the transistor switch without additional signaling, by automatically electrically coupling the control terminal to the first load terminal in response to detecting the short circuit state.
However, Fukuda teaches the detection circuit [10] detects an inrush current through the first load terminal [4d] and second load terminal [4b] via sense resistors 11 and 12 [fig. 1 and col 5 lines 61-65] which causes the control terminal [4a] to short to ground where ground is the same potential as node 4c. It would have been obvious to one having ordinary skill in the art of the effective filing date to use the inrush current detection circuit, as taught by Fukuda in order to detect a short circuit as defined by applicants’ specs [para. 003] describing a short circuit state as “…for example a short circuit by a simple wire or other metal connection). In such a short circuit case, the current flowing through the power transistor can become very large”.
Regarding claim 2, Fukuda discloses further wherein the short circuit detection circuit comprises a detector/driver circuit [10 comprising 13] configured to receive an indication of a current from the first load terminal [current through 11 and 12 turning on/off 13] and to detect the short circuit state [13 turned on], and a voltage supply [voltage from sense resistors 11 and 12 providing a voltage onto 13] that is energized by the voltage between the control terminal and the first load terminal [11 and 12 between 4a and 4c], and wherein the voltage supply is configured to provide a voltage to the detector/driver circuit when the voltage between the control terminal and the first load terminal is at least in a range of a threshold voltage necessary for turning on the transistor switch [current flowing through 11 and 12 when transistor is turned on].
Regarding claim 5, Fukuda discloses further wherein the detector/driver circuit is configured to measure a current through the transistor switch between the first load terminal and the second load terminal [current through 11 and 12], and to detect the short circuit state if the current exceeds a predefined threshold [13 turned on, shorting gate to ground].
Regarding claim 6, Fukuda discloses further wherein the transistor switch further includes a separate terminal [4c] electrically connected to a portion of an active area of the transistor switch such that a current proportional to but smaller than a current between the first load terminal and the second load terminal is provided at the separate terminal [col 11 lines 58-67], and wherein the detector/driver circuit is electrically connected to the first load terminal and the separate terminal [as shown in fig. 1].
Regarding claim 7, Fukuda discloses wherein the short circuit detection circuit further comprises a buffer capacitor [28 as shown in fig. 1] coupled between [coupled indirectly through 4] the voltage supply [voltage produced by 11 and 12] and the detector/driver circuit [13].
Regarding claim 8, Fukuda discloses further wherein the short circuit detection circuit further comprises a transistor [13 shown in fig. 1], wherein when the short circuit state is detected, the detector/driver circuit is configured to control the transistor to be switched on such that the transistor electrically couples the control terminal to the first load terminal via a resistor [col 6 lines 14-23].
Regarding claim 9, Fukuda discloses further wherein the resistor has a resistance value such that the voltage between the control terminal and the first load terminal drops in case of a short circuit and the transistor switch turns off [gate coupled to ground when 13 is turned on].
Regarding claim 10, Fukuda discloses further wherein the resistance value is selected depending on an external gate resistor [5 shown in fig. 1] coupled to the control terminal, an on-resistance of the transistor, and an internal resistance of a driver for the transistor switch such that when transistor is switched on [inherent to ensure proper operation of system], the voltage between the control terminal and the first load terminal is lower than a threshold voltage of the transistor switch but high enough for the voltage supply to still receive sufficient voltage to maintain operation of the short circuit detection circuit [col 9 lines 55-58].
Regarding claim 11, Fukuda discloses further wherein the detector/driver circuit comprises a comparator [21] configured to compare the indication of the current [current through 27] to a threshold value [V1 on 21], and wherein the detector/driver circuit is configured to detect the short circuit state if the threshold value is exceeded [col 6 lines 48-55].
Regarding claim 14, Fukuda discloses further wherein the transistor switch comprises an insulated gate bipolar transistor [col 8 lines 16-19], and wherein the control terminal is a gate terminal [as shown in fig. 1], the first load terminal is an emitter terminal [as shown in fig. 1] and the second load terminal is a collector terminal [as shown in fig. 1] of the insulated gate bipolar transistor.
Regarding claim 16, Fukuda discloses further a system, comprising: the switch module of claim 1; and a driver circuit [3] configured to provide a control signal to the control terminal of the switch module for controlling the transistor switch [col 9 lines 41-48], to detect the short circuit state between the first and second load terminals of the switch module independently from the short circuit detection circuit detecting the short circuit state [current through 11 and 12 controlling 13], and to turn off the transistor switch in response to detecting the short circuit state [2, 3 and 13 working in unison to ensure protection of 4, col 5 lines 37-50 and col 6 lines 39-63].
Regarding claim 17, Fukuda discloses further wherein the driver circuit is configured to detect the short circuit state based on a voltage rise between the first and second load terminals of the switch module [13 turned on via current through 11 and 12 with 20a and 2 operating 3, col 5 lines 37-50].
Regarding claim 18, Fukuda discloses further wherein the driver circuit comprises: a driver configured to drive the transistor switch in normal operation [no short detected]; and a controller configured to detect the short circuit state independently from the short circuit detection circuit detecting the short circuit state [20a detecting voltage on 4a or from 10, col 5 lines 46-50].
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Fukuda in view of Kaneda et al. (US 20160301351 A1 and Kaneda hereinafter.).
Regarding claim 3, Fukuda discloses all the features regarding claim 2 as indicated above. Fukuda does not explicitly disclose wherein the short circuit detection circuit further comprises a diode electrically connecting the control terminal to the voltage supply.
However, Kaneda discloses [fig. 3] wherein the short circuit detection circuit [54] further comprises a diode [D1] electrically connecting the control terminal to the voltage supply [R3, Q1 and R1 along with associated circuitry]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Faukuda to include the diode circuitry as taught by Kaneda to prevent inadvertent turning on of a transistor due to the miller effect.
Regarding claim 4, Fukuda in view of Kaneda discloses further wherein an anode of the diode is electrically connected to the control terminal [as shown in fig. 3 of Kaneda] and a cathode of the diode is electrically connected to the voltage supply [R1 and R2 coupled to 42 in fig. 3 of Kaneda].
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Fukuda in view of Takami et al. (JP H09311729 A and Takami hereinafter.).
Regarding claim 12, Fukuda does not explicitly disclose wherein the detector/driver circuit comprises a differentiator and a comparator.
However, Takami discloses [fig. 17] wherein the detector/driver circuit comprises a differentiator [33] and a comparator [35]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Fukuda to include the differentiator and comparator as taught by Takami to improve short circuit detection capabilities in a switching circuit.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Fukuda in view of Norling et al. (US 20180097515 A1 and Norling hereinafter.).
Regarding claim 13, Fukuda discloses all the features regarding claim 1 as indicated above. Fukuda does not explicitly disclose wherein the transistor switch comprises a silicon carbide based metal oxide semiconductor field effect transistor, and wherein the control terminal is a gate terminal, the first load terminal is a source terminal and the second load terminal is a drain terminal of the silicon carbide based metal oxide semiconductor field effect transistor.
However, Norling discloses wherein the transistor switch comprises a silicon carbide based metal oxide semiconductor field effect transistor [para. 13 and 16], and wherein the control terminal is a gate terminal [inherent], the first load terminal is a source terminal [inherent] and the second load terminal is a drain terminal [inherent] of the silicon carbide based metal oxide semiconductor field effect transistor. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Fukuda to include the silicon carbide MOSFET as taught by Norling to further prevent possible damage to a switching element due to overpower states.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Fukuda in view of Hokazono et al. (US 20180198442 A1 and Hokazono hereinafter.).
Regarding claim 19, Fukuda discloses all the features regarding claim 18 as indicated above. Fukuda discloses further in response to detecting the short circuit state, set the control signal such that the transistor switch is switched off [inherent protection measured of the system]. Fukuda does not explicitly disclose wherein the controller is configured to: detect the short circuit state based on a temporary voltage rise between an auxiliary collector/drain terminal of the switch module and an auxiliary emitter/source terminal of the switch module.
However, Hokazono discloses [fig. 1 and 2] wherein the controller [200] is configured to: detect the short circuit state based on a temporary voltage rise [Vdesat graph shown in fig. 2] between an auxiliary collector/drain terminal of the switch module [collector of 500] and an auxiliary emitter/source terminal of the switch module [emitter of 500].Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Fukuda to include the detection of a voltage rise as taught by Hokazono to improve saturation voltage detection of transistor switch.
Claims 15 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Fukuda in view of Mauder et al. (US 10254327 B2 and Mauder hereinafter.).
Regarding claim 15, Fukuda discloses all the features regarding claim 14 as indicated above. Fukuda does not explicitly disclose wherein all external terminals of the switch module coupled to the transistor switch or the short circuit detection circuit are selected from the group consisting of: a main gate terminal [4a] coupled to the gate terminal [as shown in fig. 1]; a main emitter terminal [4c] coupled to the emitter terminal [as shown in fig. 1]; a main collector terminal [4b] coupled to the collector terminal [as shown in fig. 1]; an auxiliary emitter terminal [4d] coupled to the emitter terminal [as shown in fig. 1]. Fukuda does not explicitly disclose external terminals of the switch module coupled to the transistor switch or the short circuit detection circuit are selected from the group consisting of: an auxiliary collector terminal coupled to the collector terminal.
However, Mauder discloses external terminals of the switch module coupled to the transistor switch or the short circuit detection circuit are selected from the group consisting of: an auxiliary collector terminal coupled to the collector terminal [col 8 lines 25-28]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Fukuda to include the group of external terminals as taught by Mauder to improve short circuit detection of desaturation currents.
Regarding claim 20, Fukuda discloses all the features regarding claim 18 as indicated above, wherein the controller is configured to: monitor a current flowing from the driver circuit to the control terminal of the switch module and/or a voltage between the control terminal and an auxiliary emitter/source terminal of the switch module; detect the short circuit state based on an increase in the monitored current and/or a decrease in the monitored voltage; and in response to detecting the short circuit state, set the control signal such that the transistor switch is switched off.
However, Mauder discloses [fig. 2] wherein the controller [24, 25, 26 and related circuitry] is configured to: monitor a current flowing from the driver circuit to the control terminal of the switch module [24 accepting input voltage from gate of 21] and/or a voltage between the control terminal and an auxiliary emitter/source terminal of the switch module [25 accepting voltage at node E]; detect the short circuit state based on an increase in the monitored current [curve 41 in fig. 4] and/or a decrease in the monitored voltage [curve 40b in fig. 4]; and in response to detecting the short circuit state, set the control signal such that the transistor switch is switched off [high inductive short circuit mode 1]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Fukuda to include current and voltage monitoring as taught by Mauder to improve short circuit detection of desaturation currents.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's
disclosure, Kadavelugu (US 20200403608 A1) is cited to teach short circuit protection measures in semiconductor switches.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES G YEAMAN whose telephone number is (571)272-5580. The examiner can normally be reached Mon - Fri 954 Schedule.
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/JAMES G YEAMAN/Examiner, Art Unit 2836 /TAELOR KIM/Supervisory Patent Examiner, Art Unit 2836
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