DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This action is in response to application filed on January 27, 2025.
Information Disclosure Statement
3. The information disclosure statement (IDS) submitted on 1/27/2025 has been considered by the examiner.
Drawings
4. The drawings were received on January 27, 2025. These drawings are accepted.
Double Patenting
5. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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6. Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,244,234. Although the claims at issue are not identical, they are not patentably distinct from each other because both claims pertain to a memory, a controller, and a plurality of sequences.
7. Claims 2-10 depend either directly or indirectly from claim 1, and therefore inherit the same deficiencies.
8. Claim 11 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 17 of U.S. Patent No. 12,244,234. Although the claims at issue are not identical, they are not patentably distinct from each other because both claims pertain to a first transistor, a second transistor, a third transistor, a fourth transistor, respective driver circuits, a controller, and a sequence.
9. Claims 12-14 depend either directly or indirectly from claim 11, and therefore inherit the same deficiencies.
Claim Rejections - 35 USC § 103
10. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
11. Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Leong et al (US 2018/0337610) in view of Yang et al (US 2020/0161977).
Regarding claim 15, Leong et al discloses a system (i.e circuit of Figure 1), comprising:
an input (Fig .1, input terminals of circuit of front-end circuit 156) configurable to receive a first voltage (Fig. 1, voltage input to front-end circuit 156 from power source 124);
an output (Fig. 1, output terminals of PCRC stage 158 carrying voltage Vout) configurable to output a second voltage (Fig. 1, voltage Vout); and
a voltage converter (Fig. 1, circuit of front-end circuit 156 and PCRC stage 158) coupled to the input (Fig .1, input terminals of front-end circuit 156) and the output (Fig. 1, output terminals of PCRC stage 158 carrying voltage Vout), the voltage converter (Fig. 1, circuit of front-end circuit 156 and PCRC stage 158) including:
a first half bridge (Fig. 1, switches S102 and S104) coupled in parallel with a first capacitor (Fig. 1, capacitor 110), the first half bridge (Fig. 1, switches S102 and S104) including a first transistor (Fig. 1, switch S102) coupled to a second transistor (Fig. 1, switch S104), each of the first (Fig. 1, switch S102) and second (Fig. 1, switch S104) transistors having a respective control input (Fig. 1, gate terminals of switches S102 and S104);
a second half bridge (Fig. 1, switches S106 and S108) coupled in parallel with a second capacitor (Fig. 1, capacitor 112), the second half bridge (Fig. 1, switches S106 and S108) coupled to the first half bridge (Fig. 1, switches S102 and S104), the second half bridge (Fig. 1, switches S106 and S108) including a third transistor (Fig. 1, switch S106) coupled to a fourth transistor (Fig. 1, switch S108), each of the third (Fig. 1, switch S106) and fourth (Fig. 1, switch S108) transistors having a respective control input (Fig. 1, gate terminals of switches S106 and S108), the first capacitor (Fig. 1, capacitor 110) coupled in series with the second capacitor (Fig. 1, capacitor 112);
a transformer (Fig. 1, transformer 168) coupled to the first half bridge (Fig. 1, switches S102 and S104), the second half bridge (Fig. 1, switches S106 and S108), and an output capacitor (Fig. 1, capacitor 138), the output capacitor (Fig. 1, capacitor 138) coupled to the output (Fig. 1, output terminals of PCRC stage 158 carrying voltage Vout); and
a controller (Fig. 1, controller 152) coupled to the output capacitor (Fig. 1, capacitor 138), wherein the controller (Fig. 1, controller 152) includes first (Fig. 1, output from controller 152 carrying gate signals to switch S102), second (Fig. 1, output from controller 152 carrying gate signals to switch S104), third (Fig. 1, output from controller 152 carrying gate signals to switch S106), and fourth (Fig. 1, output from controller 152 carrying gate signals to switch S108) control outputs;
wherein the controller (Fig. 1, controller 152) is configured to provide control signals on the first (Fig. 1, output from controller 152 carrying gate signals to switch S102), second (Fig. 1, output from controller 152 carrying gate signals to switch S104), third (Fig. 1, output from controller 152 carrying gate signals to switch S106), and fourth (Fig. 1, output from controller 152 carrying gate signals to switch S108) control outputs such that the controller (Fig. 1, controller 152) implements a sequence for turning the transistors of the first (Fig. 1, switches S102 and S104) and second (Fig. 1, switches S106 and S108) half bridges ON and OFF (See ¶[0040]) .
Leong et al fails to disclose respective driver circuits coupled to each of the respective control inputs; a controller including a memory, wherein the controller includes first, second, third, and fourth control outputs coupled to the respective driver circuits.
However, Yang et al discloses respective driver circuits (Fig. 2, buck control logic 210 and boost control logic 212) coupled to each of respective control inputs (Fig. 2, gate terminals of switches Q1-Q4); a controller (Fig. 2, circuits of buck Toff Timer 230, boost Toff Timer 240, and latches 211 and 219) including a memory (Fig. 10, memory 1004), wherein the controller (Fig. 2, circuits of buck Toff Timer 230, boost Toff Timer 240, and latches 211 and 219) includes first (Fig. 2, output to gate terminal of switch Q1), second (Fig. 2, output to gate terminal of switch Q2), third (Fig. 2, output to gate terminal of switch Q3), and fourth (Fig. 2, output to gate terminal of switch Q4) control outputs coupled to the respective driver circuits (Fig. 2, buck control logic 210 and boost control logic 212).
Therefore, it would have been obvious, to one having ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the circuit of Leong et al, by including driver circuits and a memory, as taught by Yang et al, in order to obtain a circuit system with improved efficiency with switch control and faster transient responses.
Allowable Subject Matter
12. Claims 1-14 are rejected for nonstatutory double patenting as mentioned above, but would be allowable upon alleviation of the rejection.
13. Claims 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
14. The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 1-10, the prior art fails to disclose or suggest the emboldened and italicized features below:
An apparatus comprising:
a memory; and
a controller coupled to the memory, wherein the controller includes:
an input; and
a plurality of outputs
wherein:
the controller is configurable to output respective control signals on the plurality of outputs; and
the respective control signals are configurable to switch respective transistors in a plurality of sequences that includes:
a first sequence in which a first control signal of the respective control signals is configured to turn ON a first transistor of the respective transistors and a second control signal of the respective control signals is configured to turn OFF a second transistor of the respective transistors;
a second sequence in which the first control signal of the respective control signals is configured to turn ON the first transistor of the respective transistors and the second control signal of the respective control signals is configured to turn OFF the second transistor of the respective transistors;
a third sequence in which the first control signal of the respective control signals is configured to turn OFF the first transistor of the respective transistors and the second control signal of the respective control signals is configured to turn ON the second transistor of the respective transistors; and
a fourth sequence in which the first control signal of the respective control signals is configured to turn OFF the first transistor of the respective transistors and the second control signal of the respective control signals is configured to turn ON the second transistor of the respective transistors.
Regarding claims 11-14, the prior art fails to disclose or suggest the emboldened and italicized features below:
A system, comprising:
a first transistor coupled to a second transistor, each of the first and second transistors having a respective control input;
a third transistor coupled to a fourth transistor, each of the third and fourth transistors having a respective control input;
respective driver circuits coupled to each of the respective control inputs; and
a controller including a memory, wherein the controller includes first, second, third, and fourth control outputs coupled to the respective driver circuits;
wherein the control is configured to provide control signals on the first, second, third, and fourth control outputs such that the controller implements a sequence for the first, second, third, and fourth transistors, the sequence including a first configuration in which the first and fourth transistors are ON and the second and third transistors are OFF, a second configuration in which the first and third transistors are ON and the second and fourth transistors are OFF, a third configuration in which the second and fourth transistors are ON and the first and third transistors are OFF, and a fourth configuration in which the second and third transistors are ON and the first and fourth transistors are OFF.
Regarding claims 16-19, the prior art fails to disclose or suggest the emboldened and italicized features below:
A system, wherein:
the sequence includes a first configuration in which the first and fourth transistors are ON and the second and third transistors are OFF, a second configuration in which the first and third transistors are ON and the second and fourth transistors are OFF, a third configuration in which the second and fourth transistors are ON and the first and third transistors are OFF, and a fourth configuration in which the second and third transistors are ON and the first and fourth transistors are OFF.
Regarding claim 20, the prior art fails to disclose or suggest the emboldened and italicized features below:
A system, wherein:
a sequence for turning the transistors of the first and second half bridges ON and OFF is configured to configure:
a current between the first capacitor and the second capacitor at approximately zero amps; and
respective root mean square currents in the first transistor, the second transistor, the third transistor, and the fourth transistor at approximately equal values.
Conclusion
15. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Fu et al (US 10,615,701) deals with a hybrid resonant converter, Dina et al (US 2019/0052123) deals with a wireless power transmission with fractional timing resolution, Cho et al (US 2021/0067041) deals with a buck converter including inductor current sensing via high and low-side switching device current sensing, Zhang et al (US 10,903,738) deals with a high conversion-ratio hybrid switched power converter, Fang et al (US 2020/0091828) deals with a resonant switching converter, and Notsch (US 2019/0214922) deals with a converter with ZVS.
16. Any inquiry concerning this communication or earlier communications from the examiner should be directed to GARY NASH whose telephone number is (571) 270-3349. The examiner can normally be reached on Monday-Friday 8am-4pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner‘s supervisor, Thienvu Tran can be reached on (571) 270-1276. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/GARY A NASH/Primary Examiner, Art Unit 2838
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