DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
This office action is a response to a preliminary amendment filed on 06/24/2025, wherein claims 1-20 are cancelled, and claims 21-40 are newly added and presented for examination.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/01/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 24 is objected to because of the following informalities:
The limitation “… maintaining, by the SFA, dynamic associations between active sessions on the plurality of controlling hosts to the input/output buffers” appears to be grammatically incorrect. The examiner suggests rewriting the limitation to recite “… maintaining, by the SFA, dynamic associations between active sessions on the plurality of controlling hosts and the input/output buffers”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 40 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 40 recites the limitation “the switch” which lacks sufficient antecedent basis. Therefore, claim 40 is rendered indefinite.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21, 23, 26, 27, 30, 31, 33, 36, 37, 40 are rejected under 35 U.S.C. 103 as being unpatentable over Marolia et al. (US 20190297015), hereinafter Marolia, in view of Zhou et al. (US 2016/0094519), hereinafter Zhou.
Regarding claim 21, Mariola discloses a method comprising:
providing a server fabric adapter (SFA) connected to (i) a network, (ii) a plurality of controlling hosts, and (iii) a plurality of endpoints (Marolia, Fig. 2B: network interface (SFA) connected to a DC network, CPU Socket-0 and CPU Socket-1 (controlling hosts) and multiple accelerators (endpoints)), each controlling host from the plurality of controlling hosts comprising a central processing unit (CPU) (Marolia, [0022]: the computing elements connected to network interface (SFA) include general purpose CPUs), each endpoint from the plurality of endpoints comprising one or more of a graphics processing unit (GPU), a field-programmable gate array (FPGA), or an accelerator (Marolia, [0022]: the computing elements connected to network interface (SFA) include FPGAs and GPU based accelerators);
receiving, by the SFA, a network packet from the network, the network packet comprising a payload (Marolia, [0027]: network interface (SFA) receives a packet from a remote device; [0041], [0046]: the packet comprises a header and an accelerator payload);
separating, by the SFA, the network packet into the payload (Marolia, [0031]: separately routing a data portion (payload) and a control portion (header) of the packet);
sending, by the SFA (Marolia, [0074]: received packets are distributed for processing by multiple CPUs or cores (controlling hosts); Fig. 2B, [0031]: routing a packet’s control portion (header) through host-to-device fabric 256-0 or 256-1); and
sending, by the SFA, the payload to an endpoint from the plurality of endpoints (Marolia, Fig. 2B, Fig. 3D, [0037]: DMA transfer of accelerator payload from the received packet to a destination buffer memory locally connected to an accelerator).
Marolia does not explicitly disclose the network packet comprising a plurality of headers; separating, by the SFA, the network packet into the plurality of headers; sending, by the SFA, each header from the plurality of headers to a respective controlling host from the plurality of controlling hosts.
However, Zhou discloses
receiving, by the SFA, a network packet from the network, the network packet comprising a plurality of headers and a payload (Zhou, [0062]: network I/O device (SFA) receives an incoming packet; [0050]: packet has L2 Ethernet, L3 IP and L4 TCP headers and PL payload);
separating, by the SFA, the network packet into the plurality of headers and the payload (Zhou, [0062]: parsing the packet into header segments and payload);
sending, by the SFA, each header from the plurality of headers to a respective controlling host from the plurality of controlling hosts (Marolia, [0048]-[0049], [0061]: network I/O device (SFA) writes the L2/L3/L4 header portion of the packet to the cache of a corresponding (respective) CPU (controlling host)).
It would have been obvious to one of ordinary skill in the art, having the teachings of Marolia and Zhou before him or her before the effective filing date of the claimed invention, to modify a packet processing network interface as taught by Marolia, to selectively deliver packet header portions to corresponding CPUs as taught by Zhou. The motivation for doing so would have been to reduce unnecessary cache/memory traffic, thereby improving packet processing efficiency.
Regarding claim 23, Marolia does not explicitly disclose wherein sending each header comprises mapping the header to the respective controlling host.
However, Zhou discloses wherein sending each header comprises mapping the header to the respective controlling host (Zhou, [0047], [0049]: distributing parsed packet portions (headers) according to the CPU corresponding to the I/O device queue, and using DCA controls to define which packet portions (headers) are sent to the respective CPU).
It would have been obvious to one of ordinary skill in the art, having the teachings of Marolia and Zhou before him or her before the effective filing date of the claimed invention, to modify a packet processing network interface as taught by Marolia, to selectively deliver packet header portions to corresponding CPUs as taught by Zhou. The motivation for doing so would have been to reduce unnecessary cache/memory traffic, thereby improving packet processing efficiency.
Regarding claim 26, Marolia discloses further comprising combining the payload with at least one of a PCIe header or a direct memory access (DMA) descriptor (Marolia, [0030, [0046]: network interface (SFA) uses DMA to copy a portion (payload) of a received packet through the accelerator fabric; [0023], [0025]: network interface (SFA) generates I/O requests for RDMA transfer over an accelerator fabric implemented using PCIe. [This implies the payload is combined with the PCIe header required for that PCIe request]).
Regarding claim 27, Marolia discloses wherein the SFA is a scalable and aggregated input/output (I/O) hub (Marolia, [0020], [0023], [0024]: multi-headed network controller/interface (SFA) connects host and accelerator fabrics, supports multiple primary and secondary heads and multiple high bandwidth I/O links (i.e., scalable), and processes I/O requests over those multiple heads (i.e., is a I/O hub)).
Regarding claim 30, Marolia discloses further comprising moving the plurality of headers and the payload over one or more disjoint physical interfaces (Marolia, [0023], [0025]: separate physical links to the host-to-device fabric and accelerator fabric).
Regarding claims 31, 33, 36, 37 and 40, the limitations have been addressed in the rejections of claims 21, 23, 26, 27 and 30, respectively.
Claims 22 and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Marolia in view of Zhou, further in view of Elzur (US 2003/0172342).
Regarding claim 22, Marolia and Zhou do not explicitly disclose wherein the plurality of headers comprises a transport header and an upper layer protocol (ULP) header.
However, Elzur discloses wherein the plurality of headers comprises a transport header and an upper layer protocol (ULP) header (Elzur, [0003], [0037], [0038]: TCP frame comprising TCP header (transport header) and ULP header).
It would have been obvious to one of ordinary skill in the art, having the teachings of Marolia, Zhou and Elzur before him or her before the effective filing date of the claimed invention, to modify a packet processing network interface as taught by Marolia and Zhou, to process packets having a transport header and ULP header as taught by Elzur. The motivation for doing so would have been to enable the receiver to identify and directly place ULP data carried in the transport packet, thereby reducing copying and processing overhead (Elzur, [0021], [0038]).
Regarding claim 32, the limitations have been addressed in the rejection of claim 22.
Claims 24 and 34 are rejected under 35 U.S.C. 103 as being unpatentable over Marolia in view of Zhou, further in view of Alanis et al. (US 2013/0179732), hereinafter Alanis.
Regarding claim 24, Marolia discloses wherein each endpoint from the plurality of endpoints is associated with an input/output buffer (Marolia, Fig. 2B: plurality of accelerators (endpoints); [0046]: a destination memory buffer (input/output buffer) is locally connected to an accelerator (endpoint)).
Marolia and Zhou do not explicitly disclose the method further comprises maintaining, by the SFA, dynamic associations between active sessions on the plurality of controlling hosts to the input/output buffers.
However, Alanis discloses the method further comprises maintaining, by the SFA, dynamic associations between active sessions on the plurality of controlling hosts to the input/output buffers (Alanis, [0040]-[0041], [0044]: network adapter (SFA) updates connection information including connection states such as active and posted transmit and receive buffers (input/output buffers). [The plurality of controlling hosts are already taught by Marolia and Zhou, to which Alanis’ session to buffer association is applied]).
It would have been obvious to one of ordinary skill in the art, having the teachings of Marolia, Zhou and Alanis before him or her before the effective filing date of the claimed invention, to modify a packet processing network interface as taught by Marolia and Zhou, to maintain and update connection information associating active communication sessions with transmit and receive buffers as taught by Alanis. The motivation for doing so would have been to support stateful offload processing while reducing host processing load and improving network throughput.
Regarding claim 34, the limitations have been addressed in the rejection of claim 24.
Claims 25 and 35 are rejected under 35 U.S.C. 103 as being unpatentable over Marolia in view of Zhou, further in view of Breakstone et al. (US 2018/0322082), hereinafter Breakstone.
Regarding claim 25, Marolia and Zhou do not explicitly disclose wherein each of the plurality of controlling hosts and the plurality of endpoints is associated with a respective peripheral component interconnect express (PCIe) address.
However, Breakstone discloses wherein each of the plurality of controlling hosts and the plurality of endpoints is associated with a respective peripheral component interconnect express (PCIe) address (Breakstone, [0117]-[0118]: multiple host processors (controlling hosts) each having a corresponding local PCIe address space; [0126]: identifying an address in the local address pace associated with a host processor; [0116], [0124]: plurality of GPUs (endpoints) having corresponding PCIe device/endpoint addresses).
It would have been obvious to one of ordinary skill in the art, having the teachings of Marolia, Zhou and Breakstone before him or her before the effective filing date of the claimed invention, to modify a packet processing network interface as taught by Marolia and Zhou, to associate the controlling hosts and endpoints with PCIe addresses as taught by Breakstone. The motivation for doing so would have been to provide non-colliding PCIe addressing, thereby preventing address collisions when routing PCIe traffic (Breakstone, [0132]).
Regarding claim 35, the limitations have been addressed in the rejection of claim 25.
Claims 28 and 38 are rejected under 35 U.S.C. 103 as being unpatentable over Marolia in view of Zhou, further in view of Jain et al. (US 2019/0173850), hereinafter Jain.
Regarding claim 28, Marolia and Zhou do not explicitly disclose further comprising performing a consistent hash function on the plurality of headers to identify the respective controlling hosts and the endpoint.
However, Jain discloses further comprising performing a consistent hash function on the plurality of headers to identify the respective controlling hosts and the endpoint (Jain, [0031], [0040], [0066]: using a consistent hash of packet header values (plurality of headers) to determine a processor (controlling host) and VTI; the VTI corresponds to a tunnel having endpoints).
It would have been obvious to one of ordinary skill in the art, having the teachings of Marolia, Zhou and Jain before him or her before the effective filing date of the claimed invention, to modify a packet processing network interface as taught by Marolia and Zhou, to use consistent hashing of packet header values to identify respective processors (controlling hosts) and endpoints as taught by Jain. The motivation for doing so would have been to enable data messages of the same flow to be processed by the same processing resources and path.
Regarding claim 38, the limitations have been addressed in the rejection of claim 28.
Claims 29 and 39 are rejected under 35 U.S.C. 103 as being unpatentable over Marolia in view of Zhou, further in view of Hung et al. (US 2011/0283068), hereinafter Hung.
Regarding claim 29, Marolia and Zhou do not explicitly disclose wherein the plurality of headers are sent to the respective controlling hosts and the payload is sent to the endpoint in parallel.
However, Hung discloses wherein the plurality of headers are sent to the respective controlling hosts and the payload is sent to the endpoint in parallel (Hung, [0040], [0042], [0035]: using separate access circuits for multiple headers and the payload; the data of the different packet areas are written to memory at the same time).
It would have been obvious to one of ordinary skill in the art, having the teachings of Marolia, Zhou and Hung before him or her before the effective filing date of the claimed invention, to modify a packet processing network interface as taught by Marolia and Zhou, to include transferring headers and payload in parallel as taught by Hung. The motivation for doing so would have been to reduce packet transfer time and increase packet access speed.
Regarding claim 29, the limitations have been addressed in the rejection of claim 39.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LESA M KENNEDY whose telephone number is (571)431-0704. The examiner can normally be reached Monday-Wednesday 9:30 am - 5:30 pm ET.
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The examiner also requests, in response to this Office Action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line no(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application.
/LESA M KENNEDY/Primary Examiner, Art Unit 2458
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