DETAILED ACTION
The present Office Action is in response to Applicant Arguments/Remarks and amended claims filed on 05/12/2026. Claims 1 and 7 have been amended. Claims 1-12 remain pending in the application.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No.KR10-2024-0135299, filed on 10/07/2024.
Response to Amendments and Arguments
Applicant’s amendment and remarks have been fully considered, with the Examiner’s response set forth below.
(1)Applicant contends that, regarding claims 4 and 10, Wells does not teach the recited limitation. Particularly, “Wells lacks any disclosure or suggestion of reducing or dynamically scaling the parallel write count (stripe count) in response to resource-constrained conditions where N exceeds a set threshold. Regarding "Stripe Count Representation," the Examiner incorrectly equates the "superblock size" or "number of streams" notification in Wells with the "stripe count" of the present invention … Wells fails to teach or suggest the controller's active capability to vary the stripe count per super memory block based on the real-time processing requirements indicated by N tags”. The Examiner respectively disagrees.
The argument is moot as Wells is no longer used to teach “stripe count”. The new ground of rejections relies on Kanno’841 for teaching the limitations recited in claims 2 and 8 which are the parent claims of claims 4 and 10.
(2) Applicant contends that, regarding claims 4 and 10, Wells does not teach the recited limitation. Particularly “Regarding ‘Stripe Count Determination based on N,’ the Examiner's reliance on Oh is misplaced, as Oh focuses solely on physical defect management. Oh teaches the selection of a ‘victim’ super memory block based on the number and location of bad blocks to facilitate data recovery … In contrast, the present invention performs dynamic resource management based on the number of tags (N) requested by the host, regardless of the physical health (i.e., bad block status) of the memory blocks. Therefore, the logic of determining a ‘stripe count’ to optimize parallel write performance under resource-constrained conditions is a technical feature entirely absent from Oh's defect-centric approach”. The Examiner respectively disagrees.
While Kanno’841 teaches the limitation recited in claim 2, “the controller determines a stripe count for each of the N target super memory blocks, and the stripe count for each of the N target super memory blocks represents a number of data units that can be written in parallel to the target super memory block”, Kanno’841 does not explicitly teach determining a stripe count for a number N of superblocks associated with a write command. Oh is used to remedy the deficiency since Oh teaches determining locations/count of bad blocks in superblocks associated in an access command. The data units can only be written to non-bad (normal) blocks of super blocks, therefore, a number of data units that can be written in parallel is determined by determining normal blocks in superblocks. The claim limitations do not preclude the use of a “defect-centric approach”.
(3) Applicant contends that, regarding claims 4 and 10, Wells does not teach the recited limitation. Particularly “The Examiner has cited Kim regarding the classification of superblocks based on the presence of ‘bad blocks’. However, the present invention is not directed to managing physical defects or bad block status. Instead, the invention manages active computational and bandwidth resources by varying the stripe count based on the number of concurrent streams (N). The technical objective of the present invention is to maintain maximum performance for a subset of default blocks (M) while efficiently allocating remaining resources to other target superblocks when the system is under high load (N > threshold). This active, load-based resource management logic is absent in Kim's bad-block-centric approach”. The Examiner respectively disagrees.
Since stripe count is specified as a number of data units that can be written in parallel to a superblock and the presence of bad blocks limits the number of data units that can be written in parallel for a superblock, when a number of bad/normal blocks are determined, the stripe count is determined. The claims do not appear to recite “varying the stripe count based on the number of concurrent streams (N)”.
(4) Applicant contends that, regarding claims 4 and 10, the combination of Wells, Gohain, Oh, Kim, and Song does not teach “the logic of dynamically throttling the parallel write count for specific superblocks to accommodate increased tag counts within a resource-limited environment”. The Examiner respectively disagrees.
Claims 4 and 10 do not appear to recite limitations requiring “the logic of dynamically throttling the parallel write count for specific superblocks to accommodate increased tag counts within a resource-limited environment”.
(5) The rest of the Applicant’s arguments are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
(6) Another iteration of claim analysis has been made. Refer to the corresponding sections of the claim analysis below for details.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wells et al. (US 2023/0289078), hereinafter Wells in view of Gohain et al. (US 2024/0289031), hereinafter Gohain, and further in view of Kanno (US2024/0311291), hereinafter Kanno’291.
Regarding claims 1 and 7, taking claim 1 as exemplary, Wells teaches a storage device, comprising:
a memory including a plurality of memory blocks (Wells, [0018], The storage device 100 includes … and a non-volatile memory 140 … The non-volatile memory 140 can therefore be referred to a memory array of dies as shown. Each of the dies 142 a-142 d, 144 a-144 d, 146 a-146 d, and 148 a-148 d has one or more planes. Each plane has multiple blocks); and
a controller (Wells, [0018], The storage device 100 includes at least a controller 120) configured to:
set a plurality of super memory blocks, each including at least one of the plurality of memory blocks (Wells, [0011], a superblock structure refers to a plurality of blocks grouped together; [0024], the superblock manager 130 can form superblocks from the dies 142 a-142 d, 144 a-144 d, 146 a-146 d, and 148 a-148 d by selecting or reselecting block locations (e.g., those dies 142 a-142 d, 144 a-144 d, 146 a-146 d, and 148 a-148 d or planes thereof) that form the superblocks);
receive, from a host, a write command requesting writing of a plurality of data units, the write command including N tags (Wells, [0037], the stream alignment command can indicate the superblock IDs), each tag indicating a value identifying a location of a super memory block to which at least one of the plurality of data units is to be written (Wells, [0037], The host 101 can notify the storage device 100 using a stream alignment command … the stream alignment command includes a stream ID and the indication that data corresponding to such stream ID (e.g., tagged with the stream ID) should be written to the one or more superblocks); and
write the plurality of data units to N target super memory blocks corresponding to the N tags, respectively, among the plurality of super memory blocks, wherein N is a natural number (Wells, [0040]).
Wells does not explicitly teach a plurality of data units and each tag indicating a value identifying a location of a super memory block, as claimed.
However, Wells in view of Gohain teaches a write command requesting writing of a plurality of data units (Gohain, [0054], Blocks 210 and blocks 215 may each include a plurality of data units 205. A data unit 205 may be an example of a subdivision of data such as a page, a codeword, a logical block, or any other subdivision of data; [0055], Respective characteristics for data units 205 may be identified by one or more indicators (e.g., a stream ID)).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Wells to incorporate teachings of Gohain to include a host write command requesting to write a plurality of data units to a plurality of super memory blocks indicated by super memory block IDs. A person of ordinary skill in the art would have been motivated to combine the teachings of Wells with Gohain because it improves efficiency and performance of the storage system disclosed in Wells by providing sufficient information in a write command for a storage device to perform the write command.
The combination of Wells does not explicitly teach each tag indicating a value identifying a location of a super memory block, as claimed.
However, the combination of Wells in view of Kanno’291 teaches each tag indicating a value identifying a location of a super memory block (Kanno’291, [0099], When each write command issued to the SSD3 is a write command which directly specifies a write destination super block, each write command includes the size of write data, the super block address, the start LBA, and the data pointer.).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Wells to incorporate teachings of Kanno’291 to include address/LBA for each super memory block as superblock tags in a write command. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Wells with Kanno’291 because it improves efficiency of the storage system disclosed in the combination of Wells by specifying write destination superblock for write data in a write command.
Claim 7 has similar limitations as claim 1 and is rejected for the similar reasons.
Claim(s) 2 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wells, Gohain, and Kanno’291 as applied to claims 1 and 7 above, and further in view of Kanno (US2019/0129841), hereinafter Kanno’841 and Oh et al. (US2018/0151251), hereinafter Oh.
Regarding claims 2 and 8, taking claim 2 as exemplary, the combination of Wells teaches all the features with respect to claim 1 as outlined above. The combination of Wells does not explicitly teach the storage device according to claim 1, wherein: the controller determines a stripe count for each of the N target super memory blocks based on a value of N, and the stripe count for each of the N target super memory blocks represents a number of data units that can be written in parallel to the target super memory block, as claimed.
However, the combination of Wells in view of Kanno’841 teaches the storage device according to claim 1, wherein: the controller determines a stripe count for each of the N target super memory blocks based on a value of N, and the stripe count for each of the N target super memory blocks represents a number of data units that can be written in parallel to the target super memory block (Kanno’841, [0075]; [0159], a defect information management table 33 corresponding to each of the super blocks is provided. In the defect information management table 33 for super block SB5, defect information (bit map) including 1-bit information indicative of being available or unavailable for each block).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Wells to incorporate teachings of Kanno’841 to determine a number of available blocks that can be accessed in parallel for each superblock, A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Wells with Kanno’841 because it improves efficiency of the storage system disclosed in the combination of Wells by determining status of superblocks in order to select the best candidate for processing.
The combination of Wells does not explicitly teach determines a stripe count for each of the N target super memory blocks based on a value of N, as claimed.
However, the combination of Wells in view of Oh teaches the storage device according to claim 1, wherein: the controller determines a stripe count for each of the N target super memory blocks based on a value of N (Oh, [0113], The controller 130 may detect the locations of bad blocks included in the respective bad super memory blocks and store the locations of the bad blocks in a bad block summary table; [0143], When the controller 130 tries to access any one among the plurality of super memory blocks included in the memory device 150, according to the access request, a corresponding super memory block may be a bad super block. The controller 130 may determine whether the access-requested super memory block is a bad super memory block based on the bad block summary table at step 617).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Wells to determine a number of bad/normal memory blocks in super memory blocks that are associated with an access request. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Wells with Oh because it improves efficiency and reliability of the storage system disclosed in the combination of Wells by ensuring bad memory blocks are not used for storing user data.
Claim 8 has similar limitations as claim 2 and is rejected for the similar reasons.
Claim(s) 3-5 and 9-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wells, Gohain, Kanno’291, Kanno’841, and Oh as applied to claims 2 and 8 above, and further in view of Kim et al. (US2020/0004462), hereinafter Kim.
Regarding claims 3 and 9, taking claim 3 as exemplary, the combination of Wells teaches all the features with respect to claim 2 as outlined above. The combination of Wells does not explicitly teach the storage device according to claim 2, wherein when N is equal to or smaller than a set threshold super memory block count, the controller sets the stripe count for each of the N target super memory blocks to a maximum stripe count, as claimed.
However, the combination of Wells in view of Kim teaches the storage device according to claim 2, wherein when N is equal to or smaller than a set threshold super memory block count, the controller sets the stripe count for each of the N target super memory blocks to a maximum stripe count (Kim, [0153], the controller 130 manages the super memory blocks SUPER BLOCK<0:4, N-2> by classifying them as first super blocks indicated as BAD+SUPERBLOCK0. Conversely, the normal super memory blocks SUPER BLOCK<5:N-3, N-1, N> are managed by being classified as second super blocks indicated as NORMAL SUPERBLOCK; [0154]; [0175]; [0179]-[0188]; Note – A controller manages two types of super blocks: BAD+SUPER-BLOCKs, which include at least one bad memory block in a superblock; and NORMAL SUPER-BLOCKs, which are entirely normal blocks (i.e. maximum number of good memory blocks for each stripe). If N is less than or equal to a predetermined Normal Superblock count threshold (i.e. 4, [0173]), then all N superblocks will be normal_superblocks).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Wells to incorporate teachings of Kim to use super-blocks with maximum number of normal memory blocks when the number of super-blocks required for a write command is less than or equal to a threshold value. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Wells with Kim because it improves efficiency of the storage system disclosed in the combination of Wells by avoiding excessively access bad memory blocks in order to prevent deterioration of overall performance of the storage system.
Claim 9 has similar limitations as claim 3 and is rejected for the similar reasons.
Regarding claims 4 and 10, the combination of Wells teaches all the features with respect to claim 3 as outlined above. The combination of Wells further teaches the storage device according to claim 3, wherein: when N is greater than the threshold super memory block count, the controller sets a stripe count for each of M default target super memory blocks among the N target super memory blocks to the maximum stripe count, and sets a stripe count of each of remaining target super memory blocks, excluding the M default target super memory blocks, to a value smaller than the maximum stripe count, and M is a natural number smaller than N (Kim, [0189]-[0192]; Note - if N is greater than a predetermined Normal Superblock count threshold (i.e. 4, [0173]), then the remaining number of super-blocks (N-4) will be BAD+SUPERBLOCKs (i.e. super-blocks with stripe count less than maximum as the super-blocks include at least one bad memory block.).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Wells to incorporate teachings of Kim to use super-blocks with less-than-maximum number of normal memory blocks when the number of super-blocks required for a write command is greater than a threshold value. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Wells with Kim because it improves efficiency of the storage system disclosed in the combination of Wells by avoiding excessively access bad memory blocks in order to prevent deterioration of overall performance of the storage system.
Claim 10 has similar limitations as claim 4 and is rejected for the similar reasons.
Regarding claims 5 and 11, taking claim 5 as exemplary, the combination of Wells teaches all the features with respect to claim 4 as outlined above. The combination of Wells further teaches the storage device according to claim 4, wherein the controller sets the stripe count for each of the remaining target super memory blocks to be equal to or greater than a minimum stripe count (Kim, [0154], the controller 130 differently manages the respective uses of the first super blocks BAD+SUPERBLOCK0 based on the numbers of the bad memory blocks included in the respective first super blocks BAD+SUPERBLOCK0. That is, the controller 130 manages first super blocks SUPER BLOCK<0, 2, 3, N-2>, each of which includes a number of bad memory blocks which is less than or equal to a preset number (e.g., 2),); Note – as such, the number of the normal memory blocks for each of the super-blocks is equal or greater than (M-2), M is the maximum number of normal memory blocks in a stripe.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Wells to incorporate teachings of Kim to select a partial superblock (BAD+SUPERBLOCK) for a write operation when the number of bad memory blocks of the partial superblock is less than or equal to a preset number. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Wells with Kim because it improves efficiency of the storage system disclosed in the combination of Wells by avoiding excessively access bad memory blocks in order to prevent deterioration of overall performance of the storage system.
Claim 11 has similar limitations as claim 5 and is rejected for the similar reasons.
Claim(s) 6 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wells, Gohain, Kanno’291, Kanno’841, Oh, and Kim as applied to claims 5 and 11 above, and further in view of Song et al. (US2025/0165154), hereinafter Song.
Regarding claims 6 and 12, taking claim 6 as exemplary, the combination of Wells teaches all the features with respect to claim 5 as outlined above. The combination of Wells does not explicitly teach the storage device according to claim 5, wherein the controller determines the stripe counts for the remaining target super memory blocks to be the same with each other, as claimed.
However, the combination of Wells in view of Song teaches the storage device according to claim 5, wherein the controller determines the stripe counts for the remaining target super memory blocks to be the same with each other (Song, [0144], the super block managing module 1234 may configure the number of memory blocks included in the first partial super block to be the same as the number of memory blocks included in the second partial super block. The super block managing module 1234 may configure the number of memory blocks included in a new additional super block to be the same as the number of memory blocks included in the first partial super block and/or the second partial super block.).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Wells to incorporate teachings of Song to configure partial/short super-blocks with a fixed number of memory blocks. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Wells with Song because it is easy for the storage system disclosed in the combination of Wells to store same amount of data in each of the super-blocks.
Claim 12 has similar limitations as claim 6 and is rejected for the similar reasons.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NANCI N WONG whose telephone number is (571)272-4117. The examiner can normally be reached Monday-Friday 9am -6pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached at 571-272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NANCI N WONG/ Primary Examiner, Art Unit 2137
Prosecution Insights