Prosecution Insights
Last updated: August 17, 2026
Application No. 19/038,333

APPARATUS AND METHOD FOR HIGH LINEARITY SLEW ENHANCEMENT ON AN OUTPUT BUFFER

Non-Final OA §103§112
Filed
Jan 27, 2025
Examiner
KIM, JUNG H
Art Unit
2836
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Analog Devices Inc.
OA Round
1 (Non-Final)
89%
Grant Probability
Favorable
1-2
OA Rounds
4m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
687 granted / 775 resolved
+20.6% vs TC avg
Moderate +6% lift
Without
With
+6.2%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 10m
Avg Prosecution
23 currently pending
Career history
787
Total Applications
across all art units

Statute-Specific Performance

§101
0.8%
-39.2% vs TC avg
§103
44.9%
+4.9% vs TC avg
§102
38.5%
-1.5% vs TC avg
§112
11.5%
-28.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 775 resolved cases

Office Action

§103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Election/Restrictions Applicant's election with traverse of Invention I in the reply filed June 8, 2026 is acknowledged. The traversal is on the ground(s) that prior art search for the elected invention overlaps with that of the non-elected invention(s). This is not found persuasive because of the separate classification and/or different search fields (e.g., different search queries) for the elected and non-elected invention(s). Claims 12-21 drawn to the non-elected invention(s) have been withdrawn from examination for patentability. The requirement is still deemed proper and is therefore made FINAL. Specification The Abstract stating “Aspects of the present disclosure provide for apparatuses, which may be highly linear precision output buffers, with enhanced slew rates. An apparatus in accordance with the present disclosure may comprise a first transistor” uses phrases which can be implied; the quoted portion should be changed to “Highly linear precision output buffers, with enhanced slew rates, comprising a first transistor”. A new Abstract with an amendment to remove such an implied phrase is required and must be presented on a separate sheet, apart from any other text. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claims 4-5 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. In claims 4-5, the claimed feature that the voltage at the gate of the first transistor is changed when the current through the biasing source and a current through the replica device is greater (claim 4) or less (claim 5) than the threshold current is inconsistent with the specification. For example, in Fig. 5, the voltage at the gate of M2 corresponding to the claimed second transistor changes instead when the current through M4 corresponding to the claimed replica device is greater or less than SET THRESHOLD corresponding to the claimed threshold current. Thus, the feature has been interpreted to require that the voltage at the gate of the second transistor is changed when a current through the replica device is greater (claim 4) or less (claim 5) than the threshold current. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over US 6,894,563 to Si. With respect to claims 1-2, Si discloses in Fig. 2 an apparatus comprising: a first transistor (e.g., M4); a second transistor (e.g., M2), coupled in cascode to the first transistor (e.g., M4); a biasing source (e.g., M5), coupled to the second transistor (e.g., M2, wherein M5 is coupled to M2 via M4); a replica device (e.g., M3 may be a replica of M4 as discussed below), coupled to the first transistor (e.g., M4); and a comparator (e.g., the differential to single ended current amplifier receiving I1-I2 as inputs and outputting I3 as per Col. 3 ll. 54-57), coupled to the biasing source (e.g., the differential to single ended current amplifier receiving I1-I2 as inputs and outputting I3 as per Col. 3 ll. 54-57 has inputs coupled to M5 via M1-M4) and the replica device (e.g., M3), wherein a slew rate of the first transistor (e.g., M4) is controlled based on a current through the replica device (e.g., M3) (e.g., current through M4 is controlled based on Vctrl, which in turn is based on I3, which in turn is based on current I1 through M3; thus, current through M4 is based on current through M3; when current through M4 is changed based on current through M3, a slew rate change of the current through M4 also occurs). Si fails to explicitly disclose that current mirror transistors M3-M4 in a differential amplifier M1-M5 in Fig. 2 has the same geometry. However, it was notoriously well known to a person of ordinary skill in the art before the effective filing date of the claimed invention that mirror transistors in a differential amplifier may have the same geometry so that the differential amplifier detects a difference in the differential input signals; an official notice of the foregoing fact is hereby taken. Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement current mirror transistors M3-M4 in a differential amplifier M1-M5 in Fig. 2 of Si using the notoriously well-known method of implementing mirror transistors in a differential amplifier to have the same geometry because such a modification allows the differential amplifier M1-M5 in Fig.2 of Si to detect a difference in the differential input signals. With respect to claim 3, the comparator (e.g., the differential to single ended current amplifier receiving I1-I2 as inputs and outputting I3 as per Col. 3 ll. 54-57) compares a current (e.g., I2 flows through M5) through the biasing source (e.g., M5) with a threshold current (e.g., I1). Allowable Subject Matter Claims 4-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jung KIM whose telephone number is (571)270-7964. The examiner can normally be reached on M-F from 9AM to 5:30PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Regis BETSCH, can be reached at (571)270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JUNG KIM/ Primary Examiner, Art Unit 2836
Read full office action

Prosecution Timeline

Jan 27, 2025
Application Filed
Aug 03, 2026
Non-Final Rejection mailed — §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
89%
Grant Probability
95%
With Interview (+6.2%)
1y 10m (~4m remaining)
Median Time to Grant
Low
PTA Risk
Based on 775 resolved cases by this examiner. Grant probability derived from career allowance rate.

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