DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-16 and 20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites a step of “generating the first clock signal by shifting the phase of the second clock signal by a delay equal to the second time period multiplied by a third number in the range from zero to the second number”. This limitation is unsupported by the specification as originally filed. The specification teaches that the third number is in a range from 1 to the second number [para. 0055: “...where P is a parameter defined by a user, preferably P is in the range from 1 to value cnt.”]. The Examiner additionally notes that the specification is inconsistent regarding this teaching, at times disclosing the third number as in para. 0055, while at other times disclosing the third number in the same manner as recited in claim 1 [e.g., para. 0013, 0014].
Claim 7 recites a step of “calculating an overage of the number of full periods of the third signal”. This limitation is unsupported by the specification as originally filed. The specification teaches calculating an average of the number of full periods of the third signal [para. 0076].
Claims 11 and 20 employ the same language and are rejected on the same basis.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 and 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “the third signal” in line 6. There is insufficient antecedent basis for this limitation in the claim. Claim 1 provides an original recitation of a “third periodic signal”. Consistent terminology should be employed when referencing previously established claim elements.
Claim 9 is rejected as being indefinite because it recites “a logic gate of exclusive OR (XOR) type”. MPEP 2173.05(b)(III)(E) indicates that “the addition of the word ‘type’ to an otherwise definite expression extends the scope of the expression so as to render it indefinite.” The Examiner notes claim 16 which omits this language and recites an exclusive OR (XOR) gate.
Claim 16 recites the limitations “the rising edge shift circuit” and “the falling edge shift circuit” in lines 2 and 3. There is insufficient antecedent basis for these limitations. Claim 15 provides an original recitation of a rising edge shift circuit and a falling edge shift circuit, but it is not a parent of claim 16.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang et al., U.S. Patent Application Publication No. 2007/0109880.
Regarding claim 17, Zhang discloses a method comprising:
communicating between a first electronic device [Fig. 1: digital circuit device 102] and a second electronic device [digital circuit device 104], the communicating including:
transmitting a plurality of data signals along a respective plurality of data transmission channels [Fig. 4: data bus A and data bus B]; and
generating a reception clock signal synchronized to each of the plurality of data signals [delay_clock_in_A, delay_clock_in_B], the generating the reception clock signal including:
generating a first clock signal [delay_clock_in_A, delay_clock_in_B] based on a second clock signal [clock_in_A, clock_in_B], the first and second clock signals having a same first time period [para. 0020, delay_clock_in_A/B is a delayed version of clock_in_A/B, therefore having the same period: “Slave delay module 408A receives the clock_in_A signal and generates a delayed_clock_in_A signal by delaying the clock_in_A signal's rising and falling edges by an amount of time corresponding to the D_count delay value.”], and based on a third periodic signal [Fig. 5: clock_ring; para. 0030: “ND corresponds to a number of clock_ring cycles that clock_in signal may be delayed to obtain a 90-degree phase shift.”] having a second time period equal to the first time period divided by a first number at least equal to two [Fig. 6: clock_ring period is at least half of clock_in period].
Regarding claim 18, Zhang teaches that the first clock signal is used to synchronize the plurality of data signals received by the first device [Fig. 4: delay_in_clock_A/B received as clk input for data-in-registers 406A and 406B].
Regarding claim 19, Zhang teaches that the communicating uses a single data rate protocol [para. 0049: clock speed of 200 MHz].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Akondy et al., U.S. Patent Application Publication No. 2017/0205845, discloses a method comprising:
generating a first clock signal based on a second clock signal, the first and second clock signals having a same first time period [para. 0015: “During the data transfer mode, the adaptive clock delay compensator circuit generates two clock signals—one clock signal is generated for the peripheral device and another clock signal is generated for a data interface... Both of these clock signals have the same frequency but the data interface clock signal is delayed by the adaptive clock delay compensator circuit with respect to the peripheral device clock signal by the delay value measured during the delay measurement mode and converted to the clock domain of the data transfer clock.”], and based on a third periodic signal having a second time period equal to the first time period divided by a first number greater than or equal to two [para. 0022: “For example, the frequency of the high frequency clock 153 may be approximately 10 times greater than the frequency of CLOCK generated during data transmission.”], the generating the first clock signal including:
counting a second number of full periods of the third signal [para. 0014: “In some embodiments, the adaptive clock delay compensator circuit generates a clock edge and counts cycles of a relatively high frequency counter clock until it detects the data signal edge. The number of clock cycles of the high frequency counter clock represents the delay value due, at least in part, to the cable length.”]; and
generating the first clock signal by shifting the phase of the second clock signal by a delay equal to the second time period multiplied by a third number in the range from zero to the second number [para. 0014: “Because the delay is measured in units of the number of clock cycles of the high frequency counter clock...”].
Ware et al., U.S. Patent No. 9,843,315, discloses a circuit for delaying a timing signal used in capturing data by comparing a phase of the timing signal with a calibration signal and adjusting the phase of the timing signal [abstract].
Dal Molin et al., U.S. Patent Application Publication No. 2012/0263218, discloses a system that calculates an offset between a master and slave clock by, in part, counting a number of full periods of a periodic signal having higher frequency than the master and slave clock [Fig. 3; para. 0052].
Kurd et al., U.S. Patent Application Publication No. 2004/0183613, discloses an invention that counts a number of pulses from a fast ring oscillator based on a period of time determined by a slow ring oscillator [para. 0074].
Chainer et al., U.S. Patent Application Publication No. 2004/0003193, discloses an invention adjusts a system clock phase by a delay that is a fractional amount of the system clock period [abtract].
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JI H BAE whose telephone number is (571)272-7181. The examiner can normally be reached Tuesday to Friday and every other Monday, 9 am to 6 pm.
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/JI H BAE/Primary Examiner, Art Unit 2176 U.S. Patent and Trademark Office
Phone: 571-272-7181
Fax: 571-273-7181
ji.bae@uspto.gov
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