DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or
nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-8, 10, 14-16, 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over [ Wasserstrom (US 11392450), hereinafter "Wasserstrom", in view of Chang (US 8446161), hereinafter "Chang" ].
As per claim 1, Wasserstrom significantly teaches a method for hardware integrity checks, the method comprising: receiving a first precomputed cyclic redundancy check (CRC) checksum of a first electronic component, wherein the first electronic component comprises a first eFuse (An OTP memory can be implemented, for example, by incorporating an electronic fuse (e-fuse) … into each memory cell.[Wasserstrom PP 0001], error detection code (e.g., a cyclic redundancy check (CRC) value) computed over the first set of data bits … is stored in an unused error detection code entry.[Wasserstrom PP 0017]);
receiving a first post computed CRC checksum of the first electronic component (computing a verification error detection code from the first set of data bits read from the OTP memory [Wasserstrom PP 0018]);
determining that the first precomputed CRC checksum is not equal to the first post computed CRC checksum (If the verification error detection code mismatches the error detection code read from the EDC entry, then a memory error may have occurred in the OTP memory. [Wasserstrom PP 0028]);
Wasserstrom does not explicitly teach “based on the determining that the first precomputed CRC checksum is not equal to the first post computed CRC checksum, transmitting an indication of an error”.
However, Chang, in an analogous art, teaches based on the determining that the first precomputed CRC checksum is not equal to the first post computed CRC checksum, transmitting an indication of an error (If a mismatch is detected, the test logic may issue a fail signal to an error monitor.[Chang PP 0023]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the eFuse integrity checking system disclosed by Wasserstrom to incorporate Chang's teachings of a built-in-self-test (BIST) component that operates during boot and mission mode, in order to provide redundant fault detection and enable the integrated circuit to self-test and self-repair in the field without external equipment (if the IC has the optional error monitor, a fault may be detected in the IC during mission mode. A signal may then be sent to the MUX to initiate process flow 300 [Chang PP 0027]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
As per claim 2, Wasserstrom significantly teaches receiving a second precomputed CRC checksum of a second electronic component, wherein the second electronic component comprises a second eFuse (the OTP memory includes a first set of data bits … and a second set of data bits [Wasserstrom PP 0016] multiple error detection code (EDC) entries.[Wasserstrom PP 0021]);
receiving a second post computed CRC checksum of the second electronic component (computing a verification error detection code from the first set of data bits read from the OTP memory. [Wasserstrom PP 0018] same computation applies to any eFuse component);
determining that the second precomputed CRC checksum is not equal to the second post computed CRC checksum (If the verification error detection code mismatches the error detection code read from the EDC entry, then a memory error may have occurred in the OTP memory. [Wasserstrom PP 0028] mismatch detection works for each eFuse);
Wasserstrom does not explicitly teach “based on the determining that the second precomputed CRC checksum is not equal to the second post computed CRC checksum, transmitting an indication of a second error”
However, Chang, in an analogous art, teaches based on the determining that the second precomputed CRC checksum is not equal to the second post computed CRC checksum, transmitting an indication of a second error (If a mismatch is detected, the test logic may issue a fail signal to an error monitor. [Chang PP 0023] each mismatch triggers its own error signal).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the eFuse integrity checking system disclosed by Wasserstrom to incorporate Chang's teachings of a built-in-self-test (BIST) component that operates during boot and mission mode, in order to provide redundant fault detection and enable the integrated circuit to self-test and self-repair in the field without external equipment (if the IC has the optional error monitor, a fault may be detected in the IC during mission mode. A signal may then be sent to the MUX to initiate process flow 300 [Chang PP 0027]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
As per claim 3, Wasserstrom does not explicitly teach “further comprising transmitting, based on the indication of the error, an indication to cease operation of one or more applications”
However, Chang, in an analogous art, teaches further comprising transmitting, based on the indication of the error, an indication to cease operation of one or more applications (If the IC has the optional error monitor, a fault may be detected … A signal may then be sent to the MUX to initiate process flow 300. [Chang PP 0027]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the eFuse integrity checking system disclosed by Wasserstrom to incorporate Chang's teachings of a built-in-self-test (BIST) component that operates during boot and mission mode, in order to provide redundant fault detection and enable the integrated circuit to self-test and self-repair in the field without external equipment (if the IC has the optional error monitor, a fault may be detected in the IC during mission mode. A signal may then be sent to the MUX to initiate process flow 300 [Chang PP 0027]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
As per claim 4, Wasserstrom does not explicitly teach “wherein the one or more applications comprise an autonomous driving application”
However, Chang, in an analogous art, teaches wherein the one or more applications comprise an autonomous driving application (If the IC has the optional error monitor, a fault may be detected … A signal may then be sent to the MUX to initiate process flow 300. [Chang PP 0027] the fault response applies to any application, including autonomous driving).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the eFuse integrity checking system disclosed by Wasserstrom to incorporate Chang's teachings of a built-in-self-test (BIST) component that operates during boot and mission mode, in order to provide redundant fault detection and enable the integrated circuit to self-test and self-repair in the field without external equipment (if the IC has the optional error monitor, a fault may be detected in the IC during mission mode. A signal may then be sent to the MUX to initiate process flow 300 [Chang PP 0027]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
As per claim 5, Wasserstrom significantly teaches wherein the first electronic component is integrated into an electric vehicle (An OTP memory can be implemented, for example, by incorporating an electronic fuse (e-fuse) … into each memory cell. [Wasserstrom PP 0001] the eFuse memory structure is suitable for electric vehicle integration).
As per claim 6, Wasserstrom significantly teaches wherein the precomputed CRC checksum is stored with the first eFuse (error detection code (e.g., a cyclic redundancy check (CRC) value) computed over the first set of data bits … is stored in an unused error detection code entry.[Wasserstrom PP 0017] the CRC is stored in the same memory array as the eFuse).
As per claim 7, Wasserstrom significantly teaches wherein the first precomputed CRC checksum was verified by using a hardware CRC checker before loading the first precomputed CRC checksum to on-chip memory of the first electronic component (reading an error detection code (e.g., stored CRC value) … computing a verification error detection code … determining that the computed verification error detection code matches the error detection code read. [Wasserstrom PP 0018] verification is performed by hardware and occurs prior to use).
As per claim 8, Wasserstrom does not explicitly teach “wherein the first electronic component uses, during boot, a built-in- self-test and a CRC check”
However, Chang, in an analogous art, teaches wherein the first electronic component uses, during boot, a built-in- self-test and a CRC check (The process begins as the IC is powered up (step 302) … The IC state as selected by the MUX is test/repair mode (step 304). [Chang PP 0025], In test/repair mode, the e-fuse data is loaded (step 306) … The BIST module is activated (step 308). [Chang PP 0026]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the eFuse integrity checking system disclosed by Wasserstrom to incorporate Chang's teachings of a built-in-self-test (BIST) component that operates during boot and mission mode, in order to provide redundant fault detection and enable the integrated circuit to self-test and self-repair in the field without external equipment (if the IC has the optional error monitor, a fault may be detected in the IC during mission mode. A signal may then be sent to the MUX to initiate process flow 300 [Chang PP 0027]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
As per claim 10, Wasserstrom does not explicitly teach “wherein the indication of the error causes a shutdown of a data flow”
However, Chang, in an analogous art, teaches wherein the indication of the error causes a shutdown of a data flow (A signal may then be sent to the MUX to initiate process flow 300. [Chang PP 0027]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the eFuse integrity checking system disclosed by Wasserstrom to incorporate Chang's teachings of a built-in-self-test (BIST) component that operates during boot and mission mode, in order to provide redundant fault detection and enable the integrated circuit to self-test and self-repair in the field without external equipment (if the IC has the optional error monitor, a fault may be detected in the IC during mission mode. A signal may then be sent to the MUX to initiate process flow 300 [Chang PP 0027]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
As per claim 14, Wasserstrom significantly teaches A method for hardware integrity checks, the method comprising: receiving a first precomputed cyclic redundancy check (CRC) checksum of a first electronic component, wherein the first electronic component comprises a first eFuse (An OTP memory can be implemented, for example, by incorporating an electronic fuse (e-fuse) … into each memory cell. [Wasserstrom PP 0001], error detection code (e.g., a cyclic redundancy check (CRC) value) computed over the first set of data bits for the corresponding programming session is stored in an unused error detection code entry in the second set of data bits. [Wasserstrom PP 0017]);
receiving a first post computed CRC checksum of the first electronic component (computing a verification error detection code from the first set of data bits read from the OTP memory. [Wasserstrom PP 0018]);
determining whether there is a first fault based on a mismatch of the first precomputed CRC checksum and the first post computed CRC checksum (If the verification error detection code mismatches the error detection code read from the EDC entry, then a memory error may have occurred in the OTP memory. [Wasserstrom PP 0055]);
based on determining that there is a first fault or a second fault, transmitting an indication of an error (If the verification error detection code mismatches … then a memory error may have occurred. [Wasserstrom PP 0055]).
Wasserstrom does not explicitly teach “determining whether there is a second fault based on a safety mechanism comprising a triple modular redundancy (TMR) or built-in-self-test (BIST);”
However, Chang, in an analogous art, teaches determining whether there is a second fault based on a safety mechanism comprising a triple modular redundancy (TMR) or built-in-self-test (BIST) (If a mismatch is detected, the test logic may issue a fail signal to an error monitor [Chang PP 0023])
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the eFuse integrity checking system disclosed by Wasserstrom to incorporate Chang's teachings of a built-in-self-test (BIST) component that operates during boot and mission mode, in order to provide redundant fault detection and enable the integrated circuit to self-test and self-repair in the field without external equipment (if the IC has the optional error monitor, a fault may be detected in the IC during mission mode. A signal may then be sent to the MUX to initiate process flow 300 [Chang PP 0027]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
As per claim 15, Wasserstrom does not explicitly teach “wherein the BIST comprises a logic built-in-self-test”
However, Chang, in an analogous art, teaches wherein the BIST comprises a logic built-in-self-test (The IC state as selected by the MUX is test/repair mode … The BIST module is activated. [Chang PP 0025-0026] BIST activated during test/repair mode is a standard implementation for testing logic circuits).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the eFuse integrity checking system disclosed by Wasserstrom to incorporate Chang's teachings of a built-in-self-test (BIST) component that operates during boot and mission mode, in order to provide redundant fault detection and enable the integrated circuit to self-test and self-repair in the field without external equipment (if the IC has the optional error monitor, a fault may be detected in the IC during mission mode. A signal may then be sent to the MUX to initiate process flow 300 [Chang PP 0027]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
As per claim 16, Wasserstrom does not explicitly teach “wherein the BIST comprises a memory built-in-self-test”
However, Chang, in an analogous art, teaches wherein the BIST comprises a memory built-in-self-test (The BIST module tests the memory array (step 309 ) [Chang PP 0026]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the eFuse integrity checking system disclosed by Wasserstrom to incorporate Chang's teachings of a built-in-self-test (BIST) component that operates during boot and mission mode, in order to provide redundant fault detection and enable the integrated circuit to self-test and self-repair in the field without external equipment (if the IC has the optional error monitor, a fault may be detected in the IC during mission mode. A signal may then be sent to the MUX to initiate process flow 300 [Chang PP 0027]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
As per claim 18, Wasserstrom significantly teaches wherein the precomputed CRC checksum is stored with the first eFuse (error detection code (e.g., a cyclic redundancy check (CRC) value) computed over the first set of data bits for the corresponding programming session is stored in an unused error detection code entry in the second set of data bits. [Wasserstrom PP 0017]).
As per claim 19, Wasserstrom significantly teaches wherein the first precomputed CRC checksum was verified by using a hardware CRC checker before loading the first precomputed CRC checksum to on-chip memory of the first electronic component (reading an error detection code (e.g., stored CRC value) … computing a verification error detection code … determining that the computed verification error detection code matches the error detection code read. [Wasserstrom PP 0018]).
As per claim 20, Wasserstrom does not explicitly teach “wherein the indication of the error causes a shutdown of a data flow”.
However, Chang, in an analogous art, teaches wherein the indication of the error causes a shutdown of a data flow (A signal may then be sent to the MUX to initiate process flow 300. [Chang PP 0027] initiating test/repair mode shuts down normal data flow).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the eFuse integrity checking system disclosed by Wasserstrom to incorporate Chang's teachings of a built-in-self-test (BIST) component that operates during boot and mission mode, in order to provide redundant fault detection and enable the integrated circuit to self-test and self-repair in the field without external equipment (if the IC has the optional error monitor, a fault may be detected in the IC during mission mode. A signal may then be sent to the MUX to initiate process flow 300 [Chang PP 0027]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
Claim(s) 9 are rejected under 35 U.S.C. 103 as being unpatentable over [ Wasserstrom, in view of Chang, in further view of Leger et al. (US Pub No. 20200242248), hereinafter "Leger"].
As per claim 9, Wasserstrom in view of Chang do not explicitly teach “wherein the first electronic component uses, during mission mode, a built-in-self-test and triple modular redundancy”
However, Leger, in an analogous art, teaches wherein the first electronic component uses, during mission mode, a built-in-self-test and triple modular redundancy (These include spatially or chronologically redundant implementation of critical operations, for example, by way of triple modular redundancy (TMR) [Leger PP 0010], the process registers (12, 13, 14) are designed as triply redundant. [Leger PP 0035]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the eFuse integrity checking system of Wasserstrom in view of Chang to incorporate Leger's teachings of a redundant implementation of the fuse read process for protecting process registers, in order to improve fault tolerance against transient faults in register storage during mission mode (FIG. 2 shows by way of example a redundant implementation of the read process of a fuse [Leger PP 0017]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
Claim(s) 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over [ Wasserstrom, in view of Cho (US 11599411), hereinafter "Cho"].
As per claim 11, Wasserstrom significantly teaches a system comprising:a first eFuse, which comprises a cyclic redundancy check (CRC) checksum of the first eFuse (An OTP memory can be implemented, for example, by incorporating an electronic fuse (e-fuse) … into each memory cell. [Wasserstrom PP 0001], error detection code (e.g., a cyclic redundancy check (CRC) value) computed over the first set of data bits for the corresponding programming session is stored in an unused error detection code entry in the second set of data bits. [Wasserstrom PP 0017]);
Wasserstrom does not explicitly teach “a second eFuse, which comprises a CRC checksum of the second eFuse”
However, Cho, in an analogous art, teaches a second eFuse, which comprises a CRC checksum of the second eFuse (According to example embodiments, an integrity check device includes a register array, and processing circuitry. The register array includes a plurality of registers that store a plurality of safety sensitive data forming one codeword. The processing circuitry generates a current cyclic redundancy check (CRC) parity value by sequentially performing a CRC calculation on the plurality of safety sensitive data, stores a reference CRC parity value, outputs a check result signal indicating whether an error occurs by activating a first path and by comparing the current CRC parity value with the reference CRC parity value when the plurality of safety sensitive data are maintained and when an operation of updating the reference CRC parity value is unnecessary, and updates the reference CRC parity value to the current CRC parity value by activating a second path when at least one of the plurality of safety sensitive data is intentionally changed and when the operation of updating the reference CRC parity value is necessary.[Cho PP 0008]) a register array with stored CRC parity for safety-sensitive data; this corresponds to a second eFuse with its own CRC checksum).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the eFuse integrity checking system disclosed by Wasserstrom to incorporate Cho's teachings of a dedicated integrity check device that generates a current CRC parity value, stores a reference CRC parity value, and outputs a check result signal indicating whether an error occurs, in order to improve the reliability and efficiency of the eFuse integrity verification (Cho teaches that an integrity check device “generates a current cyclic redundancy check (CRC) parity value by sequentially performing a CRC calculation on the plurality of safety sensitive data, stores a reference CRC parity value, outputs a check result signal indicating whether an error occurs”. [Cho PP 0008]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
As per claim 12, Wasserstrom significantly teaches wherein the system is integrated into an electric vehicle (An OTP memory can be implemented, for example, by incorporating an electronic fuse (e-fuse) … into each memory cell. [Wasserstrom PP 0001] eFuse memory system; integrating such a system into an electric vehicle is a routine application).
As per claim 13, Wasserstrom does not explicitly teach “wherein the system is compliant with Automotive Safety Integrity Level (ASIL) B or ASIL D”
However, Cho, in an analogous art, teaches wherein the system is compliant with Automotive Safety Integrity Level (ASIL) B or ASIL D (The register array includes a plurality of registers that store a plurality of safety sensitive data forming one codeword. … outputs a check result signal indicating whether an error occurs … when at least one of the plurality of safety sensitive data is intentionally changed [Cho PP 0008] error detection for safety-sensitive data; such mechanisms directly support meeting ASIL B/D integrity levels).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the eFuse integrity checking system disclosed by Wasserstrom to incorporate Cho's teachings of a dedicated integrity check device that generates a current CRC parity value, stores a reference CRC parity value, and outputs a check result signal indicating whether an error occurs, in order to improve the reliability and efficiency of the eFuse integrity verification (generates a current cyclic redundancy check (CRC) parity value by sequentially performing a CRC calculation on the plurality of safety sensitive data, stores a reference CRC parity value, outputs a check result signal indicating whether an error occurs [Cho PP 0008]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
Claim(s) 17 are rejected under 35 U.S.C. 103 as being unpatentable over [ Wasserstrom, in view of Chang, in further view of Cho].
As per claim 17, Wasserstrom in view of Chang do not explicitly teach “wherein the BIST comprises a software built-in-self-test”
However, Cho, in an analogous art, teaches wherein the BIST comprises a software built-in-self-test (The processing circuitry generates a current cyclic redundancy check (CRC) parity value by sequentially performing a CRC calculation on the plurality of safety sensitive data [Cho PP 0008] processing circuitry performing CRC calculation is typically implemented via software/firmware, which encompasses SWBIST).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the eFuse integrity checking system of Wasserstrom and Chang to incorporate Cho's teachings of a dedicated integrity check device that performs both a CRC integrity check and a reference CRC parity value update when safety sensitive data is intentionally changed, in order to efficiently and continuously perform the integrity check even after data modifications (when the at least one of the plurality of safety sensitive data is intentionally changed, the integrity check device and the electronic device may perform the update operation on the reference CRC parity value that is stored in the integrity check device. Accordingly, the integrity check operation may be continuously and efficiently performed not only on the initial values of the plurality of safety sensitive data but also when one or more safety sensitive data are modified by the user. [Cho PP 0011]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAREEM FUAD ALHWAMDEH whose telephone number is (571)272-5501. The examiner can normally be reached Mon-Fri 7:30-5:00.
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/KAREEM FUAD ALHWAMDEH/Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
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