DETAILED ACTION
Instant action is responsive to the communication received on 6/8/2026. Claims 1-20 are pending and have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 6/4/2026 and 6/26/2026 are being considered by the examiner.
Claim Language
Claims 2 and 3 recite limitations which, as claimed, are conditionally executed without accounting for the possibility of the condition failing to trigger.
The claims comprise limitation(s) that are not positively recited, as the limitations, as claimed, are conditionally executed without accounting for the possibility of the condition failing to trigger. The method may never be required to execute the conditions as the conditions are temporal conditional precedents that may never be reached within the scope of the claim under the broadest reasonable interpretation. The examiner recommends, for the limitations in claims 2 and 3 reciting executing a process based on a determination, reciting an additional limitation positively reciting the determination being made. (e.g. for claim 2, reciting a separate limitation stating, “determining that the first function is a memory bound function”; for claim 3, reciting a separate limitation stating, “determining that the second function is a compute bound operation”)
See Ex parte Schulhauser, Appeal No. 2013-007847, 2016 WL 6277792, at *9 (PTAB, Apr. 28, 2016) (precedential) (holding “The Examiner did not need to present evidence of the obviousness of the remaining method steps of the claim that are not required to be performed under a broadest reasonable interpretation of the claim”); see also Ex parte Katz, Appeal No. 2010-006083, 2011 WL 514314, at *4-5 (BPAI Jan. 27, 2011).” Board Decision pages 5-6, emphasis in original.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Malladi et al. (US 20190050325 A1) in view of De Santis et al. (US 20220100760 A1).
As per claim 1,
1. A method of processing in a memory, the method comprising: determining, by a host system, at least one feature associated with a data query for routing a first function of the data query to a destination processor; determining the destination processor based on the at least one feature; routing, based on the determination of the destination processor the first function of the data query to a memory base die for processing by a processing unit on the memory base die; and [Malladi teaches a system comprising HBM stacks, having a logic die (base die) and dies stacked above the logic die, and a host (para. 20-25; figs. 1-3 and associated paragraphs), where the host may process different functions, kernels, or portions of an application on a GPU or the HBM stack (para. 29-40; figs. 4-5B and associated paragraphs), with the HBM stack being offloaded computation work from host by implementing specialized logic functions for applications having special high bandwidth requirements (feature) (para. 24-25; figs 2-3 and associated paragraphs; also see para. 30 on AI applications being modified to use HBM stack for computation; see para. 43-44 fig. 6 on the logic die of the HBM+ stack comprising offloading processing logic section (processing unit) to perform processing operations (functions) from host)] processing, via the processing unit, data that a memory controller on the memory base die receives from at least one of one or more memory dies stacked on top of the memory base die. [Malladi teaches the logic section’s (processing unit) offloaded processing operations to be dependent on data stored in the stacked dies and a memory controller for interfacing with the stacked dies (para. 43-44; fig. 6 and associated paragraphs)]
Malladi does not explicitly disclose, but De Santis discloses:
a data query; the data query; the data query [Malladi does not explicitly disclose a query comprising operations; however, De Santis teaches a host-issued query comprising a command for performing operations (para. 29-30, 33-35, 49-50, 19; fig. 1 and associated paragraphs)]
Malladi and De Santis are analogous to the claimed invention because they are in the same field of endeavor involving data storage and memory access.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Malladi and De Santis, to modify the disclosures by Malladi to include disclosures by De Santis since they both teach data storage and memory access, wherein De Santis is directed towards improved processing performance (para. 5). Therefore, it would be applying a known technique (host issuing a query for performing operations) to a known device (a system for offloading certain operations to a stacked die structure) ready for improvement to yield predictable results (a system for offloading certain operations to a stacked die structure via a query comprising information for the operations in order to provide for more efficient transmission and processing of operations to be performed). MPEP 2143
As per claim 2, Malladi in view of De Santis teaches claim 1 as shown above and further teaches:
2. The method of claim 1, further comprising routing the first function to the memory base die for processing by the processing unit on the memory base die based on a determination that the first function is a memory bound function. [Malladi as shown above teaches the host processing different functions, kernels, or portions of an application on or the HBM stack (para. 29-40; figs. 4-5B), the HBM stack’s logic die being offloaded computation work related to applications with high bandwidth requirements (para. 24-25), the logic die’s logic section’s (processing unit) offloaded processing operations to be dependent on data stored in the stacked dies (para. 43-44; also see para. 30 on AI applications being modified to use HBM stack for computation, where being directed to HBM stack comprising memory may also correspond to being memory bound)]
As per claim 18,
18. A non-transitory computer-readable medium storing code that comprises instructions executable by at least one processor of a device to: [Malladi teaches a medium comprising instructions executable by one or more processors for implementing its disclosure (para. 56)] determine, by a host system, at least one feature associated with a data query for routing a first function of the data query to a destination processor; determine the destination processor based on the at least one feature; route, based on the determination of the destination processor, a first function of the data query to a memory base die for processing by a processing unit on the memory base die; and [Malladi teaches a system comprising HBM stacks, having a logic die (base die) and dies stacked above the logic die, and a host (para. 20-25; figs. 1-3 and associated paragraphs), where the host may process different functions, kernels, or portions of an application on a GPU or the HBM stack (para. 29-40; figs. 4-5B and associated paragraphs), with the HBM stack being offloaded computation work from host by implementing specialized logic functions for applications having special high bandwidth requirements (feature) (para. 24-25; figs 2-3 and associated paragraphs; also see para. 30 on AI applications being modified to use HBM stack for computation; see para. 43-44 fig. 6 on the logic die of the HBM+ stack comprising offloading processing logic section (processing unit) to perform processing operations (functions) from host)] process, via the processing unit, data that a memory controller on the memory base die receives from at least one of one or more memory dies stacked on top of the memory base die. [Malladi teaches the logic section’s (processing unit) offloaded processing operations to be dependent on data stored in the stacked dies and a memory controller for interfacing with the stacked dies (para. 43-44; fig. 6 and associated paragraphs)]
Malladi does not explicitly disclose, but De Santis discloses:
data query; data query; data query [Malladi does not explicitly disclose a query comprising operations; however, De Santis teaches a host-issued query comprising a command for performing operations (para. 29-30, 33-35, 49-50, 19; fig. 1 and associated paragraphs)]
Malladi and De Santis are analogous to the claimed invention because they are in the same field of endeavor involving data storage and memory access.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Malladi and De Santis, to modify the disclosures by Malladi to include disclosures by De Santis since they both teach data storage and memory access, wherein De Santis is directed towards improved processing performance (para. 5). Therefore, it would be applying a known technique (host issuing a query for performing operations) to a known device (a system for offloading certain operations to a stacked die structure) ready for improvement to yield predictable results (a system for offloading certain operations to a stacked die structure via a query comprising information for the operations in order to provide for more efficient transmission and processing of operations to be performed). MPEP 2143
As per claim 19, Malladi in view of De Santis teaches claim 18 as shown above and further teaches:
19. The non-transitory computer-readable medium of claim 18, wherein the code includes further instructions executable by the processor to route the first function to the memory base die for processing by the processing unit on the memory base die based on a determination that the first function is a memory bound function. [Malladi as shown above teaches the host processing different functions, kernels, or portions of an application on or the HBM stack (para. 29-40; figs. 4-5B), the HBM stack’s logic die being offloaded computation work related to applications with high bandwidth requirements (para. 24-25), the logic die’s logic section’s (processing unit) offloaded processing operations to be dependent on data stored in the stacked dies (para. 43-44; also see para. 30 on AI applications being modified to use HBM stack for computation, where being directed to HBM stack comprising memory may also correspond to being memory bound)]
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Malladi et al. (US 20190050325 A1) in view of De Santis et al. (US 20220100760 A1) in view of Gu et al. (US 20200184001 A1).
As per claim 3, Malladi in view of De Santis teaches claim 1 as shown above and further teaches:
3. The method of claim 1, further comprising: routing a second function of the data query to a compute die for processing by the compute die based on a determination that the second function is a compute bound operation, [Instant limitation is not positively recited, as the limitation, as claimed, is conditionally executed without accounting for the possibility of the condition failing to trigger (i.e. determination being made that the second function is a compute bound operation). The method may never be required to execute the condition as the condition is a temporal conditional precedent that may never be reached within the scope of the claim under the broadest reasonable interpretation. The examiner recommends reciting an additional limitation positively reciting the determination being made. (please see the Claim Language section above). Provided with the corresponding amendment as suggested, instant claim may be considered allowable subject matter pending a further rewrite in independent form including all of the limitations of the base claim and instant claim (please see the allowable subject matter section pertaining to claim 20 below)]
Malladi in view of De Santis in view of Binfet does not explicitly disclose, but Gu discloses:
wherein the compute die is connected to the memory base die via a silicon interposer of a system in package that includes the compute die and the memory base die. [Malladi teaches interposer connected to the host as well as the logic die (Malladi: para. 23; fig. 2 and associated paragraphs); it does not explicitly disclose the interposer as silicon interposer, but Gu discloses a die stack offloading computations from a processor, the die stack and the processor both placed on a silicon interposer (para. 46-47; fig. 4 and associated paragraphs)]
The disclosures by Malladi, De Santis, and Gu are analogous because they are in the same field of endeavor of data storage and memory access.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Malladi in view of De Santis and Gu, to modify the teachings of Malladi in view of De Santis to include the teaching of Gu since they both teach data storage and memory access, wherein Gu is directed towards improved accelerator performance (para. 2-5). Therefore, it would have been a simple substitution of one type of non-volatile interposer with another interposer (silicon interposer) ready for improvement to provide predictable results (improved performance over alternatives such as organic interposers). MPEP 2143
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Malladi et al. (US 20190050325 A1) in view of De Santis et al. (US 20220100760 A1) in view of Nygren et al. (US 20240004583 A1).
As per claim 4, Malladi in view of De Santis discloses claim 1 as shown above. It does not explicitly disclose, but Nygren discloses:
4. The method of claim 1, wherein the memory base die comprises a memory expansion port connected to at least one of a low power double data rate memory or a graphics double data rate memory external to the memory base die. [Malladi in view of De Santis as shown above teaches memory controller of the logic die interfacing with the stacked HBM dies (Malladi: para. 24-25, 43); it does not explicitly provide for, but Nygren teaches a memory controller interfacing with various types of memory including HBM and external GDDR memory, where the memory controller may comprise a port for connecting to the GDDR memory, and the memory controller may store data associated with write commands to GDDR for determining whether the data comprises poisoned data related to unrecoverable error (para. 53, 21, 32-33, 1-2; figs. 2-3 and associated paragraphs)]
The disclosures by Malladi, De Santis, and Nygren are analogous because they are in the same field of endeavor of data storage and memory access.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Malladi in view of De Santis and Nygren to modify the teachings of Malladi in view of De Santis to include the teaching of Nygren since they both teach data storage and memory access, wherein Nygren is directed to improved system stability (para. 1-2). Therefore, it would be applying a known technique (memory controller connected to HBM and external GDDR, the memory controller to determine presence of unrecoverable error in data using the GDDR) to a known device (a system having a memory controller interfacing with HBM memory) ready for improvement to yield predictable results (a system having a memory controller interfacing with HBM memory and further connected to a GDDR memory used to determine presence of unrecoverable error in data). MPEP 2143
As per claim 5, Malladi in view of De Santis in view of Nygren teaches claim 1 as shown above and further teaches:
5. The method of claim 4, further comprising at least one of: routing, via the memory controller, functions of a first category to the memory base die for processing by the processing unit on the memory base die, routing, via the memory controller, functions of a second category to a compute die for processing by the compute die, or routing, via the memory controller, functions of a third category to at least one of the low power double data rate memory or the graphics double data rate memory external to the memory base die. [Malladi in view of De Santis in view of Nygren as shown above teaches the memory controller storing data associated with write commands to GDDR for determining whether the data comprises poisoned data associated with unrecoverable error (see claim 4 above; Nygren: para. 32-33)]
The disclosures by Malladi, De Santis, and Nygren are analogous because they are in the same field of endeavor of data storage and memory access.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Malladi in view of De Santis and Nygren to modify the teachings of Malladi in view of De Santis to include the teaching of Nygren since they both teach data storage and memory access, wherein Nygren is directed to improved system stability (para. 1-2). Therefore, it would be applying a known technique (memory controller connected to HBM and external GDDR, the memory controller to determine presence of unrecoverable error in data using the GDDR) to a known device (a system having a memory controller interfacing with HBM memory) ready for improvement to yield predictable results (a system having a memory controller interfacing with HBM memory and further connected to a GDDR memory used to determine presence of unrecoverable error in data). MPEP 2143
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Malladi et al. (US 20190050325 A1) in view of De Santis et al. (US 20220100760 A1) in view of Breternitz et al. (US 20180081583 A1).
As per claim 6, Malladi in view of De Santis discloses claim 1 as shown above. It does not explicitly disclose, but Breternitz discloses:
The method of claim 1, further comprising: transferring, by way of a through silicon via, the data from the one or more memory dies to a physical layer interface of the memory base die; transferring the data from the physical layer interface to the memory controller of the memory base die; and transferring the data from the memory controller to a shared memory on the memory base die, wherein the shared memory holds the data for processing of the data by the processing unit. [Breternitz teaches a memory module comprising a logic die having a memory controller connected to an external interface, the memory controller configured to access data in stacked dies having silicon vias responsive to memory access requests from processing elements on the logic die, the memory controller also comprising interface for connecting to the stacked dies and interface for connecting to processors in the logical die (para. 18-20, 24-25; figs. 1, 3 and associated paragraphs), where processors on the memory module can be grouped with a cache and configured to use data from the stacked dies (para. 26-28; fig. 4 and associated paragraphs)]
The disclosures by Malladi, De Santis, and Breternitz are analogous because they are in the same field of endeavor of data storage and memory access.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Malladi in view of De Santis and Breternitz to modify the teachings of Malladi in view of De Santis to include the teaching of Breternitz since they both teach data storage and memory access, wherein Breternitz is directed to improved data processing (para. 1, 16). Therefore, it would be applying a known technique (memory controller configured to access data from stacked memories having silicon via for processing units having a cache) to a known device (a system having a memory controller interfacing with HBM memory) ready for improvement to yield predictable results (memory controller configured to access data from stacked memories having silicon via for processing units having a cache to provide support processing in memory utilizing data in the stacked memories). MPEP 2143
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Malladi et al. (US 20190050325 A1) in view of De Santis et al. (US 20220100760 A1) in view of Siegl et al. (US 20200081744 A1).
As per claim 7, Malladi in view of De Santis teaches claim 1 as shown above. It does not explicitly disclose, but Siegl discloses:
7. The method of claim 1, wherein the processing unit comprises at least one of: a tensor core configured for matrix multiplication, or an accumulator configured for accumulating intermediate calculations. [Malladi in view of De Santis as shown above teaches a logic sector on the logic die (processor) for performing offloaded operations and teaches functions executable by the logic die including matrix element swap, linear algebra related operations, and accumulation in convolution neural network, among others (see claim 1 above; Malladi: para. 47-48; table 1); it does not explicitly recite the logic section as performing matrix multiplication, but Siegl teaches accelerators involved in matrix to matrix operations and accumulating intermediate calculations (para. 4)]
Malladi, De Santis, and Siegl are analogous to the claimed invention because they are in the same field of endeavor involving data storage and memory access.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Malladi in view of De Santis and Siegl, to modify the disclosures by Malladi in view of De Santis to include disclosures by Siegl since they both teach data storage and memory access, wherein Siegl is directed towards improved computing performance (para. 1-3, 25). Therefore, it would be applying a known technique (accelerator configured to perform matrix to matrix operations or accumulation of intermediate calculations) to a known device (processor performing functions including matrix element swap, linear algebra related operations, and accumulation in convolution neural network) ready for improvement to yield predictable results (processor performing linear algebra or neural network-related processes including those involving matrix to matrix operations or accumulation of intermediate calculations in order to provide for reducing calculation overhead of the computing die or a host). MPEP 2143
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Malladi et al. (US 20190050325 A1) in view of De Santis et al. (US 20220100760 A1) in view of Fang et al. (US 20090300292 A1) in view of Litt et al. (US 20250085875 A1).
As per claim 8, Malladi in view of De Santis teaches claim 1 as shown above. It does not explicitly disclose, but Fang discloses:
8. The method of claim 1, wherein: the memory controller connects to the processing unit via a network on chip (NOC) interconnect bus, and [Fang teaches a network on a chip, which may be a single die integrated circuit that connects components including cores, specializer processors, accelerators, local memories, and other such structures through interconnect links (Fang: para. 11; fig. 1 and associated paragraphs)]
Malladi, De Santis, and Fang are analogous to the claimed invention because they are in the same field of endeavor involving data storage and memory access.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Malladi in view of De Santis and Fang, to modify the disclosures by Malladi in view of De Santis to include disclosures by Fang since they both teach data storage and memory access, wherein Fang is directed towards improved memory system performance (para. 1-3, 28). Therefore, it would be applying a known technique (use of network on chip interconnect links for within a chip) to a known device (logic die comprising a plurality of components including a processor and memory controller) ready for improvement to yield predictable results (logic die comprising network on chip interconnect links connecting a plurality of components in the die including a processor and a memory controller to provide for improved scalability and/or latency). MPEP 2143
Malladi in view of De Santis in view of Fang does not explicitly disclose, but Litt discloses:
the memory controller connects to a dynamic random-access memory (DRAM) physical layer on the memory base die via a double data rate (DDR) physical layer interface of the memory base die. [Malladi in view of De Santis as shown above teaches a memory controller interfacing with stacked dies (see claim 1 above; Malladi: para. 43-44); Litt teaches that HBM includes a stack of DRAM dies and a wide-interface architecture providing operation to the stack of DRAM dies across multiple interfaces operating at double data rate (para. 2, 20; figs. 1-2 and associated paragraphs)]
Malladi, De Santis, Fang, and Litt are analogous to the claimed invention because they are in the same field of endeavor involving data storage and memory access.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Malladi in view of De Santis in view of Fang and Litt, to modify the disclosures by view of Malladi in view of De Santis in view of Fang to include disclosures by Litt since they both teach data storage and memory access, wherein Litt is directed towards improved memory performance (para. 2-3, 23). Therefore, it would be applying a known technique (HBM connecting to DRAM dies using interfaces operating at double data rate) to a known device (logic die comprising a memory controller interfacing with stacked HBM dies) ready for improvement to yield predictable results (logic die comprising a memory controller connecting to DRAM die stack above the accelerator die using double data rate interfaces operating at double data rate to provide for compatible connection with the DRAM dies). MPEP 2143
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Malladi et al. (US 20190050325 A1) in view of De Santis et al. (US 20220100760 A1) in view of Fang et al. (US 20090300292 A1) in view of Litt et al. (US 20250085875 A1) in view of Jin et al. (US 20250077457 A1) in view of Shin et al. (US 20190272110 A1).
As per claim 9, Malladi in view of De Santis in view of Fang in view of Litt teaches claim 8 as shown above. It does not explicitly disclose, but Jin discloses::
9. The method of claim 8, wherein: a system bus interface connects to a die-to-die interface of the memory base die, and the processing unit connects to the system bus interface via the NOC interconnect bus, the system bus interface converting data in a die-to-die flit format to a network packet format. [Malladi in view of De Santis in view of Fang in view of Litt as shown above teaches NOC links connecting components in the logic die (see claim 8 above; Fang: para. 11); it does not explicitly disclose, but Jin discloses generating die-to-die flit from a first protocol type transaction of a first chiplet and transmitting the die-to-die interface flit to the second chiplet, the process involving the first chiplet encoding first protocol type transaction into a payload of a die-to-die interface flit, transmitting the payload of the die-to-die interface to an adapter layer for generating header and trailer for combining (converting to network packet format) with the payload for transmission to a second chiplet (abstract; para. 72-77)]
[Jin does not explicitly recite a bus for connecting the chiplets, but Shin teaches a memory bus connecting host and memory device, on different dies, via a memory bus including a die-to-die connection (para. 35; fig. 4 and associated paragraphs)]
Malladi, De Santis, and Fang are analogous to the claimed invention because they are in the same field of endeavor involving data storage and memory access.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Malladi in view of De Santis and Fang, to modify the disclosures by Malladi in view of De Santis to include disclosures by Fang since they both teach data storage and memory access, wherein Fang is directed towards improved memory system performance (para. 1-3, 28). Therefore, it would be applying a known technique (use of network on chip interconnect links for within a chip) to a known device (logic die comprising a plurality of components including a processor and memory controller) ready for improvement to yield predictable results (logic die comprising network on chip interconnect links connecting a plurality of components in the die including a processor and a memory controller to provide for improved scalability and/or latency). MPEP 2143
Malladi, De Santis, Fang, Litt, and Jin are analogous to the claimed invention because they are in the same field of endeavor involving data storage and memory access.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Malladi in view of De Santis in view of Fang in view of Litt and Jin, to modify the disclosures by Malladi in view of De Santis in view of Fang in view of Litt to include disclosures by Jin since they both teach data storage and memory access, wherein Jin is directed towards improved communication between dies (para. 1-6, 63-64). Therefore, it would be applying a known technique (conversion of protocol in a first chiplet for transmission to a second chiplet) to a known device (system comprising a logic die communicating with a host) ready for improvement to yield predictable results (system comprising a logic die communicating with a host, the communicating comprising converting protocols used within the logic die to a flit used for transmission in order to provide for improved communication between dies). MPEP 2143
Malladi, De Santis, Fang, Litt, Jin, and Shin are analogous to the claimed invention because they are in the same field of endeavor involving data storage and memory access.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Malladi in view of De Santis in view of Fang in view of Litt in view of Jin and Shin, to modify the disclosures by Malladi in view of De Santis in view of Fang in view of Litt in view of Jin to include disclosures by Shin since they both teach data storage and memory access, wherein Shin teaches utilization of memory bus supporting communication between host and memory device on different dies (para. 2-8, 35). Therefore, it would be applying a known technique (bus having die-to-die connection for connecting dies) to a known device (die-to-die interface on a die for communication) ready for improvement to yield predictable results (die-to-die interface connected to bus for communication between dies in order to provide for supporting communication between non-adjacent dies). MPEP 2143
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Malladi et al. (US 20190050325 A1) in view of De Santis et al. (US 20220100760 A1) in view of Pappu et al. (US 20190042240 A1).
As per claim 10, Malladi in view of De Santis teaches claim 1 as shown above. It does not explicitly disclose, but Pappu teaches:
10. The method of claim 1, wherein: the memory controller is communicatively coupled to the processing unit, and a second memory controller on the memory base die is communicatively coupled to a second processing unit on the memory base die. [Malladi teaches logic die having an offload processing logic section and memory controller that are connected (see claim 1 above; para. 41-4; fig. 6 and associated paragraphs); it does not explicitly disclose, but Pappu teaches an accelerator chip comprising a plurality of accelerators and a plurality of memory controllers that are connected (24-29; fig. 1 and associated paragraphs)]
Malladi, De Santis, and Pappu are analogous to the claimed invention because they are in the same field of endeavor involving data storage and memory access.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Malladi in view of De Santis and Pappu, to modify the disclosures by Malladi in view of De Santis to include disclosures by Pappu since they both teach data storage and memory access, wherein Pappu is directed towards improved offloading (para. 2). Therefore, it would be applying a known technique (accelerator die configured to offload tasks and having a plurality of accelerators and memory controllers) to a known device (logic die configured to offload tasks and having a processor and a memory controller) ready for improvement to yield predictable results (logic die configured to offload tasks and having multiple processors and multiple memory controllers to provide for improved bandwidth and computing capacity). MPEP 2143
Claims 11-12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Malladi et al. (US 20190050325 A1) in view of De Santis et al. (US 20220100760 A1) in view of Binfet et al. (US 20230137866 A1).
As per claim 11,
11. A system comprising: a host system configured to: determine at least one feature associated with a data query for routing a first function of the data query to a destination processor; and determine the destination processor based on the at least one feature; a memory base die, the memory base die comprising: a memory controller; one or more memory dies stacked on top of the memory base die; and [Malladi teaches a system comprising HBM stacks, having a logic die (base die) and dies stacked above the logic die, and a host (para. 20-25; figs. 1-3 and associated paragraphs), where the host may process different functions, kernels, or portions of an application on a GPU or the HBM stack (para. 29-40; figs. 4-5B and associated paragraphs), with the HBM stack being offloaded computation work from host by implementing specialized logic functions for applications having special high bandwidth requirements (feature) (para. 24-25; figs 2-3 and associated paragraphs; also see para. 30 on AI applications being modified to use HBM stack for computation; see para. 43-44 fig. 6 on the logic die of the HBM+ stack comprising offloading processing logic section (processing unit) to perform processing operations (functions) from host)] a processing unit configured to process data that the memory controller receives from at least one of the one or more memory dies, the data being routed to the processing unit based on the determination of the destination processor; [Malladi teaches the logic section’s (processing unit) offloaded processing operations to be dependent on data stored in the stacked dies and a memory controller for interfacing with the stacked dies (para. 43-44; fig. 6 and associated paragraphs)] a die-to-die interface that connects the memory base die to a compute die of a system in package. [The logic die comprises an interface to connect with the host (para. 6, 42; figs. 4-6, and associated paragraphs), where the host comprising at least a CPU and/or a GPU may correspond to a compute die (para. 23-25, 28; figs. 2, 4 and associated paragraphs)]
Malladi does not explicitly disclose, but De Santis discloses:
a data query; data query; Malladi does not explicitly disclose a query comprising operations; however, De Santis teaches a host-issued query comprising a command for performing operations (para. 29-30, 33-35, 49-50, 19; fig. 1 and associated paragraphs)]
Malladi and De Santis are analogous to the claimed invention because they are in the same field of endeavor involving data storage and memory access.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Malladi and De Santis, to modify the disclosures by Malladi to include disclosures by De Santis since they both teach data storage and memory access, wherein De Santis is directed towards improved processing performance (para. 5). Therefore, it would be applying a known technique (host issuing a query for performing operations) to a known device (a system for offloading certain operations to a stacked die structure) ready for improvement to yield predictable results (a system for offloading certain operations to a stacked die structure via a query comprising information for the operations in order to provide for more efficient transmission and processing of operations to be performed). MPEP 2143
Malladi in view of De Santis does not explicitly disclose, but Binfet discloses:
an interconnect that connects the memory controller to the one or more memory dies stacked on the memory base die and to multiple processing units that include the processing unit; and [Binfet discloses a memory sub-system comprising a data interface bus connecting local media controller to memory array and to one or more processing devices (para. 56-61, 32; figs. 1A, 3 and associated paragraphs)]
Malladi, De Santis, and Binfet are analogous to the claimed invention because they are in the same field of endeavor involving data storage and memory access.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Malladi in view of De Santis and Binfet, to modify the disclosures by Malladi in view of De Santis to include disclosures by Binfet since they both teach data storage and memory access, wherein Binfet is directed towards improved data bus utilization (para. 18). Therefore, it would be applying a known technique (data bus connecting local media controller to memory array and one or more processors) to a known device (logic die comprising a memory controller interfacing with stacked dies and connected to a processor) ready for improvement to yield predictable results (logic die comprising a memory controller interfacing with stacked dies and connected to one or more processors, where a data bus is utilized for connecting said components to provide for improved throughput). MPEP 2143
As per claim 12, Malladi in view of De Santis in view of Binfet teaches claim 11 as shown above and further teaches:
12. The system of claim 11, wherein a function of the data query is routed to the memory base die for processing by the processing unit based on a determination that the function is a memory bound function. [Malladi as shown above teaches the host processing different functions, kernels, or portions of an application on or the HBM stack (para. 29-40; figs. 4-5B), the HBM stack’s logic die being offloaded computation work related to applications with high bandwidth requirements (para. 24-25), the logic die’s logic section’s (processing unit) offloaded processing operations to be dependent on data stored in the stacked dies (para. 43-44; also see para. 30 on AI applications being modified to use HBM stack for computation, where being directed to HBM stack comprising memory may also correspond to being memory bound)]
As per claim 14, Malladi in view of De Santis in view of Binfet teaches claim 11 as shown above and further teaches:
14. The system of claim 11, wherein the system in package includes multiple memory base dies connected to the compute die, the multiple memory base dies including the memory base die. [Malladi teaches multiple HBM stacks connected to host (compute die) (para. 23-25; fig. 2 and associated paragraphs)]
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Malladi et al. (US 20190050325 A1) in view of De Santis et al. (US 20220100760 A1) in view of Binfet et al. (US 20230137866 A1) in view of Gu et al. (US 20200184001 A1).
As per claim 13, Malladi in view of De Santis in view of Binfet teaches claim 11 as shown above and further teaches:
13. The system of claim 11, wherein a function of a second data query is routed to the compute die for processing by the compute die based on a determination that the second function is a compute bound operation, [Malladi as shown above teaches the host may process different functions, kernels, or portions of an application on a GPU (compute die) or the HBM stack (see claim 11 above; para. 26-40; figs. 3-5B and associated paragraphs) and teaches GPUs used for performing computation (para. 21) where involving computation may correspond to being compute bound.]
Malladi in view of De Santis in view of Binfet does not explicitly disclose, but Gu discloses:
wherein the compute die is connected to the memory base die via a silicon interposer of the system in package. [Malladi teaches interposer connected to the host as well as the logic die (Malladi: para. 23; fig. 2 and associated paragraphs); it does not explicitly disclose the interposer as silicon interposer, but Gu discloses a die stack offloading computations from a processor, the die stack and the processor both placed on a silicon interposer (para. 46-47; fig. 4 and associated paragraphs)]
The disclosures by Malladi, De Santis, Binfet, and Gu are analogous because they are in the same field of endeavor of data storage and memory access.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Malladi in view of De Santis in view of Binfet and Gu, to modify the teachings of Malladi in view of De Santis in view of Binfet to include the teaching of Gu since they both teach data storage and memory access, wherein Gu is directed towards improved accelerator performance (para. 2-5). Therefore, it would have been a simple substitution of one type of non-volatile interposer with another interposer (silicon interposer) ready for improvement to provide predictable results (improved performance over alternatives such as organic interposers). MPEP 2143
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Malladi et al. (US 20190050325 A1) in view of De Santis et al. (US 20220100760 A1) in view of Binfet et al. (US 20230137866 A1) in view of Jin et al. (US 20250077457 A1).
As per claim 15, Malladi in view of De Santis in view Binfet teaches claim 11 as shown above. It does not explicitly disclose, but Jin discloses:
15. The system of claim 11, wherein: the memory base die comprises a system bus interface that connects the interconnect to the die-to-die interface of the memory base die, and the system bus interface maps a data format used by the interconnect to a data format used by the die-to-die interface. [Malladi in view of De Santis in view of Binfet as shown above teaches a data interface bus connecting components including processors, memory controller, and memory (see claim 11 above); it does not explicitly disclose, but Jin discloses a bus system connecting components (IP blocks) within a first chiplet and a controller of the first chiplet for converting requests of first protocol associated with the components of the first chiplet, as received from the bus system, to die-to-die interface flit for transmission to a second chiplet, wherein the controller is situated between the bus system of the first chiplet and PHY layer for transmitting the requests to the second chiplet via UCIe interface (abstract; para. 59-60; 72-77; figs. 1, 3 and associated paragraphs)]
Malladi, De Santis, Binfet, and Jin are analogous to the claimed invention because they are in the same field of endeavor involving data storage and memory access.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Malladi in view of De Santis in view of Binfet and Jin, to modify the disclosures by Malladi in view of De Santis in view of Binfet to include disclosures by Jin since they both teach data storage and memory access, where in Jin is directed towards improved communication between dies (para. 1-6, 63-64). Therefore, it would be applying a known technique (a controller for converting requests of first protocol received from the bus system of a chiplet and transmitting the converted requests to PHY layer of UCIe interface for transmission to a second chiplet) to a known device (a die comprising a data interface bus connecting components therein and an interface computing die) ready for improvement to yield predictable results (a controller for converting requests of first protocol received by the bus of a die and transmitting the converted requests to PHY layer of UCIe interface for transmission to a second chiplet in order to provide for improved communication between dies). MPEP 2143
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Malladi et al. (US 20190050325 A1) in view of De Santis et al. (US 20220100760 A1) in view of Binfet et al. (US 20230137866 A1) in view of Breternitz et al. (US 20180081583 A1).
As per claim 16, Malladi in view of De Santis in view Binfet teaches claim 11 as shown above. It does not explicitly disclose, but Breternitz discloses:
16. The system of claim 11, wherein the memory base die comprises a shared memory to share data between a first processing unit and a second processing unit of the multiple processing units. [Breternitz teaches a memory module comprising a logic die having a memory controller connected to an external interface, the memory controller configured to access data in stacked dies having silicon vias responsive to memory access requests from processing elements on the logic die, the memory controller also comprising interface for connecting to the stacked dies and interface for connecting to processors in the logical die (para. 18-20, 24-25; figs. 1, 3 and associated paragraphs), where processors on the memory module can be grouped with a cache and configured to use data from the stacked dies (para. 26-28; fig. 4 and associated paragraphs)]
The disclosures by Malladi, De Santis, Binfet, and Breternitz are analogous because they are in the same field of endeavor of data storage and memory access.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Malladi in view of De Santis in view of Binfet and Breternitz to modify the teachings of Malladi in view of De Santis in view of Binfet to include the teaching of Breternitz since they both teach data storage and memory access, wherein Breternitz is directed to improved data processing (para. 1, 16). Therefore, it would be applying a known technique (memory controller configured to access data from stacked memories having silicon via for processing units having a cache) to a known device (a system having a memory controller interfacing with HBM memory) ready for improvement to yield predictable results (memory controller configured to access data from stacked memories having silicon via for processing units having a cache to provide support processing in memory utilizing data in the stacked memories). MPEP 2143
Claims 17 is rejected under 35 U.S.C. 103 as being unpatentable over Malladi et al. (US 20190050325 A1) in view of De Santis et al. (US 20220100760 A1) in view of Binfet et al. (US 20230137866 A1) in view of Nygren et al. (US 20240004583 A1).
As per claim 16, Malladi in view of De Santis in view Binfet teaches claim 11 as shown above. It does not explicitly disclose, but Nygren discloses:
17. The system of claim 11, wherein the memory base die comprises a memory expansion port connected to at least one of a low power double data rate memory or a graphics double data rate memory external to the memory base die. [Malladi as shown above teaches memory controller of the logic die interfacing with the stacked HBM dies (Malladi: para. 24-25, 43); it does not explicitly provide for, but Nygren teaches a memory controller interfacing with various types of memory including HBM and external GDDR memory, where the memory controller may comprise a port for connecting to the GDDR memory, and the memory controller may store data associated with write commands to GDDR for determining whether the data comprises poisoned data related to unrecoverable error (para. 53, 21, 32-33, 1-2; figs. 2-3 and associated paragraphs)]
The disclosures by Malladi, De Santis, Binfet, and Nygren are analogous because they are in the same field of endeavor of data storage and memory access.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Malladi in view of De Santis in view of Binfet and Nygren to modify the teachings of Malladi in view of De Santis in view of Binfet to include the teaching of Nygren since they both teach data storage and memory access, wherein Nygren is directed to improved system stability (para. 1-2). Therefore, it would be applying a known technique (memory controller connected to HBM and external GDDR, the memory controller to determine presence of unrecoverable error in data using the GDDR) to a known device (a system having a memory controller interfacing with HBM memory) ready for improvement to yield predictable results (a system having a memory controller interfacing with HBM memory and further connected to a GDDR memory used to determine presence of unrecoverable error in data). MPEP 2143
Allowable Subject Matter
Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to claim 20, “… route a second function of the data query to a compute die for processing by the compute die based on a determination that the second function is a compute bound operation” in conjunction with the other limitations of the claim and the limitations of the base claim and any intervening claims, are not disclosed by the prior art of record.
The closest prior art of record are Malladi et al. (US 20190050325 A1), Pappu et al. (US 20190042240 A1), De Santis et al. (US 20220100760 A1), Shahim et al. (US 20210303346 A1),
Malladi teaches different portions of an application being executed on a HBM die stack or a GPU. Pappu teaches an accelerator die for directing requests to other destinations. De Santis teaches a host-issued query comprising a command for performing operations. Shahim teaches routing a command stream comprising queued commands.
However, the prior arts of record, neither individually nor in combination, teaches, a host determining at least one feature associated with a data query for routing a function, and, based on the determination, routing the first function of the data query to a memory base die for processing, where the memory base die comprises a processor for processing the first function, and where the host determines a second function of the data query as a compute bound operation and routes the second function of the data query to a compute die for processing by the compute die.
Therefore, the prior arts of record, neither individually nor in combination disclose, in conjunction with the other limitations of the claim and the limitations of the base claim and any intervening claims, the claim as a whole.
Response to Arguments
Applicant’s arguments, pertaining to the rejection pursuant to 35 USC 103 as relating to the independent claims as amended have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of a different interpretation of the previously applied reference and a newly found prior art reference (Malladi et al. (US 20190050325 A1), De Santis et al. (US 20220100760 A1), Binfet et al. (US 20230137866 A1)). Specifically, Malladi has been interpreted to provide for a host processing different portions of an application in a GPU or a HBM stack (para. 29-40; figs. 4-5B and associated paragraphs), with the HBM stack being offloaded computation work from host involving applications having special high bandwidth requirements (para. 24-25, 30, 43-44; please see the rejection(s) above). Applicant’s arguments with respect to the Pappu reference have been considered but are moot because the new ground of rejection does not rely on the Pappu reference in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/E.Y.K./Examiner, Art Unit 2135
/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135
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