DETAILED ACTION
This is in response to the application filed on January 27, 2025 in which claims 1 – 20 are presented for examination.
Status of Claims
Claims 1 – 20 are pending, of which claims 1, 12, and 18 are in independent form.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 1/27/2025, 10/23/2025, 1/27/2026, 6/4/2026, and 6/26/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 6, 8 – 10, and 12 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ramchandran et al., U.S. Patent Application 2022/0206869 (hereinafter referred to as Ramchandran) in view of Seo et al., U.S. Patent Application 2021/0110876 (hereinafter referred to as Seo).
Referring to claim 1, Ramchandran discloses “A method of” “memory access” (Fig. 3 memory interface die 304 with memory control logic 332), “the method comprising: receiving, at a base die processor on a base die of a stacked memory module, a first memory request for processing on a first memory die of multiple memory dies of the stacked memory module” (Fig. 2 along with [0029] multiple memory dies 202 (e.g., DRAM cores) stacked on a memory interface die 204 (e.g., a base logic die)” and “The memory interface die 204 is communicatively coupled to host processor system,” “Commands and data that are received from a memory controller at the memory interface die 204 and routed to the appropriate channel or pseudo channel in a memory die 202, and to the target memory bank”); “based on the first memory request being configured for processing on the first memory die,” utilizing “a processing unit on the first memory die” (Fig. 2 PIM unit 226 with PIM ALU 218); “sending the first memory request to the processing unit on the first memory die, the first memory request being processed on the first memory die based on” “sending the first memory request to the processing unit on the first memory die” (Fig. 2, [0029], and [0035] “Commands and data that are received from a memory controller at the memory interface die 204 and routed to the appropriate channel or pseudo channel in a memory die 202” and “The commands and data may include PIM commands and host-based data for executing those PIM commands in the PIM-enabled memory system 200”).
Ramchandran does not appear to explicitly disclose a “method of concurrent memory access” including “activating a processing unit on the first memory die,” “the first memory request being processed on the first memory die based on activating the processing unit on the first memory die,” and “deactivating the processing unit on the first memory die based on sending the first memory request to the processing unit on the first memory die.”
However, Seo discloses another PIM system and a “method of concurrent memory access” ([0015] “controlling a PIM operation by the first memory bank group to be performed together with processing of the memory requests” and [0017] “a first memory bank including a computation circuit configured to perform a processing in memory (PIM) operation; a second memory bank to process one or more memory requests concurrently with the PIM operation”) including “activating a processing unit on the first memory die” ([0039] and [0041] computation circuits 115a and 115b in memory banks 110a and 110b. Fig. 5 and [0063] “MV-mul” refers to a state in which a memory bank including a computation circuit and capable of performing the PIM operation performs a matrix vector multiplication operation as the PIM operation) “the first memory request being processed on the first memory die based on activating the processing unit on the first memory die” ([0063] “MV-mul” refers to a state in which a memory bank including a computation circuit and capable of performing the PIM operation performs a matrix vector multiplication operation as the PIM operation and [0080] r-PRE is a command to indicate the end of the pause of the PIM operation together with a precharge) and “deactivating the processing unit on the first memory die based on sending the first memory request to the processing unit on the first memory die” ([0006] and [0045] control circuit pausing the PIM operation of a memory bank group. [0077] command "P" is a command to pause the PIM operation by a target memory bank).
Ramchandran and Seo are analogous art because they are from the same field of endeavor, which is PIM methods.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Ramchandran and Seo before him or her, to modify the teachings of Ramchandran to include the teachings of Seo so that concurrent memory access is utilized and processing units are activated and deactivated.
The motivation for doing so would have been to improve performance by utilizing concurrent access as well as to save power by deactivating processing units when they are not needed (as stated by Seo at [0006]).
Therefore, it would have been obvious to combine Seo with Ramchandran to obtain the invention as specified in the instant claim.
As per claim 2, Ramchandran discloses “receiving, at the base die processor, a second memory request for processing on a second processing unit” (Fig. 2 along with [0029] multiple memory dies 202 (e.g., DRAM cores) stacked on a memory interface die 204 (e.g., a base logic die)” and “The memory interface die 204 is communicatively coupled to host processor system,” “Commands and data that are received from a memory controller at the memory interface die 204 and routed to the appropriate channel or pseudo channel in a memory die 202, and to the target memory bank”); “and providing data fetched from a second memory die of the stacked memory module to the second processing unit based on the second memory request” “based on the second processing unit being external to the multiple memory dies of the stacked memory module” ([0038] PIM units may be in memory interface die 304 or on accelerator die stacked on the memory dies, “data from the memory array must be passed”).
Ramchandran does not appear to explicitly disclose “wherein a processing unit on the second memory die remains deactivated.”
However, Seo discloses “providing data fetched from a second memory die of the stacked memory module to the second processing unit based on the second memory request, wherein a processing unit on the second memory die remains deactivated” ([0012] Each of the plurality of memory banks may include one or more dynamic random access memory (DRAM) arrays, and the memory request may be a DRAM request comprising at least one of read, write, copy, and erase. [0039] Each of the memory banks 110a and 110b includes the computation circuit 115a or the computation circuit 115b, and thus the memory bank 110a and the memory bank 110b may perform a PIM operation as well as process normal memory requests. Also, [0006] and [0045] control circuit pausing the PIM operation of a memory bank group. [0077] command "P" is a command to pause the PIM operation by a target memory bank).
Ramchandran and Seo are analogous art because they are from the same field of endeavor, which is PIM methods.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Ramchandran and Seo before him or her, to modify the teachings of Ramchandran to include the teachings of Seo so that concurrent memory access is utilized and processing units are activated and deactivated.
The motivation for doing so would have been to improve performance by utilizing concurrent access as well as to save power by deactivating processing units when they are not needed (as stated by Seo at [0006]).
Therefore, it would have been obvious to combine Seo with Ramchandran to obtain the invention as specified in the instant claim.
As per claim 3, Ramchandran discloses “the second memory request is processed on the second processing unit” (Fig. 2 along with [0029] multiple memory dies 202 (e.g., DRAM cores) stacked on a memory interface die 204 (e.g., a base logic die)” and “The memory interface die 204 is communicatively coupled to host processor system,” “Commands and data that are received from a memory controller at the memory interface die 204 and routed to the appropriate channel or pseudo channel in a memory die 202, and to the target memory bank.” [0035] “Commands and data that are received from a memory controller at the memory interface die 204 and routed to the appropriate channel or pseudo channel in a memory die 202” and “The commands and data may include PIM commands and host-based data for executing those PIM commands in the PIM-enabled memory system 200”).
Ramchandran does not appear to explicitly disclose “at least a portion of accessing data associated with the first memory request or processing the first memory request overlaps at least a portion of processing the second memory request on the second processing unit.”
However, Seo discloses another PIM system and a method of concurrent memory access wherein “at least a portion of accessing data associated with the first memory request or processing the first memory request overlaps at least a portion of processing the second memory request on the second processing unit” ([0015] “controlling a PIM operation by the first memory bank group to be performed together with processing of the memory requests” and [0017] “a first memory bank including a computation circuit configured to perform a processing in memory (PIM) operation; a second memory bank to process one or more memory requests concurrently with the PIM operation”).
Ramchandran and Seo are analogous art because they are from the same field of endeavor, which is PIM methods.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Ramchandran and Seo before him or her, to modify the teachings of Ramchandran to include the teachings of Seo so that concurrent memory access is utilized.
The motivation for doing so would have been to improve performance by utilizing concurrent access.
Therefore, it would have been obvious to combine Seo with Ramchandran to obtain the invention as specified in the instant claim.
As per claim 4, Ramchandran discloses “accessing data associated with the first memory request or processing the first memory request” ([0035] “Commands and data that are received from a memory controller at the memory interface die 204 and routed to the appropriate channel or pseudo channel in a memory die 202” and “The commands and data may include PIM commands and host-based data for executing those PIM commands in the PIM-enabled memory system 200”).
Ramchandran does not appear to explicitly disclose “at least a portion of accessing data associated with the first memory request or processing the first memory request overlaps at least a portion of fetching the data from the second memory die.”
However, Seo discloses another PIM system and a method of concurrent memory access wherein “at least a portion of accessing data associated with the first memory request or processing the first memory request overlaps at least a portion of fetching the data from the second memory die” ([0015] “controlling a PIM operation by the first memory bank group to be performed together with processing of the memory requests” and [0017] “a first memory bank including a computation circuit configured to perform a processing in memory (PIM) operation; a second memory bank to process one or more memory requests concurrently with the PIM operation”).
Ramchandran and Seo are analogous art because they are from the same field of endeavor, which is PIM methods.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Ramchandran and Seo before him or her, to modify the teachings of Ramchandran to include the teachings of Seo so that concurrent memory access is utilized.
The motivation for doing so would have been to improve performance by utilizing concurrent access.
Therefore, it would have been obvious to combine Seo with Ramchandran to obtain the invention as specified in the instant claim.
As per claim 5, Ramchandran discloses “the second processing unit comprises a processing unit on the base die of the stacked memory module or a graphical processing unit that is communicatively coupled to the base die processor of the stacked memory module” ([0038] PIM units may be in memory interface die 304 or on accelerator die stacked on the memory dies).
As per claim 6, Ramchandran discloses “data associated with the first memory request is stored in a memory bank of the first memory die, and data associated with the second memory request is stored in a memory bank of the second memory die” (Figs. 2 and 3 memory dies 202/302, each with memory banks 206/306. [0035] “Commands and data that are received from a memory controller at the memory interface die 204 and routed to the appropriate channel or pseudo channel in a memory die 202” and “The commands and data may include PIM commands and host-based data for executing those PIM commands in the PIM-enabled memory system 200.” Also, [0031] “a PIM register file 220 that includes multiple PIM registers for storing the result of a PIM computation as well as for storing data from the memory array and/or host-generated data that are used as operands of the PIM computation”).
As per claim 8, Ramchandran discloses “the multiple memory dies of the stacked memory module comprise one or more layers of memory dies stacked on top of the base die” (Figs. 2 and 3 along with [0029] memory dies 202/302 stacked on top of a memory interface die 204/304 (e.g., a base logic die)).
As per claim 9, Ramchandran discloses “the base die processor comprises an interposer connected to processing units on the base die of the stacked memory module, to processing units on the multiple memory dies of the stacked memory module, and to one or more graphical processing units connected to the stacked memory module” ([0029] “The I/O bus is implemented by TSVs that connect each memory die 202 to the memory interface die 204. The memory interface die 204 is communicatively coupled to host processor system (e.g., the computing device 150 of FIG. 1) through a high-speed link (e.g., a interposer wafer). Further, [0038] PIM units may be in memory interface die 304 or on accelerator die stacked on the memory dies).
As per claim 10, Ramchandran discloses “the base die processor is incorporated in a memory controller on the base die of the stacked memory module” (Fig. 3 memory control logic 332 of memory interface die 304).
Referring to claim 12, claim 1 recites the corresponding limitations as that of claim 12. Therefore, the rejection of claim 1 applies to claim 12.
Further, Seo discloses “based on the first memory request being configured for processing on the first memory die, modifying the first memory request, the modified first memory request being based on the base die processor adding an indicator that indicates to process the first memory request at the first memory die” ([0063] “MV-mul” refers to a state in which a memory bank including a computation circuit and capable of performing the PIM operation performs a matrix vector multiplication operation as the PIM operation. [0076] – [0077] The CCU may receive a command from the MC of the host processor and transfer the command to a command generator unit (CGU) in each memory bank. The CGU may receive a DRAM command, and a command and an address with respect to a PIM operation and convert the commands and the address into more detailed sub-commands); “and sending the modified first memory request to a processing unit on the first memory die, the first memory request being processed on the first memory die based on the indicator indicating to process the first memory request at the first memory die” ([0076] – [0077] MV-mul command may indicate a command for starting a matrix vector multiplication operation (a PIM operation)).
Note, claim 13 recites the corresponding limitations of claim 2. Therefore, the rejection of claim 2 applies to claim 13.
Note, claim 14 recites the corresponding limitations of claim 3. Therefore, the rejection of claim 3 applies to claim 14.
Note, claim 15 recites the corresponding limitations of claim 4. Therefore, the rejection of claim 4 applies to claim 15.
Note, claim 16 recites the corresponding limitations of claim 5. Therefore, the rejection of claim 5 applies to claim 16.
Note, claim 17 recites the corresponding limitations of claim 6. Therefore, the rejection of claim 6 applies to claim 17.
Referring to claim 18, claim 1 recites the corresponding limitations as that of claim 18. Therefore, the rejection of claim 1 applies to claim 18.
Further, Ramchandran discloses “A non-transitory computer-readable medium storing code that comprises instructions executable by a processor on a base die of a stacked memory module to” carry out the method of claim 1 ([0052] computer readable instructions).
Note, claim 19 recites the corresponding limitations of claim 2. Therefore, the rejection of claim 2 applies to claim 19.
Note, claim 20 recites the corresponding limitations of claim 3. Therefore, the rejection of claim 3 applies to claim 20.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Ramchandran in view of Seo, further in view of Kang et al., U.S. Patent Application 2023/0128183 (hereinafter referred to as Kang).
As per claim 7, Ramchandran discloses “the processing unit on the first memory die” (Fig. 2 PIM unit 226 with PIM ALU 218) and “a register of the stacked memory module” (Figs. 2 and 3 PIM register file 220).
Seo discloses “activating the processing unit on the first memory die” and “deactivating the processing unit on the first memory die” ([0039] and [0041] computation circuits 115a and 115b in memory banks 110a and 110b. Fig. 5 and [0063] “MV-mul” refers to a state in which a memory bank including a computation circuit and capable of performing the PIM operation performs a matrix vector multiplication operation as the PIM operation. [0080] r-PRE is a command to indicate the end of the pause of the PIM operation together with a precharge. [0006] and [0045] control circuit pausing the PIM operation of a memory bank group. [0077] command "P" is a command to pause the PIM operation by a target memory bank).
Neither Ramchandran nor Seo appears to explicitly disclose “activating the processing unit on the first memory die comprises toggling a bit of a register of the stacked memory module from a deactivation value to an activation value, and deactivating the processing unit on the first memory die comprises toggling the bit of the register from the activation value to the deactivation value.”
However, Kang discloses activating PIM mode comprises “toggling a bit of a register” “from a deactivation value to an activation value” and deactivating PIM mode comprises “toggling the bit of the register from the activation value to the deactivation value” ([0045] enter/exit of a PIM mode and [0106] PIM enter/exit code indicating PIM mode, using a register and “a PIM enter/exit code may be expressed in less than or more than 2 bits”).
Ramchandran, Seo, and Kang are analogous art because they are from the same field of endeavor, which is PIM methods.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Ramchandran, Seo, and Kang before him or her, to modify the teachings of Ramchandran and Seo to include the teachings of Kang so that a register bit is toggled from a deactivation value to an activation value and vice versa when the processing unit is activated/deactivated.
The motivation for doing so would have been to provide a simple means for tracking the status of a PIM circuit that can be utilized or bypassed.
Therefore, it would have been obvious to combine Kang with Ramchandran and Seo to obtain the invention as specified in the instant claim.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Ramchandran in view of Seo, further in view of Jayasena et al., U.S. Patent Application 2014/0181427 (hereinafter referred to as Jayasena) (from Applicant’s IDS).
As per claim 11, Ramchandran discloses “the base die processor” “on the base die of the stacked memory module” (Figs. 2 and 3 memory interface die 204/304 and memory control logic 332. [0029] memory interface die 204 (e.g., a base logic die)).
Neither Ramchandran nor Seo appears to explicitly disclose “the base die processor is incorporated in a snoop filter on the base die of the stacked memory module.”
However, Jayasena discloses another stacked memory module with PIM ([0008]) wherein “the base die processor is incorporated in a snoop filter on the base die of the stacked memory module” (Fig. 1 logic layer 120 and memory layers 110a-d. [0062] the logic layer implements a snoop filter).
Ramchandran, Seo, and Jayasena are analogous art because they are from the same field of endeavor, which is stacked memory and PIM methods.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Ramchandran, Seo, and Jayasena before him or her, to modify the teachings of Ramchandran and Seo to include the teachings of Jayasena so that the base die processor is incorporated in a snoop filter on the base die.
The motivation for doing so would have been to improve the performance and/or energy/power efficiency (as stated by Jayasena at [0062]).
Therefore, it would have been obvious to combine Jayasena with Ramchandran and Seo to obtain the invention as specified in the instant claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patent Application 20210200696 teaches a PIM device with an information gatherer.
U.S. Patent 11468001 teaches a PIM module for concurrently performing operations for multiple threads/applications.
U.S. Patent Applications 20220206817, 20220414013, 20230195375, 20230195459, 20230195645, 20240211256, 20240220164, 20240394199 and Patents 11921634, 11934698, 11934827, 12019560, 12393371, 12613808 teach PIM with stacked memory dies.
U.S. Patent Applications 20170344301, 20220036929, 20220068366, 20220406369, 20230094148, 20240004585, 20240103745, 20260003617 and Patents 10592467, 11139033, 11158357, 11462255, 11869571, 11977782, 12087388 teach activating and deactivating PIM mode.
Machine Translation of Japanese Patent Application JP 2019531546 A teaches a PIM method wherein each PIM processor has a register that allows the host CPU to control it.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN G SNYDER whose telephone number is (571)270-1971. The examiner can normally be reached on M-F 8:00am-4:30pm (flexible).
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/STEVEN G SNYDER/Primary Examiner, Art Unit 2184
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