DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
2. Claim 1 is objected to because of the following informalities: line 8 recites “a encoder” which should be corrected to “an encoder”.
Claim 5 is objected to because of the following informalities: claim recites “DSI” without properly defining the abbreviation.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 17 – 23 are rejected under 35 U.S.C. 103 as being unpatentable over Marena et al. (US Publication Number 2015/0199291, “Marena”) in view of Wiley (US Publication Number 2017/0019186).
5. As per claim 17, Marena teaches a design structure comprising: a first integrated circuit ("IC") component (110, figure 1), able to process digital information, configured to generate a first data stream formatted in a D-PHY data stream (generates D-PHY data stream on 112, figure 1); a field programmable gate arrays ("FPGA") (FPGA 130, figure 1) coupled to the first IC component (via 112 and 122, figure 1) and configured to be a bridge component (bridge between 110 and 150, figure 1, paragraph 8) configured to convert the first data steam to a second data steam formatted in a C-PHY data stream first stream inputted in figure 2 and second stream outputted at figure 5, from TX to RX); and a second IC component (599, figure 5) coupled to the FPGA and configured to receive the second data stream via a C-PHY bus (real time transmission of video data via bus 596/597, figure 5, to display paragraph 42).
Marena/Wang does not appear to explicitly disclose hardware description language (HDL) design structure encoded on a machine- readable data storage medium, the HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of data conversion between a D physical layer ("D-PHY") protocol and a C physical layer ("C- PHY") protocol.
However, Wiley discloses hardware description language (HDL) design structure (HDL known to be method to program FPGA, paragraph 130) encoded on a machine- readable data storage medium (encoded on medium, first and second IC, paragraph 9), the HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of data conversion between a D physical layer ("D-PHY") protocol and a C physical layer ("C- PHY") protocol (C-PHY, paragraph 49).
Marena and Wiley are analogous art because they are from the same field of endeavor of C-PHY/D-PHY handling.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Marena and Wiley before him or her, to modify the FPGA high level capabilities of Marena to include the programmable nature of Wiley because FPGAs are advanced forms of PLDs.
One of ordinary skill would be motivated to make such modification in order to enhance MIPI functionality (paragraphs 4 and 5). Therefore, it would have been obvious to combine Wiley with Marena to obtain the invention as specified in the instant claims.
6. Marena modified by the teachings of Wiley as seen in claim 17 above, as per claim 18, Marena teaches a design structure, wherein the first IC component is a camera processor capable of processing captured imaging data and formatting processed imaging data into D-PHY data stream (paragraph 8, 110 camera, figure 1).
7. Marena modified by the teachings of Wiley as seen in claim 17 above, as per claim 19, Marena teaches a design structure, wherein the second IC component is a display processor capable of displaying images in accordance with the second data stream (paragraph 8, 150 display, figure 1).
8. Marena modified by the teachings of Wiley as seen in claim 17 above, as per claim 20, Marena teaches a design structure, wherein the FPGA includes a D-PHY interface able to interface with the D-PHY bus to receive the first data from a camera (via 122, figure 1, paragraph 10).
9. Marena modified by the teachings of Wiley as seen in claim 17 above, as per claim 21, Wiley teaches a design structure, wherein the FPGA includes a first-in first-out ("FIFO") buffer configured to buffer the first data stream (FIFO 510, figure 5).
10. Marena modified by the teachings of Wiley as seen in claim 17 above, as per claim 22, Wiley teaches a design structure, wherein the FPGA includes a C-PHY circuit configured to fetch the first data stream from a FIFO buffer and convert the first data stream to the second data stream based on C-PHY protocol (fetch 506, convert via 508, FIFO 510, figure 5, paragraphs 70 - 72).
11. Marena modified by the teachings of Wiley as seen in claim 17 above, as per claim 23, Marena teaches a design structure, wherein the first IC component, the second IC component, and the FPGA are fabricated on a single semiconductor die (figure 2 on single semiconductor die, paragraphs 23 and 24).
12. Claims 1 – 9 are rejected under 35 U.S.C. 103 as being unpatentable over Ji et al. (US Patent Number 10,374,845, hereinafter “Ji”) in view of Wang et al. (US Publication Number 2018/0241382, “Wang”) further in view Marena.
13. As per claim 1, Ji teaches a device (figure 1) for converting data formatted in C physical layer ("C-PHY") to data formatted in D physical layer ("D-PHY"), comprising; a C-PHY block (10, figure 1) operated by a first portion of FPGA, and configured to receive incoming data from a plurality of lanes (A…C, figure 1) based on C-PHY protocol; a decoder (decoder 30, figure 1) operated by a second portion of FPGA and configured to generate decoded data (decoded data output to 40, figure 1) in accordance with the incoming data (generated by the circuitry seen in figures 3 and 4, Data_A/Data_B/Data_C as well as 20, figure 1).
Ji does not appear to explicitly disclose an interface bridging device situated in a field programmable gate arrays ("FPGA") and a encoder operated by a third portion of FPGA and configured to generating a first output in D-PHY protocol in response to the decoded data.
However, Wang discloses a encoder operated by a third portion of FPGA and configured to generating a first output in D-PHY protocol in response to the decoded data (C-PHY data figure 2 and 6, paragraphs 2 – 5, encoder function to convert decoded data figure 3a, D-PHY protocol output, figure 3b and 6)
Ji and Wang are analogous art because they are from the same field of endeavor of C-PHY/D-PHY handling.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Ji and Wang before him or her, to modify the processing of Ji to include the structure of Wang because it would allow enhanced protocol functionality.
One of ordinary skill would be motivated to make such modification in order to enhance connectivity for MIPI system management (paragraph 3). Therefore, it would have been obvious to combine Wang with Ji to obtain the invention as specified in the instant claims.
Ji/Wang does not appear to explicitly disclose interface bridging device situated in a field programmable gate arrays ("FPGA").
However, Marena discloses interface bridging device situated in a field programmable gate arrays ("FPGA") (FPGA bridging device 130 between 110 and 150, 250, figure 2, and 550, figure 5).
Ji/Wang and Marena are analogous art because they are from the same field of endeavor of C-PHY/D-PHY handling.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Ji/Wang and Marena before him or her, to modify the arrangement of Ji/Wang to include the structure of Marena because it allows for enhance connectivity between devices.
One of ordinary skill would be motivated to make such modification in order to enhance connectivity of MIPI/FPGA environment (paragraph 6). Therefore, it would have been obvious to combine Marena with Ji/Wang to obtain the invention as specified in the instant claims.
14. Ji modified by the teachings of Wang/Marena as seen in claim 1 above, as per claim 2, Ji teaches a device, further comprising a storage block (40, figure 1) coupled to the decoder and configured to temporarily buffer the decoded data (Marena, paragraph 36, packet header stored in FPGA buffer).
15. Ji modified by the teachings of Wang/Marena as seen in claim 1 above, as per claim 3, Marena teaches a device, further comprising a D-PHY transmitter coupled to a DSI D- PHY encoder and able to transmit values via a D-PHY bus (DSI protocol D-PHY transmission, figure 2, paragraphs 23 and 25).
16. Ji modified by the teachings of Wang/Marena as seen in claim 1 above, as per claim 4, Marena teaches a device, further comprising a low-power conversion block configured to facilitate power and timing conversions between the C-PHY block and a D-PHY transmitter (low power LP mode figures 3 and 6, paragraphs 29 and 32 and timing paragraph 32).
17. Ji modified by the teachings of Wang/Marena as seen in claim 1 above, as per claim 5, Marena teaches a device, further comprising a Display Stream Compression ("DSC") block coupled to a DSI C-PHY decoder and configured to compress the decoded data before storing at a storage block (display side processing, paragraphs 41 and 42, figure 5.
18. Ji modified by the teachings of Wang/Marena as seen in claim 1 above, as per claim 6, Marena teaches a device, further comprising a low-power ("LP") converter configured to adjust power requirements between D-PHY interface and C-PHY interface (low power LP mode figures 3 and 6, paragraphs 29 and 32).
19. Ji modified by the teachings of Wang/Marena as seen in claim 1 above, as per claim 7, Marena teaches a device, wherein further the decoder is a display serial interface ("DSI") C-PHY decoder (DSI protocol, paragraphs 41 and 42, via Ji’s C-PHY 30, figure 1).
20. Ji modified by the teachings of Wang/Marena as seen in claim 1 above, as per claim 8, Marena teaches a device, wherein the encoder is a DSI D-PHY encoder configured to generating values based on D-PHY protocol (paragraph 42).
21. Ji modified by the teachings of Wang/Marena as seen in claim 1 above, as per claim 9, Marena teaches an apparatus comprising an interface bridging device of claim 1 developed as an ASIC (ASIC, paragraph 57) or FPGA capable of converting one or more C-PHY interfaces to one or more D-PHY interfaces.
22. Claims 10 – 16 are rejected under 35 U.S.C. 103 as being unpatentable over Marena in view of Wang further in view of Wiley.
23. As per claim 10, Marena teaches a programmable device (FPGA 130, figure 1) configured to provide data conversion between a data stream in a C physical layer ("C-PHY") protocol and a data stream in D physical layer ("D-PHY") protocol, comprising: an interface situated in the programmable device and configured to couple a first wire (214(0), figure 2) of data lane (DATA1_P, figure 2) to a first terminal of first serializer (LVCMOS12 274(1), figure 2) of programmable device for receiving a first data stream from a D-PHY transmitter of an external device and couple a second wire (DATA1_N, figure 2) of the data lane to a second terminal (LVCMOS 274(2), figure 2) of the first serializer of programmable device for receiving a second data stream from the D-PHY transmitter (272 handles first and second data streams received, figure 2, paragraph 40); and a C-PHY encoder coupled to the interface and configured to generate a first signal on first wire for a C-PHY output based on a first value on a P channel (driving LVCMOS to create single ended termination for HS mode, paragraph 36).
Marena does not appear to explicitly disclose a programmable logic device ("PLD") configured to provide data conversion between a data stream in a C physical layer ("C-PHY") protocol and a data stream in D physical layer ("D-PHY") protocol and configured to couple a first wire of data lane 0 and configured to generate a first signal on first wire of trio 0.
However, Wang discloses a device configured to couple a first wire of data lane 0 (D0P/D0N first wire of data lane 0, figure 6, paragraph 56).
Marena and Wang are analogous art because they are from the same field of endeavor of C-PHY/D-PHY handling.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Marena and Wang before him or her, to modify the processing of Marena to include the structure of Wang because it would allow enhanced protocol functionality.
One of ordinary skill would be motivated to make such modification in order to enhance connectivity for MIPI system management (paragraph 3). Therefore, it would have been obvious to combine Wang with Marena to obtain the invention as specified in the instant claims.
Marena/Wang does not appear to explicitly disclose a programmable logic device ("PLD") configured to provide data conversion between a data stream in a C physical layer ("C-PHY") protocol and a data stream in D physical layer ("D-PHY") protocol and configured to generate a first signal on first wire of trio 0.
However, Wiley discloses a programmable logic device ("PLD") (PLD, paragraph 38 and 130) configured to provide data conversion between a data stream in a C physical layer ("C-PHY") protocol and a data stream in D physical layer ("D-PHY") protocol (PLD 912/952 for handling data conversion between C-PHY/D-PHY, figure 9), a C-PHY encoder (paragraph 53, C-PHY encoder 306), and configured to generate a first signal on first wire of trio 0 (first wire of three wire trio 0, figure 5, 512a…c, trio paragraphs 49 and 70 to receive encoded signal, figure 3, paragraph 52).
24. Marena/Wang and Wiley are analogous art because they are from the same field of endeavor of C-PHY/D-PHY handling.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Marena/Wang and Wiley before him or her, to modify the FPGA high level capabilities of Marena/Wang to include the programmable nature of Wiley because FPGAs are advanced forms of PLDs.
One of ordinary skill would be motivated to make such modification in order to enhance MIPI functionality (paragraphs 4 and 5). Therefore, it would have been obvious to combine Wiley with Marena/Wang to obtain the invention as specified in the instant claims.
25. Marena modified by the teachings of Wang/Wiley as seen in claim 10 above, as per claim 11, Marena teaches a PLD, wherein the first serializer activates a first scalable low- voltage signal ("SLVS") to generate a first value on P channel and a second value on N channel in response to the first data and the second data (paragraphs 6 and 53, SLVS).
26. Marena modified by the teachings of Wang/Wiley as seen in claim 10 above, as per claim 12, Wang teaches a PLD, further comprising a C-PHY interface capable of generating a first signal on first wire of trio 0 for a C-PHY output based on a first value on a P channel (figure 6, interface outputs T0A/B/C, figure 2, C-PHY trio, figure 3b DP output/P channel, paragraph 8).
27. Marena modified by the teachings of Wang/Wiley as seen in claim 10 above, as per claim 13, Wiley teaches a PLD, further comprising a first-in first-out ("FIFO") buffer configured to buffer the first data stream (FIFO 510, figure 5).
28. Marena modified by the teachings of Wang/Wiley as seen in claim 10 above, as per claim 14, Wiley teaches a PLD, further comprising a C-PHY circuit configured to fetch (506, figure 5) the first data stream from the FIFO buffer and convert (508, figure 5) the first data stream to the second data stream based on C-PHY protocol (FIFO 510, figure 5, additionally seen in figure 13, fetch 1334).
29. Marena modified by the teachings of Wang/Wiley as seen in claim 10 above, as per claim 15, Marena teaches a PLD, further comprising a C-PHY circuit configured to output the second data stream to a display processor via a C-PHY bus (via 599, figure 5, paragraphs 43 and 44).
30. Marena modified by the teachings of Wang/Wiley as seen in claim 10 above, as per claim 16, Wang teaches a PLD, further comprising a C-PHY circuit configured to generate the second data stream represented by three (3) sets of three wires (trio) to the display process via the C-PHY bus (three sets 750/751/752, figure 7).
Conclusion
31. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Ahmed/Croxford/Itoigawa/Shen/Takashi/Thirumalai/Wietfeldt, have C-PHY/D-PHY teachings in an FPGA system.
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AH
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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