DETAILED ACTION
Claims 1-12 are pending. Claims 13-20 are withdrawn from consideration based on the election without traverse of claims 1-12 on 5/22/2026.
Priority: Nov. 30, 2021(Parent); Jan. 21, 2021(Provisional)
Assignee: Texas Instruments
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim(s) 1-12 rejected on the ground of nonstatutory double patenting as being unpatentable over claim(s) 1, 5, 7, 14, 17-20 of U.S. Patent No. 11,853,199. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant claims are not patentably distinct from the cited patent claims as set forth below.
19/038,856(Instant)
1. A system comprising: multiple peripherals including a first peripheral and a second peripheral, the first peripheral associated with a first channel and a second channel; a credential allocator circuit configurable to generate a unique identification value for each of the first channel, the second channel and the second peripheral; mapping circuitry configurable to: map a first function of the system to the first channel, map a second function of the system to the second channel, and map a third function of the system to the second peripheral; map each identification value generated by the credential allocator circuit to a corresponding function value and a corresponding traffic class value; and map each identification value generated by the credential allocator circuit to a corresponding address space value; and a firewall configurable to recognize the identification values generated by the credential allocator circuit.
11,853,199(Parent)
5, 17, 18, 19
Analysis
The principal difference is that instant claim 1 recites a system containing a credential allocator and mapping circuitry, whereas parent claim 19 states the corresponding mapping and programming operations as a method. Claims 17 and 18 provide the specific two-channel and second-peripheral arrangements, and claim 5 provides identification-value validation by a firewall. Implementing the patented operations in circuits configured to perform them is a predictable apparatus implementation, not a patentably distinct technological result.
19/038,856(Instant)
2. The system of claim 1, further comprising multiple credential generators including a first credential generator for the first channel, a second credential generator for the second channel, and a third credential generator for the second peripheral.
11,853,199(Parent)
17 and 18
Analysis
Parent claim 17 expressly recites first and second credential generators in first and second channels of one peripheral. Parent claim 18 expressly recites a credential generator in a second peripheral. Combining the two claimed arrangements simply provides a respective credential generator for each already-claimed transaction source.
19/038,856(Instant)
3. The system of claim 1, wherein at least one of the first and second functions is a virtual function, and the third function is a physical function.
11,853,199(Parent)
19
Analysis
Parent claim 19 expressly maps channels in one or more peripherals to one or more physical functions and one or more virtual functions. Selecting one first-peripheral channel for a virtual function and the second peripheral for a physical function is a particular allocation among the function types expressly claimed. The instant claim does not recite a critical allocation rule or an unexpected result arising from that selection.
19/038,856(Instant)
4. The system of claim 1, wherein the mapping circuitry includes an endpoint manager circuit, a transaction mapper circuit, and an address configurator circuit.
11,853,199(Parent)
1, 19
Analysis
Parent claim 1 expressly claims the transaction mapper and memory-management/address-space mapping circuits and their respective ID-to-BDF and ID-to-address-space tables. Parent claim 19 claims programming the channel/function mappings, transaction mapper, and memory-management mappings. Assigning the configuration operations to an endpoint manager and denominating the address-space configuration portion as an address configurator is a predictable functional partition of the same claimed circuitry and operations.
19/038,856(Instant)
5. The system of claim 4, wherein: the endpoint manager circuit is configurable to map the first function of the system to the first channel, map the second function of the system to the second channel, and map the third function of the system to the second peripheral; the transaction mapper circuit is configurable to map each identification value generated by the credential allocator circuit to the corresponding function value and the corresponding traffic class value; and the address configurator circuit is configurable to map each identification value generated by the credential allocator circuit to the corresponding address space value.
11,853,199(Parent)
1, 19
Analysis
Parent claim 19 expressly claims all three mapping operations. Parent claim 1 assigns the BDF mapping to the transaction mapper and the address-space mapping to the memory management circuit. The instant claim allocates the same operations to correspondingly named circuit blocks without changing the input values, output values, or resulting transaction path.
19/038,856(Instant)
6. The system of claim 5, wherein the endpoint manager circuit is configurable to program the transaction mapper circuit to map each identification value generated by the credential allocator circuit to the corresponding function value and the corresponding traffic class value.
11,853,199(Parent)
19
Analysis
Parent claim 19 expressly claims programming the transaction mapper to map each virtual identification value to a respective BDF/function value and traffic-class value. The only material difference is the identification of the endpoint manager as the programming control circuit.
19/038,856(Instant)
7. The system of claim 6, wherein the endpoint manager circuit is configurable to store the function values and traffic class values in a register of the transaction mapper circuit.
11,853,199(Parent)
7, 19
Analysis
Parent claim 7 expressly claims programmable transaction-mapper registers storing respective BDF and traffic-class values. Parent claim 19 expressly claims programming the transaction mapper with those mappings. The instant claim merely identifies the endpoint manager as the circuit writing the patented values into the patented registers.
19/038,856(Instant)
8. The system of claim 5, further comprising a memory management unit, wherein the endpoint manager circuit is configurable to program associations between identification values and address space values to a table in the memory management unit.
11,853,199(Parent)
1, 19
Analysis
Parent claim 1 expressly claims a memory management circuit containing a table that associates virtual identification values with address-space-select values. Parent claim 19 expressly claims programming the memory management circuit to map each value to a respective address-space-select value. The instant claim adds only that the endpoint manager performs the table programming.
19/038,856(Instant)
9. The system of claim 5, wherein the endpoint manager circuit is further configurable to establish communication with a host device.
11,853,199(Parent)
20
Analysis
Parent claim 20 expressly claims establishing a link with a host device after programming the credential generators, transaction mapper, and memory management circuit. The instant claim identifies the endpoint manager as the circuit performing that link-establishment operation.
19/038,856(Instant)
10. The system of claim 1, wherein the system includes a Peripheral Component Interconnect Express (PCIe) endpoint.
11,853,199(Parent)
14, 19
Analysis
Parent claim 14 claims an endpoint that includes the transaction mapper, and parent claim 19 claims physical and virtual functions, BDF values, and traffic-class values. Construed in the common specification, those terms describe the disclosed PCIe endpoint architecture. Thus, the instant “PCIe endpoint” limitation identifies the protocol context of the same endpoint/function/BDF architecture already claimed.
19/038,856(Instant)
11. The system of claim 1, further comprising multiple endpoint instances, each identified by a respective address space value.
11,853,199(Parent)
14
Analysis
Parent claim 14 claims using an address-space-select value to determine that a request is associated with an endpoint and routing the request through an interconnect to that endpoint. Repeating the same claimed endpoint block for additional address-space-select values predictably permits the interconnect to route to additional destinations without changing the selection mechanism or endpoint operation.
19/038,856(Instant)
12. The system of claim 8, further comprising an interconnect coupled between the memory management unit and the transaction mapper circuit.
11,853,199(Parent)
14
Analysis
Parent claim 14 expressly sends a request from the memory management circuit to an interconnect and then from the interconnect to an endpoint comprising the transaction mapper. That claimed transaction path necessarily places the interconnect between and coupled to the two circuits.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites a firewall “configurable to recognize” identification values, but neither the claim nor the specification establishes an objective boundary for what constitutes “recognizing” an identification value. Claims 2–12 depend, directly or indirectly, from claim 1 and therefore inherit the uncertainty.
The specification describes several distinct operations that could plausibly be characterized as recognition: (i) being programmed with acceptable virtual identification values ([0073]); (ii) comparing a virtual identification value with a mask or acceptable range ([0050], [0064], [0067]); (iii) determining whether a request has appropriate credentials and blocking the request if it does not ([0040]); and (iv) allowing or denying access based on the result ([0049]–[0053], [0064]). Those operations are not coextensive. A firewall may detect or decode an identification value without validating it; may validate it without storing an enumerated list; or may compare it to a range without itself controlling whether the request proceeds.
Because claim 1 does not state whether “recognize” requires detection, decoding, lookup, comparison against programmed acceptable values, satisfaction of a threshold range, validation, authorization, or a resulting allow/block action, persons of ordinary skill cannot determine with reasonable certainty which firewall implementations satisfy the limitation. The phrase therefore fails to particularly point out and distinctly claim the subject matter regarded as the invention.
The rejection may be overcome by replacing “recognize” with an objectively testable operation consistent with the disclosed embodiment, for example: “a firewall configurable to determine whether an identification value of an input-output request is included in a programmed set or range of acceptable identification values,” with any desired allow, block, discard, or error response recited separately.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Borikar et al.(20200278935), in view of Guo et al.(20200371953) and further in view of Hughes et al.(20210352109).
As per claim 1, Borikar discloses:
A system(Borikar, [0061 -- the computing system ]) comprising: multiple peripherals including a first peripheral and a second peripheral(Borikar, [0060 -- PCIe endpoints 312A, 312B, 312C, and 312D (e.g., the PCIe endpoints 116, 210, and 260)]), the first peripheral associated with a first channel and a second channel(Borikar, [0062 -- The VFs 322 can be light-weight PCIe functions or devices that are directly accessible by the system images 314. Each PF 320 and VF 322 can be assigned a unique Routing ID or PASID for routing Transaction Layer Packets (TLPs)]);
a credential allocator circuit configurable to generate a unique identification value for each of the first channel, the second channel and the second peripheral(Borikar, [0062 -- The VFs 322 can be light-weight PCIe functions or devices that are directly accessible by the system images 314. Each PF 320 and VF 322 can be assigned a unique Routing ID or PASID for routing Transaction Layer Packets (TLPs)]); mapping circuitry configurable to:
map a first function of the system to the first channel, map a second function of the system to the second channel, and map a third function of the system to the second peripheral(Borikar, [0059 -- FIG. 3A illustrates a block diagram of an example of a reference architecture of a computing system 300 for implementing I/O Virtualization (IOV) and ATS, as set forth in the PCI Express® Base specification. IOV can provide a mechanism by which a single Physical Function (PF) or physical device can appear to be multiple separate physical functions], [0062 -- The VFs 322 can be light-weight PCIe functions or devices that are directly accessible by the system images 314. Each PF 320 and VF 322 can be assigned a unique Routing ID or PASID for routing Transaction Layer Packets (TLPs)]);
Borikar does not explicitly disclose the following, however Guo discloses:
map each identification value generated by the credential allocator circuit to a corresponding function value and a corresponding traffic class value(Guo, [0028 -- When a PCIe interface is used, a requestor ID can include bus, device and function (BDF) information. IOMMU 302 can perform translation record lookup inside an STT 312 using a virtual address as a key], [0032 -- Field IOTLB_QoS can be used to inform IOMMU the priority of a PASID. The IOMMU can determine how many IOTLB translation entries or Translation Records in STT 510 can be assigned to a specific PASID based on the priority field]);
and map each identification value generated by the credential allocator circuit to a corresponding address space value(Guo, [0028 -- if an address translation is not present in IOTLB 304 and a IOTLB miss occurs, IOMMU 302 can locate the PASID entry by requestor ID and PASID and retrieves an STT pointer to a relevant STT 312 from the PASID entry. When a PCIe interface is used, a requestor ID can include bus, device and function (BDF) information]);
Therefore it would have been obvious to a POSITA at the time of filing to incorporate the features of Guo into the system of Borikar for the benefit of a shared virtual memory (SVM) function that allows input-output devices to utilize a guest virtual address (GVA), and reduce complexity for user space applications by avoiding a need to convert a virtual address of a process to a physical address(Guo, 0014).
Borikar, Guo does not explicitly disclose the following, however Hughes discloses:
and a firewall configurable to recognize the identification values generated by the credential allocator circuit(Hughes, [0068 -- The policy header 720 can include, but is not limited to, a network segment, information regarding the application generating or sending the packet, a firewall zone 724, and other information 726. The segment id 722 identifies which segment or VRF within a SD-WAN the WAN packet should be sent or is from. ]).
Therefore it would have been obvious to a POSITA at the time of filing to incorporate the features of Hughes into the system of Borikar, Guo for the benefit of generating and processing the wide area networking packets with network segment, application, and security information in an effective manner. The method allows the packet payloads to be encrypted and network address translation to be performed on the packet's payload in an efficient manner. (Hughes, 0006).
As per claim 3, the rejection of claim 1 is incorporated, in addition, Borikar discloses:
The system, wherein at least one of the first and second functions is a virtual function, and the third function is a physical function(Borikar, [0059 -- FIG. 3A illustrates a block diagram of an example of a reference architecture of a computing system 300 for implementing I/O Virtualization (IOV) and ATS, as set forth in the PCI Express® Base specification. IOV can provide a mechanism by which a single Physical Function (PF) or physical device can appear to be multiple separate physical functions (e.g., Virtual Functions (VFs)) or devices (e.g., Virtual Devices (VDEVs)) each with their own configuration, including bus number and Base Address Registers (BARs), or more granular, provisioned, device resources (e.g., Assignable Device Interfaces (ADIs) associated PASIDs)]).
As per claim 4, the rejection of claim 1 is incorporated, in addition, Borikar discloses:
The system, wherein the mapping circuitry includes an endpoint manager circuit, a transaction mapper circuit, and an address configurator circuit(Borikar, [0037 -- The root complex can be responsible for system configuration, enumeration of PCIe resources, and management of interrupts and errors for the PCIe tree. A root complex and its endpoints can share a single address space and communicate through memory reads and writes, and interrupts. PCIe can connect two components with a point-to-point link. Links can comprise N lanes (e.g., a x16 PCIe link can comprise N lanes), and each lane can include two pairs of wires: one pair for transmission and one pair for reception. Each lane can connect to a PCIe endpoint, PCIe switch, or a PCIe to PCI bridge.]).
As per claim 5, the rejection of claim 4 is incorporated, in addition, Borikar discloses:
The system, wherein: the endpoint manager circuit is configurable to map the first function of the system to the first channel, map the second function of the system to the second channel, and map the third function of the system to the second peripheral(Borikar, [0059 -- FIG. 3A illustrates a block diagram of an example of a reference architecture of a computing system 300 for implementing I/O Virtualization (IOV) and ATS, as set forth in the PCI Express® Base specification. IOV can provide a mechanism by which a single Physical Function (PF) or physical device can appear to be multiple separate physical functions], [0062 -- The VFs 322 can be light-weight PCIe functions or devices that are directly accessible by the system images 314. Each PF 320 and VF 322 can be assigned a unique Routing ID or PASID for routing Transaction Layer Packets (TLPs)]);
Borikar does not explicitly disclose the following however Guo discloses:
the transaction mapper circuit is configurable to map each identification value generated by the credential allocator circuit to the corresponding function value and the corresponding traffic class value(Guo, [0028 -- When a PCIe interface is used, a requestor ID can include bus, device and function (BDF) information. IOMMU 302 can perform translation record lookup inside an STT 312 using a virtual address as a key], [0032 -- Field IOTLB_QoS can be used to inform IOMMU the priority of a PASID. The IOMMU can determine how many IOTLB translation entries or Translation Records in STT 510 can be assigned to a specific PASID based on the priority field]);
and the address configurator circuit is configurable to map each identification value generated by the credential allocator circuit to the corresponding address space value(Guo, [0028 -- if an address translation is not present in IOTLB 304 and a IOTLB miss occurs, IOMMU 302 can locate the PASID entry by requestor ID and PASID and retrieves an STT pointer to a relevant STT 312 from the PASID entry. When a PCIe interface is used, a requestor ID can include bus, device and function (BDF) information]).
Therefore it would have been obvious to a POSITA at the time of filing to incorporate the features of Guo into the system of Borikar for the benefit of a shared virtual memory (SVM) function that allows input-output devices to utilize a guest virtual address (GVA), and reduce complexity for user space applications by avoiding a need to convert a virtual address of a process to a physical address(Guo, 0014).
As per claim 6, the rejection of claim 5 is incorporated, in addition, Borikar does not explicitly disclose the following, however Guo discloses:
The system, wherein the endpoint manager circuit is configurable to program the transaction mapper circuit to map each identification value generated by the credential allocator circuit to the corresponding function value and the corresponding traffic class value(Guo, [0032 -- Field IOTLB_QoS can be used to inform IOMMU the priority of a PASID. The IOMMU can determine how many IOTLB translation entries or Translation Records in STT 510 can be assigned to a specific PASID based on the priority field]).
Therefore it would have been obvious to a POSITA at the time of filing to incorporate the features of Guo into the system of Borikar for the benefit of a shared virtual memory (SVM) function that allows input-output devices to utilize a guest virtual address (GVA), and reduce complexity for user space applications by avoiding a need to convert a virtual address of a process to a physical address(Guo, 0014).
As per claim 7, the rejection of claim 6 is incorporated, in addition, Borikar does not disclose the following, however Guo discloses:
The system, wherein the endpoint manager circuit is configurable to store the function values and traffic class values in a register of the transaction mapper circuit(Guo, [0030 -- The IOMMU can use the BDF and PASID to perform a context lookup in a root table and lower context table to identify a PASID table for the requester.]).
Therefore it would have been obvious to a POSITA at the time of filing to incorporate the features of Guo into the system of Borikar for the benefit of a shared virtual memory (SVM) function that allows input-output devices to utilize a guest virtual address (GVA), and reduce complexity for user space applications by avoiding a need to convert a virtual address of a process to a physical address(Guo, 0014).
As per claim 8, the rejection of claim 5 is incorporated, in addition, Borikar does not explicitly disclose the following, however Guo discloses:
The system of claim 5, further comprising a memory management unit, wherein the endpoint manager circuit is configurable to program associations between identification values and address space values to a table in the memory management unit(Guo, [0028 -- In connection with a DMA request from a device (e.g., one of devices 306-0 to 306-B) or a memory access request (e.g., read or write), if an address translation is not present in IOTLB 304 and a IOTLB miss occurs, IOMMU 302 can locate the PASID entry by requestor ID and PASID and retrieves an STT pointer to a relevant STT 312 from the PASID entry. When a PCIe interface is used, a requestor ID can include bus, device and function (BDF) information]).
Therefore it would have been obvious to a POSITA at the time of filing to incorporate the features of Guo into the system of Borikar for the benefit of a shared virtual memory (SVM) function that allows input-output devices to utilize a guest virtual address (GVA), and reduce complexity for user space applications by avoiding a need to convert a virtual address of a process to a physical address(Guo, 0014).
As per claim 9, the rejection of claim 5 is incorporated, in addition, Borikar discloses:
The system, wherein the endpoint manager circuit is further configurable to establish communication with a host device(Borikar, [0060 -- The root complex 306 can represent the root of an I/O hierarchy that connects the CPU 302 and main memory 304 to I/O resources (e.g., the PCIe endpoints 312).]).
As per claim 10, the rejection of claim 1 is incorporated, in addition, Borikar discloses:
The system of claim 1, wherein the system includes a Peripheral Component Interconnect Express (PCIe) endpoint(Borikar, [0037 -- Various embodiments may also support PCIe. PCIe can specify point-to-point connectivity resulting in a tree structure topology with a single root complex. The root complex can be responsible for system configuration, enumeration of PCIe resources, and management of interrupts and errors for the PCIe tree.]).
As per claim 11, the rejection of claim 1 is incorporated, in addition, Borikar discloses:
The system, further comprising multiple endpoint instances, each identified by a respective address space value(Borikar, [0019 -- the virtualization intermediary 316, or the SR-PCIM 318. The VFs 322 can be light-weight PCIe functions or devices that are directly accessible by the system images 314. Each PF 320 and VF 322 can be assigned a unique Routing ID or PASID for routing Transaction Layer Packets (TLPs)]).
As per claim 12, the rejection of claim 8 is incorporated, in addition, Borikar discloses:
The system, further comprising an interconnect coupled between the memory management unit and the transaction mapper circuit(Borikar, [0066 -- The computing system 300 can include various elements for supporting ATS, such as a translation agent 324, an address translation and protection table (ATPT) 326, and ATCs 328A, 328B, 328C, and 328D (collectively, 328) in the PCIe endpoints 312A, 312B, 312C, and 312D, respectively. The translation agent 324 can include hardware, firmware, and/or software for translating an address within a PCIe transaction into the associated physical address. In some embodiments, the translation agent 324 can include an ATC to reduce latency for translation table access]).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Borikar et al.(20200278935), in view of Guo et al.(20200371953) in view of Hughes et al.(20210352109), and further in view of Raghav et al.(20190042508).
As per claim 2, the rejection of claim 1 is incorporated, in addition, Borikar, Guo, Hughes does not disclose the following, however Raghav discloses:
The system, further comprising multiple credential generators including a first credential generator for the first channel, a second credential generator for the second channel, and a third credential generator for the second peripheral(Raghav, [0067 -- At 702, a host device (e.g., through host software) accesses capability registers of a peripheral device to obtain device capability data stored in the hardware registers. Referring to FIG. 12, for example, the host device 1210 may access device capability data stored in the registers 1228 of the peripheral device 1220. The peripheral device is a multi-link capable device that includes multiple ports for communication with the host device, and each capability register corresponds to a particular port of multi-link device]).
Therefore it would have been obvious to a POSITA at the time of filing to incorporate the features of Raghav into the system of Borikar, Guo, Hughes for the benefit of reducing cross-socket traffic over a coherent processor interconnect by connecting an endpoint to each processor socket through respective Peripheral component interconnect express (PCIe) links(Raghav, 0052).
Examiner Notes
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Armstrong et al.(20110252173) involves storing translation of requester identifier ranges to north chip identifiers of north chip into south chip. A command comprising command requester identifier is received from electronic device (160) at south chip. The requester identifier range that encompasses the command requester identifier is determined. The north chip identifier that is assigned virtual functions identified by the command requester identifier is found. The command identified by the north chip identifier is sent from the south chip to the north chip(Armstrong, Abstract).
Raval et al.(20220206942) involves storing context data of an input/output memory management unit (IOMMU) by another IOMMU, where the IOMMUs are associated with a different memory access requestor that is associated with different address space of multiple address spaces. A direct memory access (DMA) request is received to a memory address space belonging to one of the former IOMUs by the latter IOMU. Direct memory access is provided to the memory address spaces belonging to the former MOMU in response to the DMA request. A set of memory-mapped input-output (MMIO) registers is synchronized with each other(Raval, abstract).
Harriman(20210255973) enables providing data transmission rate improvements that have been key to expanding a number of components that are implemented within computing systems, thus increasing overall performance of the computing systems(Harriman, abstract).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARVIND TALUKDAR whose telephone number is (303)297-4475. The examiner can normally be reached M-F, 10 am-6pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at 571-272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Arvind Talukdar
Primary Examiner
Art Unit 2132
/ARVIND TALUKDAR/Primary Examiner, Art Unit 2132
Prosecution Insights