DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 11-17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nakamura (U.S. 2014/0036210).
Regarding claim 11, Nakamura discloses a display device (1, Fig. 1; page 2, para [0023]) comprising:
a first substrate (AR, Fig. 4; page 2, para [0024]) including pixels (PX, Fig. 1; page 2, para [0024]), a first wiring (S, Fig. 2; page 2, para [0027]) extending in a first direction (along Y direction, Fig. 2), a second wiring (portions of C along Y and X directions, Fig. 2; page 2, para [0027]; page 3, para [0039]) extending in the first direction (along Y direction, Fig. 2) and arranged with the first wiring (S, Fig. 2) in a second direction (S and C arranged along X direction, Fig. 2) intersecting the first direction (along Y direction, Fig. 2), and a peripheral circuit (combination of: 2, SD, VS, and VCS, Fig. 2; page 2, para [0028, 0031-0032]) including a transistor (transistor comprising SC/G of CS that is electrically connected to C , Figs. 2 and 7; page 2, para [0035]; page 3, para [0039, 0044]), the first and second wirings (S and C, Fig. 2) connected to the peripheral circuit (S and C connected to portion SD and VCS of the peripheral circuit , Fig. 2); and
a second substrate (CT, Fig. 4; page 2, para [0024]) including a black matrix (BM, Fig. 8; page 4, para [0056]),
wherein
the pixels (PX, Fig. 1) are disposed in a display area (ACT, Fig. 1; page 2, para [0024]),
the peripheral circuit (combination of: 2, SD, VS, and VCS, Fig. 2), a part of the first wiring (S, Fig. 2), and a part of the second wiring (C, Fig. 2) are disposed in a peripheral area (area outside of ACT, Figs. 1-2) outside of the display area (ACT, Figs. 1-2),
the black matrix (BM, Fig. 8) has a first portion (left half of BM2, Fig. 8) extending in the first direction (along y direction, Fig. 8) and overlapping the first wiring (left half of BM2 overlapping first wiring S, Figs. 3, 5, and 8; page 4, para [0060]), a second portion (right half of BM2, Fig. 8) extending in the first direction (along y direction, Fig. 8) and overlapping the second wiring (right half portions of BM2 overlapping the second wiring C, Figs. 3 and 7-8; page 4, para [0060]), and an opening (AP, Fig. 8; page 4, para [0058]) between the first portion (left half of BM2, Fig. 8) and the second portions (right half of BM2, Fig. 8),
an edge of the opening includes the first and second portions (edge of AP includes left half of BM2 and right half of BM2, Fig. 8; page 4, para [0058]), and
the transistor (transistor comprising SC/G of CS, Fig. 7; page 3, para [0044]) overlaps a third portion (bottom half portions of BM1, Fig. 8) of the black matrix (BM, Fig. 8), the third portion (bottom half portions of BM1, Fig. 8) being different form the first and second portions (left half of BM2 and right half of BM2, Fig. 8).
Regarding claim 12, Nakamura discloses a display device with all the limitations above and further discloses wherein:
a semiconductor layer (SC, Fig. 7; page 3, para [0044]) of the transistor (transistor comprising SC/G of CS, Fig. 7; page 3, para [0044]) overlaps the third portion (bottom half portions of BM1 of Fig. 8 or right half portions of BM1 of Fig. 7; Figs. 3 and 7-8).
Regarding claim 13, Nakamura discloses a display device with all the limitations above and further discloses wherein:
a semiconductor layer (SC, Fig. 7; page 3, para [0044]) of the transistor (transistor comprising SC/G of CS, Fig. 7; page 3, para [0044]) is disposed inside the third portion (SC is disposed inside the right half portions of BM1 of Fig. 7 or bottom half portions of BM1 of Fig. 8; Figs. 3 and 7-8).
Regarding claim 14, Nakamura discloses a display device with all the limitations above and further discloses:
a third wiring (such as I, Fig. 7; page 3, para [0050]) extending in the second direction (thickness portion on I extends along X direction, Fig. 7),
wherein the third portion (right half portions of BM1, Fig. 7) overlaps the third wiring (I, Fig. 7).
Regarding claim 15, Nakamura discloses a display device with all the limitations above and further discloses wherein:
the edge (edges of AP, Fig. 8) includes the third portion (bottom half portions of BM1, Fig. 8).
Regarding claim 16, Nakamura discloses a display device with all the limitations above and further discloses wherein:
a fourth wiring (PE, Fig. 5; page 2, para [0035]) extending in the second direction (PE extending in along X direction, Fig. 5) and arranged with the third wiring (PE is arranged to be connected to I, Fig. 7); and
a fourth portion of the black matrix (upper half portions of BM1, Fig. 8), the fourth portion being different from the first to third portions (fourth portion consisting of upper half portions of BM1 being different from the first portion consisting of left half of BM2, second portion consisting of right half of BM2, and third portion consisting of bottom half portions of BM1, Fig. 7).
Regarding claim 17, Nakamura discloses a display device with all the limitations above and further discloses wherein:
the edge (edges of AP, Fig. 8) includes the fourth portion (upper half portions of BM1, Fig. 8).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL CHANG LEE whose telephone number is (571)270-7923. The examiner can normally be reached M-F 10am-6pm.
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/PAUL C LEE/Primary Examiner, Art Unit 2871
