DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/28/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-6, 9-15 and 18 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. Claim 1 recites storing a counter vale, generating a cache line tag and replacing one or more error correction code (ECC).
The limitation of storing a counter value, as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components. That is, other than reciting “a processing device” nothing in the claim element precludes the step from practically being performed in the mind. For example, but for the “by a processing device” language, “storing” in the context of this claim encompasses the user manually storing data. Similarly, the limitations of generating a cache line and replacing one or more stored error correction code (ECC), as drafted, are processes that, under its broadest reasonable interpretation, covers performance of the limitations in the mind but for the recitation of generic computer components. If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
This judicial exception is not integrated into a practical application. In particular, the claim only recites additional element – using a processing device, to perform the steps. The processing device is recited at a high-level of generality (i.e., as a generic processor performing a generic computer function), such that they amounts no more than mere instructions to apply the exception using a generic computer component. Accordingly, these additional elements does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea.
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional element amounts to no more than mere instructions to apply the exception using a generic computer component. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. The claim is not patent eligible.
Independent claim 10 includes limitations similar to the limitations of independent claim 1 and rejected under 3 USC 101 for being directed to abstract idea for similar reasons as discussed above with respect to independent claim 1.
Dependent claims 2-6, 9, 11-15 and 18 do not cure the deficiency of the independent claims and are rejected under 35 USC 101 for being directed to abstract idea.
Allowable Subject Matter
Claims 1-20 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 101, set forth in this Office action.
Examiner’s Statement of Reasons for Allowance
The following is an examiner’s statement of reasons for allowance: After a fully conducted search and consideration, the prior art either taken alone or in combination neither anticipates nor render obvious to the claimed subject matter of the instant application. The prior art Ramrakhyani et al. (US Pub No. 2019/0251275) discloses a counter integrity tree for memory security includes at least one split-counter node specifying at least two counters each defined as a combination of a major count value shared between the at least two counters and a respective minor count value specified separately for each of the at least two counters. This increases the number of child nodes which can be provided per parent node of the tree, and hence reduces the number of tree levels that have to be traversed in a tree covering a given size of memory region. The minor counter size can be varied dynamically by allocating nodes in a mirror counter integrity tree for accommodating larger minor counters which do not fit in the corresponding node of the main counter integrity tree. (Ramrakhyani, Abstract), Durham et al. (US Pub No. 2018/0091308) discloses managing encrypted memory comprises a processor to store a first MAC based on data stored in system memory in response to a write operation to the system memory. The processor can also detect a read operation corresponding to the data stored in the system memory, calculate a second MAC based on the data retrieved from the system memory, determine that the second MAC does not match the first MAC, and recalculate the second MAC with a correction operation, wherein the correction operation comprises an XOR operation based on the data retrieved from the system memory and a replacement value for a device of the system memory. Furthermore, the processor can decrypt the data stored in the system memory in response to detecting the recalculated second MAC matches the first MAC and transmit the decrypted data to cache thereby correcting memory errors. (Durham, Abstract), Gove (US Pub No. 2017/0075817) discloses a memory corruption prevention process includes detecting a memory instruction of a program, where the memory instruction specifies a virtual memory address of data. The memory corruption prevention process further includes accessing, in response to the memory instruction, a translation lookaside buffer (TLB) using at least a portion of the virtual memory address. The memory corruption prevention process further includes, in response to accessing the TLB, obtaining a physical memory address corresponding to the virtual memory address, where the physical memory address corresponds to the data. The memory corruption prevention process further includes, in response to accessing the TLB, obtaining an authentication value corresponding to the physical memory address. The memory corruption prevention process further includes determining, using the authentication value, whether the memory instruction is authorized to proceed. (Gove, Abstract), and Bolotov et al. (US Pub No. 2019/0042795) discloses compressed integrity check counters in memory are described herein. A set of counters may be maintained for data areas in memory. A respective counter in the set of counters is used to provide a variance to encryption operations on a corresponding data area. The respective counter is each time data is modified in the corresponding data area. The respective counter implemented by a generalized multi-dimensional counter (GMDC). In response to a trigger, a counter reset is performed on the set of counters. The counter reset may include refreshing the corresponding data area using a new key and resetting the respective counter to a default value in response to the refresh. (Bolotov, Abstract), however, the prior art taken alone or in combination fails to teach or suggest “storing, by a processing device and in a cache tree configuration, a counter value corresponding to a cache line of a memory component; generating a cache line tag value based on a one-way hash of the counter value, a plaintext or a ciphertext data block, and a memory address value; and replacing one or more stored error correction code (ECC) bits associated with the cache line with the generated cache line tag value” (as recited in claims 1 & 10). Claims are allowed in light of the above claim limitations when in combination with the remaining claim limitations.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAQUEAL D WADE whose telephone number is (571)270-0357. The examiner can normally be reached M-F 8:00-5:00.
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/SHAQUEAL D WADE-WRIGHT/Primary Examiner, Art Unit 2407
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