DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-3, 5-17, and 19-20 are presented for examination.
Response to Arguments
Applicants’ arguments filed 09/28/2026 with respect to the rejections of claims 1-11, 13-17, and 19 under 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of rejection is made over Bains in view of AKLIK et al (US 20210200621 A1), herein AKLIK (newly cited prior art).
The applicant contends that Bains “merely discloses a conventional, passive error management scheme in which addresses already identified by the host as offlined (bad) addresses are simply skipped during ECS scrubbing operations, or the scrubbing rate is adaptively adjusted based on real-time error information.” Applicant also argues that Bains does not teach the claimed active error-memory. The argument is persuasive with respect to the prior rejection. However, a new ground of rejection is set forth below based on the combined teachings of Bains and AKLIK.
Applicant further argues that the previously “BAINS' operation of writing corrected data back to the memory (write back) is nothing more than an ordinary data restoration operation for the scrubbed location; it neither identifies nor designates any particular memory as a failed (error) memory.” The argument is persuasive with respect to the prior rejection. The previous mapping is therefore not maintained, and the claimed subject matter is addressed under the new ground of rejection set forth below.
Applicant argues that “BAINS has no mechanism for verifying whether its exclusion target was correctly identified, let alone a feedback loop for re-searching for the true failed memory upon such a misdetection.” The argument is persuasive with respect to Bains alone. However, AKLIK teaches re-testing a suspect memory portion, removing the suspect designation upon a successful subsequent read, and returning to/repeating read operations when an error metric does not exceed a threshold (See Paragraphs 0022-0024, 0031, and 0038). Accordingly, this limitation is addressed in the new ground of rejection over Bains in view of AKLIK.
Applicants’ argument that the dependent claims are patentable based on the alleged patentability of their respective independent claims is not persuasive with respect to the new grounds of rejection, because the amended independent claims are unpatentable over the combinations set forth below. With regards to claims 2-3, 5-12, 14-17 and 20 the applicant did not make any arguments regarding the references; the examiner is therefore maintaining the reference. See below the new rejection of the stated claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 5-11, 13-17, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over BAINS et al (US 20240211344 A1), herein BAINS in view of AKLIK (US 20210200621 A1), herein AKLIK.
Regarding claim 1, BAINS discloses a memory system comprising:
a plurality of memories and a controller (Memory controller represents the host for system 200, and memory module represents a module that includes multiple memory devices 260; p. 0058-0059) configured to;
perform a data read operation of reading data having a unit size from each of the plurality of memories (system 100 can perform ECS operations, which include ECC operations to read, correct, and write back memory locations; p. 0044, 0212-0214, 0220),
perform, when an uncorrectable error occurs during the data read operation, a plurality of detect read operations, each detect read operation reading data having the unit size from each of remaining memories excluding at least one different memory selected in rotation among the plurality of memories (Scrubbing operations include a read to memory, detection and correction of errors, followed by a write to memory. The system can detect row hammer conditions through the monitoring of error information within the memory. In response to detection of a multibit error (MBE), the system can determine whether the MBE is part of a pattern of errors related to a specific address of the memory. When detected errors indicate a pattern of errors, the host can trigger a row hammer response related to the specific address. In one example, the number of MBEs will represent the uncorrectable errors encountered by memory device in performing internal ECC. The determination can be a determination that multiple SBEs or MBEs are found in specific areas and a scrub could prevent additional errors from occurring; p. 0035, 0061, 0130),
check and compare numbers of errors corrected in each of the plurality of detect read operations (in one example, the ECS operations include the performance of error counting in a system that performs scrubbing with transparency or insight into the number of errors. In one example, the ECS operations include operations related to detection of uncorrectable errors and reporting the uncorrectable errors such as indication to the host or poisoning the data; p. 0038, 0044, 0048, 0059),
set, as an error memory, the at least one different memory excluded in a detect read operation in which a smallest number of errors is corrected, among the plurality of detect read operations (the scrubbing operations are described below as ECS operations, referring to operations that check for errors, correct correctable errors that are found (correct detected errors), and write corrected data back to memory (“set as error memory”); p. 0038), perform a test read operation on the set error memory, and re-perform the plurality of detect read operations when a number of errors detected in the test read operation is smaller than a preset number.
Bains does not explicitly teach performing a test read operation on the set error memory and re-perform the plurality of detect read operations when a number of errors detected in the test read operation is smaller than a preset number.
However, AKLIK in an analogous art teaches performing a test read operation on the set error memory (If the page that experienced the uncorrectable read error is determined to be on the suspect page list, a scanning operation 316 may be triggered to perform a media scan of the failed page; AKLIK p. 0024) and re-perform the plurality of detect read operations (If the read fail metric does not exceed the error threshold, the process may iterate to the reading operation 510 until all identified memory samples have been read; AKLIK p. 0038) when a number of errors detected in the test read operation is smaller than a preset number (a die error parameter is monitored relative to a die performance threshold…If, on the other hand, the die error parameter does not exceed the die performance threshold, the operations return to the reading operation 402; AKLIK p. 0031)(the read fail metric may include a number of failing blocks per die and/or a number of failing pages per block per die. A comparing operation 522 may compare the tracked read fail metric to an error threshold; AKLIK p. 0038).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Bains with the teachings of AKLIK by configuring performing a test read operation on the set error memory and re-perform the plurality of detect read operations when a number of errors detected in the test read operation is smaller than a preset number.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ re-perform the plurality of detect read operations in the system of Bains because AKLIK teaches the read error mitigation module may be operative to detect read errors, the example approaches described herein may be designed to restrict false positive detection of failing portions of a memory (AKLIK p. 0022).
Regarding claim 2, BAINS in view of AKLIK, as combined, discloses all of the limitations of claim 1. BAINS also discloses wherein the controller is configured to set a value of a background test register to a first value when the error memory is set (In one example, the setting of block triggers threshold filter (TF) to increment. In one example, TF is set when the threshold filter count equals an error threshold count (ETC). The ETC represents a configurable threshold (“value”) set by the system or by the user to only count errors in response to a threshold number. The setting of TF can trigger error counter (EC) to increment. Error count represents a register or storage location to store the error count. In one example, memory controller can set a mode (e.g., via register or mode register) within memory to trigger the memory to generate addresses and control the execution of scrub operations.; p. 0051-0052, 0055, 0077).
Regarding claim 3, BAINS in view of AKLIK, as combined, discloses all of the limitations of claim 2. BAINS also discloses wherein the controller is configured to:
perform, during a period in which the value of the background test register is set to the first value, the data read operation on remaining memories excluding the error memory among the plurality of memories (system can perform ECS operations, which include ECC operations to read, correct, and write back memory locations for all selected or specified addresses. In one example, the ECS system can read the memory array, correct errors with internal ECC (error checking and correction) logic, and write back corrected data. Excluded address memory is separate from address control and separate from the ECS engine, but accessible by the ECS engine. During scrubbing, address control can check the address to be scrubbed against the list of excluded addresses in excluded address memory. If the address is not contained in the list of excluded addresses, then the ECS operation can continue without any modifications what is described previously; p. 0044, 0113, 0134-135); and
reset an error memory when the uncorrectable error occurs in the data read operation. (In one example, column, row, bank, bank group, or other counter to generate internal addresses in address control can be reset in response to a RESET condition for the memory subsystem or in response to a bit in a mode register (MR), as illustrated with the OR of the RESET signal and the MR bit with logic. In the case of detection of an uncorrectable error, in one example, ECS engine poisons the data and writes the data back to memory; p. 0043, 0135).
Regarding claim 5, BAINS in view of AKLIK, as combined, discloses all of the limitations of claim 2. BAINS also discloses wherein when a number of errors detected in the test read operation is equal to or greater than a preset number, the controller is configured to set the value of the background test register to a second value without performing the test read operation (In one example, the error detection signal from ECC logic 130 can set block 132 to be active, which when set provides an output of error count equal to one, or EC=1. In one example, the reset control signal can be controlled to prevent the counting of an error for an excluded address. In one example, the error detection signal from ECC logic can set block to be active, which when set provides an output of errors per row are greater than one, or EPR>1. It will be understood that block can require two error detection signals between resets to trigger the setting of EPR>1. Thus, the input for block is labeled as INCR/SET to indicate that in one example the row will not be considered for high error count unless there are at least 2 errors; p. 0048-0049).
Regarding claim 6, BAINS in view of AKLIK, as combined, discloses all of the limitations of claim 5. BAINS also discloses wherein the controller is configured to:
perform, during a period in which the value of the background test register is set to the second value, the data read operation on remaining memories excluding the error memory among the plurality of memories (system can perform ECS operations, which include ECC operations to read, correct, and write back memory locations for all selected or specified addresses. In one example, the ECS system can read the memory array, correct errors with internal ECC (error checking and correction) logic, and write back corrected data. Excluded address memory is separate from address control and separate from the ECS engine, but accessible by the ECS engine. During scrubbing, address control can check the address to be scrubbed against the list of excluded addresses in excluded address memory. If the address is not contained in the list of excluded addresses, then the ECS operation can continue without any modifications what is described previously; p. 0044, 0113, 0134-135); and
skip an operation of searching for an error memory when the uncorrectable error occurs in the data read operation (For example, one mode may indicate that error scrubbing should be skipped for excluded addresses. For manual ECS operation, the address generation logic can set a multiplexer to select an external address set by the memory controller for scrubbing, which may bypass (“skip”) error counting; p. 0104-0105).
Regarding claim 7, BAINS in view of AKLIK, as combined, discloses all of the limitations of claim 1. BAINS also discloses wherein when the uncorrectable error occurs in the data read operation for the plurality of memories, the controller is configured to:
perform a first detect read operation on remaining memories excluding a first memory among the plurality of memories (Thus, memory controller can determine whether a row hammer attack is happening on memory , can determine whether to provide hints and what hints to provide to ECS control, can determine what weights to apply to logic within ECS control , can adjust a rate of error scrubbing operations by ECS control of the memory, or other operations, or a combination of operations (first and second operation), based on operations performed by ECS control; p. 0080-0081, 0105); and
perform a second detect read operation on remaining memories excluding a second memory among the plurality of memories, and compares a number of errors corrected in the first detect read operation with a number of errors corrected in the second detect read operation when the uncorrectable error does not occur in the first detect read operation and the second detect read operation (In one example, address control generates internal address information, shown as one of the inputs to compare. Compare represents an address comparator, or a comparison mechanism to compare generated addresses with addresses identified by the host as offline. The other input to compare is excluded address memory. In one example, compares the address generated by address control to all entries in excluded address memory. It will be understood that up to N address can be stored in excluded address memory, but there can be as few as zero addresses excluded, or any integer between 1 and N. If any address in excluded address memory matches with the generated address, the output of compare is set to true, or set to 1. If the addresses do not match, compare will output a zero; p. 0106, 0116).
Regarding claim 8, BAINS in view of AKLIK, as combined, discloses all of the limitations of claim 7. BAINS also discloses wherein the number of errors corrected in the first detect read operation is different from the number of errors corrected in the second detect read operation (In one example, address control generates internal address information, shown as one of the inputs to compare. Compare represents an address comparator, or a comparison mechanism to compare generated addresses with addresses identified by the host as offline. The other input to compare is excluded address memory. In one example, compare compares the address generated by address control to all entries in excluded address memory. It will be understood that up to N address can be stored in excluded address memory, but there can be as few as zero addresses excluded, or any integer between 1 and N. If any address in excluded address memory matches with the generated address, the output of compare is set to true, or set to 1. If the addresses do not match, compare will output a zero; p. 0106, 0116).
Regarding claim 9, BAINS in view of AKLIK, as combined, discloses all of the limitations of claim 7. BAINS also discloses wherein when a number of errors corrected in the first detect read operation and a number of errors corrected in the second detect read operation are identical to each other and correspond to the smallest number of errors, the controller is configured to notify an external device that the uncorrectable error has occurred (In one example, address control generates internal address information, shown as one of the inputs to compare. Compare represents an address comparator, or a comparison mechanism to compare generated addresses with addresses identified by the host as offline. The other input to compare is excluded address memory. In one example, compare compares the address generated by address control to all entries in excluded address memory. It will be understood that up to N address can be stored in excluded address memory, but there can be as few as zero addresses excluded, or any integer between 1 and N. If any address in excluded address memory matches with the generated address, the output of compare is set to true, or set to 1. If the addresses do not match, compare will output a zero. In one example, excluded address memory is part of address control. In one example, excluded address memory is separate from address control but part of the ECS engine (external device); p. 0106, 0113 0116).
Regarding claim 10, BAINS in view of AKLIK, as combined, discloses all of the limitations of claim 1. BAINS also discloses wherein when the error memory is set, the controller is configured to perform the data read operation on the remaining memories excluding the error memory among the plurality of memories (system can perform ECS operations, which include ECC operations to read, correct, and write back memory locations for all selected or specified addresses. In one example, the ECS system can read the memory array, correct errors with internal ECC (error checking and correction) logic, and write back corrected data. Excluded address memory is separate from address control and separate from the ECS engine, but accessible by the ECS engine. During scrubbing, address control can check the address to be scrubbed against the list of excluded addresses in excluded address memory. If the address is not contained in the list of excluded addresses, then the ECS operation can continue without any modifications what is described previously; p. 0044, 0113, 0134-135).
Regarding claim 11, BAINS in view of AKLIK, as combined, discloses all of the limitations of claim 1. BAINS also discloses wherein when the error memory is set, the controller is configured to transmit an error memory setting notification signal to an external device (In one example, the host can provide an indication to the on-memory error scrubbing engine of rows of memory that have been offlined by the host. For an error scrubbing engine with ECS logic with transparency that counts and reports on errors detected, the indication of the offlined errors can enable the error scrubbing engine to skip the offlined rows in ECS operation counts (p. 0033). In one example, system includes a patrol scrub finished indication to mark the end of a scrub operation for a given hint/region. The indication can be programmable to support various usage models such as SMI (system management interrupts) for platform level handling, BMC (baseboard management controller) for indication to the motherboard service processor, or CMCI (corrected machine check interrupt) to notify of a corrected event, or SCI (serial communication interface) to provide direct messaging to the host OS (p. 0152).)
Regarding claim 13, BAINS discloses a memory system comprising: a plurality of memories; and a controller configured to (Memory controller represents the host for system 200, and memory module represents a module that includes multiple memory devices 260; p. 0058-0059)
perform a data read operation on remaining memories excluding a set error memory, among the plurality of memories (perform scrubbing on selected rows that are not sequential, or to exclude selected addresses from scrubbing or from error counting; p. 0103-0106. 0108), and
sequentially perform a plurality of detect read operations on memories other than a different one memory selected in rotation among the plurality of memories, compare numbers of errors corrected in each of the plurality of detect read operations, and set, as a new error memory, the different one memory excluded in a detect read operation in which a smallest number of errors is corrected, among the plurality of detect read operations, (system can perform ECS operations, which include ECC operations to read, correct, and write back memory locations for all selected or specified addresses. In one example, the ECS system can read the memory array, correct errors with internal ECC (error checking and correction) logic, and write back corrected data. Excluded address memory is separate from address control and separate from the ECS engine, but accessible by the ECS engine. During scrubbing, address control can check the address to be scrubbed against the list of excluded addresses in excluded address memory. If the address is not contained in the list of excluded addresses, then the ECS operation can continue without any modifications what is described previously; p. 0044, 0113, 0134-135).
Bains does not explicitly teach performing a test read operation on the set error memory;
when a number of errors detected in the test read operation is smaller than a preset number.
However, AKLIK in an analogous art teaches performing a test read operation on the set error memory (If the page that experienced the uncorrectable read error is determined to be on the suspect page list, a scanning operation 316 may be triggered to perform a media scan of the failed page; AKLIK p. 0024);
when a number of errors detected in the test read operation is smaller than a preset number (a die error parameter is monitored relative to a die performance threshold…If, on the other hand, the die error parameter does not exceed the die performance threshold, the operations return to the reading operation 402; AKLIK p. 0031)(the read fail metric may include a number of failing blocks per die and/or a number of failing pages per block per die. A comparing operation 522 may compare the tracked read fail metric to an error threshold; AKLIK p. 0038).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Bains with the teachings of AKLIK by configuring performing a test read operation on the set error memory.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ performing a test read operation on the set error memory in the system of Bains because AKLIK teaches the read error mitigation module may be operative to detect read errors, the example approaches described herein may be designed to restrict false positive detection of failing portions of a memory (AKLIK p. 0022).
Regarding claim 14, BAINS in view of AKLIK, as combined, discloses all of the limitations of claim 13. BAINS also discloses wherein the controller is configured to skip performing the detect read operations on the error memory (In one example, address generation logic receives as an input an ECS mode check, which represents the ECS mode configured for the ECS logic to execute. For example, one mode may indicate that error scrubbing should be skipped for excluded addresses; p. 0104).
Regarding claim 15, BAINS in view of AKLIK, as combined, discloses all of the limitations of claim 13. BAINS also discloses wherein the controller is configured to:
perform a first detect read operation on memories other than a first memory among the plurality of memories (Thus, memory controller can determine whether a row hammer attack is happening on memory , can determine whether to provide hints and what hints to provide to ECS control, can determine what weights to apply to logic within ECS control , can adjust a rate of error scrubbing operations by ECS control of the memory, or other operations, or a combination of operations (first and second operation), based on operations performed by ECS control; p. 0080-0081, 0105);
perform a second detect read operation on memories other than a second memory among the plurality of memories, and compares a number of errors corrected in the first detect read operation with a number of errors corrected in the second detect read operation when an uncorrectable error does not occur in the first detect read operation and the second detect read operation (In one example, address control generates internal address information, shown as one of the inputs to compare. Compare represents an address comparator, or a comparison mechanism to compare generated addresses with addresses identified by the host as offline. The other input to compare is excluded address memory. In one example, compare compares the address generated by address control to all entries in excluded address memory. It will be understood that up to N address can be stored in excluded address memory, but there can be as few as zero addresses excluded, or any integer between 1 and N. If any address in excluded address memory matches with the generated address, the output of compare is set to true, or set to 1. If the addresses do not match, compare will output a zero; p. 0106, 0116).
Regarding claim 16, BAINS in view of AKLIK, as combined, discloses all of the limitations of claim 15. BAINS also discloses wherein the number of errors corrected in the first detect read operation is different from the number of errors corrected in the second detect read operation (In one example, address control generates internal address information, shown as one of the inputs to compare. Compare represents an address comparator, or a comparison mechanism to compare generated addresses with addresses identified by the host as offline. The other input to compare is excluded address memory. In one example, compare compares the address generated by address control to all entries in excluded address memory. It will be understood that up to N address can be stored in excluded address memory, but there can be as few as zero addresses excluded, or any integer between 1 and N. If any address in excluded address memory matches with the generated address, the output of compare is set to true, or set to 1. If the addresses do not match, compare will output a zero; p. 0106, 0116).
Regarding claim 17, BAINS in view of AKLIK, as combined, discloses all of the limitations of claim 15. BAINS also discloses wherein when the number of errors corrected in the first detect read operation is smaller than the number of errors corrected in the second detect read operation, the controller is configured to perform the data read operation on the memories other than the new error memory (In one example, address control generates internal address information, shown as one of the inputs to compare. Compare represents an address comparator, or a comparison mechanism to compare generated addresses with addresses identified by the host as offline. The other input to compare is excluded address memory. In one example, compare compares the address generated by address control to all entries in excluded address memory. It will be understood that up to N address can be stored in excluded address memory, but there can be as few as zero addresses excluded, or any integer between 1 and N. If any address in excluded address memory matches with the generated address, the output of compare is set to true, or set to 1. If the addresses do not match, compare will output a zero. In one example, excluded address memory is part of address control. In one example, excluded address memory is separate from address control but part of the ECS engine (external device); p. 0106, 0113 0116).
Regarding claim 19, BAINS discloses a controller comprising:
a control circuit configured to perform a first read operation on a plurality of memories (ECS control 110 represents logic or control circuitry to generate control scrubbing operations within system; p. 0038, 0242, 0280, 0304, 0310); and
an error correction circuit configured to correct an error which occurs in the first read operation (Memory scrubbing is a background operation that fixes correctable errors and detects uncorrectable errors with the help of error checking and correction (ECC) mechanisms. Correction can detect and correct errors in data from multiple memory devices. Correction can be error correction logic or an error correction circuit within memory controller to perform operations on data received from memory devices related to error checking and correction; p. 0003, 0044, 0059), wherein the control circuit is configured to:
sequentially perform a plurality of second read operations on memories excluding at least one different memory selected in rotation among the plurality of memories when an uncorrectable error occurs in the first read operation (Scrubbing operations include a read to memory, detection and correction of errors, followed by a write to memory. (the adaptation to the realtime detected error information can result in the intelligent application of error scrubbing or other error mitigation (“excluding”) techniques, resulting in fewer uncorrectable errors in memory. In one example, the ECS operations include operations related to detection of uncorrectable errors and reporting the uncorrectable errors such as indication to the host or poisoning the data. System provides an example of applying memory address exclusion during internal memory scrubbing operations; p. 0004, 0031, 0038, 0108),
compare numbers of errors corrected in each of the plurality of second read operations (in one example, the ECS operations include the performance of error counting in a system that performs scrubbing with transparency or insight into the number of errors. In one example, the ECS operations include operations related to detection of uncorrectable errors and reporting the uncorrectable errors such as indication to the host or poisoning the data; p. 0038, 0044, 0048, 0059),
set, as an error memory, the at least one different memory which is excluded in a second read operation in which a smallest number of errors is corrected, among the plurality of second read operations (the scrubbing operations are described below as ECS operations, referring to operations that check for errors, correct correctable errors that are found (correct detected errors), and write corrected data back to memory (“set as error memory”); p. 0038),
BAINS does not explicitly teach performing a third read operation on the set error memory and re-perform the plurality of second read operations when a number of errors detected in the third read operation is smaller than a preset number.
However, AKLIK in an analogous art teaches performing a third read operation on the set error memory (If the page that experienced the uncorrectable read error is determined to be on the suspect page list, a scanning operation 316 may be triggered to perform a media scan of the failed page…If the media scan for the suspect page does not fail (e.g., the page is readable) during the scanning operation 316, the page may be removed from the suspect page list at the removing operation; AKLIK p. 0024), and re-perform the plurality of second read operations (If the read fail metric does not exceed the error threshold, the process may iterate to the reading operation 510 until all identified memory samples have been read; AKLIK p. 0038) when a number of errors detected in the third read operation is smaller than a preset number (a die error parameter is monitored relative to a die performance threshold…If, on the other hand, the die error parameter does not exceed the die performance threshold, the operations return to the reading operation 402; AKLIK p. 0031)(the read fail metric may include a number of failing blocks per die and/or a number of failing pages per block per die. A comparing operation 522 may compare the tracked read fail metric to an error threshold; AKLIK p. 0038).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Bains with the teachings of AKLIK by configuring performing a test read operation on the set error memory and re-perform the plurality of detect read operations when a number of errors detected in the test read operation is smaller than a preset number.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ re-perform the plurality of detect read operations in the system of Bains because AKLIK teaches the read error mitigation module may be operative to detect read errors, the example approaches described herein may be designed to restrict false positive detection of failing portions of a memory (AKLIK p. 0022).
Regarding claim 20, BAINS in view of AKLIK, as combined, discloses all of the limitations of claim 19. BAINS also discloses wherein the control circuit is configured to perform the first read operation on memories excluding the error memory among the plurality of memories (ECS control represents logic or control circuitry to generate control scrubbing operations within system; p. 0038, 0242, 0280, 0304, 0310).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over BAINS in view of AKLIK in further view of CHOI et al (U.S. Patent Application Publication No. 20190129793 A1), hereinafter referenced as CHOI.
Regarding claim 12, BAINS discloses all of the limitations of claim 1. BAINS also discloses wherein data read from the plurality of memories includes user data metadata and parity data (Memory can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of system; p. 0273).
Bains mentions a parity detect but does not explicitly teach wherein a size of the parity data is smaller than two times the unit size.
However, CHOI in the analogous art teaches wherein a size of the parity data is smaller unit size, but does not specifically teach 2 times smaller (a basic size unit of data and a parity that are input to the main memory or are output from the main memory may correspond to the size of 32 bytes or 64 bytes. Below, “current data” that are data that the processor currently writes or reads may mean data (e.g., 4 bytes), the size of which is smaller than 32 bytes being a reference size used in the main memory; p. 0030, 0032)
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the invention, to modify the system of BAINS with the teachings of Choi by choosing a size below the basic size of bits for detecting an error.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ the size of parity data which is smaller than 32 bytes being a reference size used in the main memory in the system of BAINS because CHOI teaches a main memory storing data and parity for detecting an error occurring in data upon writing the data to the memory or reading the data from the memory. (p. ABST, 0003).
Conclusion
Applicants’ amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicants are reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAYLUN ARMAN JACKSON whose telephone number is (571)270-0985. The examiner can normally be reached 7:30am - 5:00pm Monday through Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Albert Decady, can be reached at 571-272-3819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JAYLUN A JACKSON/Examiner, Art Unit 2112
/ESAW T ABRAHAM/Primary Examiner, Art Unit 2112
