DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 are presented for examination.
Abstract
The abstract of the disclosure is acceptable for examination purposes.
Drawings
The drawings received on 01/28/2025 are acceptable for examination purposes.
Information Disclosure Statement
The reference(s) listed in the disclosure statement (IDS) submitted on 01/28/2025 have been considered. The submission complies with the provisions of 37 CFR 1.97.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-11, 13-17, and 19 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by BAINS et al (U.S. Patent Application Publication No 20240211344A1), hereinafter reference as BAINS.
Regarding claim 1, BAINS discloses a memory system comprising:
a plurality of memories and a controller (Memory controller represents the host for system 200, and memory module represents a module that includes multiple memory devices 260; p. 0058-0059) configured to;
perform a data read operation of reading data having a unit size from each of the plurality of memories (system 100 can perform ECS operations, which include ECC operations to read, correct, and write back memory locations; p. 0044, 0212-0214, 0220),
perform, when an uncorrectable error occurs during the data read operation, detect read operations, each detect read operation reading data having the unit size from each of remaining memories excluding at least one memory selected in rotation among the plurality of memories (Scrubbing operations include a read to memory, detection and correction of errors, followed by a write to memory. The system can detect row hammer conditions through the monitoring of error information within the memory. In response to detection of a multibit error (MBE), the system can determine whether the MBE is part of a pattern of errors related to a specific address of the memory. When detected errors indicate a pattern of errors, the host can trigger a row hammer response related to the specific address. In one example, the number of MBEs will represent the uncorrectable errors encountered by memory device in performing internal ECC. The determination can be a determination that multiple SBEs or MBEs are found in specific areas and a scrub could prevent additional errors from occurring; p. 0035, 0061, 0130),
check numbers of errors corrected in each of the detect read operations (in one example, the ECS operations include the performance of error counting in a system that performs scrubbing with transparency or insight into the number of errors. In one example, the ECS operations include operations related to detection of uncorrectable errors and reporting the uncorrectable errors such as indication to the host or poisoning the data; p. 0038, 0044, 0048, 0059), and
set, as an error memory, at least one memory excluded in a detect read operation in which a smallest number of errors is corrected, among the detect read operations (the scrubbing operations are described below as ECS operations, referring to operations that check for errors, correct correctable errors that are found (correct detected errors), and write corrected data back to memory (“set as error memory”); p. 0038).
Regarding claim 2, BAINS discloses all of the limitations of claim 1. BAINS also discloses wherein the controller is configured to set a value of a background test register to a first value when the error memory is set, and perform a test read operation on the error memory (In one example, the setting of block triggers threshold filter (TF) to increment. In one example, TF is set when the threshold filter count equals an error threshold count (ETC). The ETC represents a configurable threshold (“value”) set by the system or by the user to only count errors in response to a threshold number. The setting of TF can trigger error counter (EC) to increment. Error count represents a register or storage location to store the error count. In one example, memory controller can set a mode (e.g., via register or mode register) within memory to trigger the memory to generate addresses and control the execution of scrub operations.; p. 0051-0052, 0055, 0077).
Regarding claim 3, BAINS discloses all of the limitations of claim 2. BAINS also discloses wherein the controller is configured to:
perform, during a period in which the value of the background test register is set to the first value, the data read operation on remaining memories excluding the error memory among the plurality of memories (system can perform ECS operations, which include ECC operations to read, correct, and write back memory locations for all selected or specified addresses. In one example, the ECS system can read the memory array, correct errors with internal ECC (error checking and correction) logic, and write back corrected data. Excluded address memory is separate from address control and separate from the ECS engine, but accessible by the ECS engine. During scrubbing, address control can check the address to be scrubbed against the list of excluded addresses in excluded address memory. If the address is not contained in the list of excluded addresses, then the ECS operation can continue without any modifications what is described previously; p. 0044, 0113, 0134-135); and
reset an error memory when the uncorrectable error occurs in the data read operation. (In one example, column, row, bank, bank group, or other counter to generate internal addresses in address control can be reset in response to a RESET condition for the memory subsystem or in response to a bit in a mode register (MR), as illustrated with the OR of the RESET signal and the MR bit with logic. In the case of detection of an uncorrectable error, in one example, ECS engine poisons the data and writes the data back to memory; p. 0043, 0135).
Regarding claim 4, BAINS discloses all of the limitations of claim 2. BAINS also discloses wherein the controller is configured to reset an error memory when a number of errors detected in the test read operation is smaller than a preset number (In one example, the ECS operations include the performance of error counting in a system that performs scrubbing with transparency or insight into the number of errors. In one example, the error detection signal from ECC logic can set block to be active, which when set provides an output of errors per row are greater than one, or EPR>1. It will be understood that block can require two error detection signals between resets to trigger the setting of EPR>1. Thus, the input for block is labeled as INCR/SET to indicate that in one example the row will not be considered for high error count unless there are at least 2 errors; p. 0038, 0049).
Regarding claim 5, BAINS discloses all of the limitations of claim 2. BAINS also discloses wherein when a number of errors detected in the test read operation is equal to or greater than a preset number are, the controller is configured to set the value of the background test register to a second value without performing the test read operation (In one example, the error detection signal from ECC logic 130 can set block 132 to be active, which when set provides an output of error count equal to one, or EC=1. In one example, the reset control signal can be controlled to prevent the counting of an error for an excluded address. In one example, the error detection signal from ECC logic can set block to be active, which when set provides an output of errors per row are greater than one, or EPR>1. It will be understood that block can require two error detection signals between resets to trigger the setting of EPR>1. Thus, the input for block is labeled as INCR/SET to indicate that in one example the row will not be considered for high error count unless there are at least 2 errors; p. 0048-0049).
Regarding claim 6, BAINS discloses all of the limitations of claim 5. BAINS also discloses wherein the controller is configured to:
perform, during a period in which the value of the background test register is set to the second value, the data read operation on remaining memories excluding the error memory among the plurality of memories (system can perform ECS operations, which include ECC operations to read, correct, and write back memory locations for all selected or specified addresses. In one example, the ECS system can read the memory array, correct errors with internal ECC (error checking and correction) logic, and write back corrected data. Excluded address memory is separate from address control and separate from the ECS engine, but accessible by the ECS engine. During scrubbing, address control can check the address to be scrubbed against the list of excluded addresses in excluded address memory. If the address is not contained in the list of excluded addresses, then the ECS operation can continue without any modifications what is described previously; p. 0044, 0113, 0134-135); and
skip an operation of searching for an error memory when the uncorrectable error occurs in the data read operation (For example, one mode may indicate that error scrubbing should be skipped for excluded addresses. For manual ECS operation, the address generation logic can set a multiplexer to select an external address set by the memory controller for scrubbing, which may bypass (“skip”) error counting; p. 0104-0105).
Regarding claim 7, BAINS discloses all of the limitations of claim 1. BAINS also discloses wherein when the uncorrectable error occurs in the data read operation for the plurality of memories, the controller is configured to:
perform a first detect read operation on remaining memories excluding a first memory among the plurality of memories (Thus, memory controller can determine whether a row hammer attack is happening on memory , can determine whether to provide hints and what hints to provide to ECS control, can determine what weights to apply to logic within ECS control , can adjust a rate of error scrubbing operations by ECS control of the memory, or other operations, or a combination of operations (first and second operation), based on operations performed by ECS control; p. 0080-0081, 0105); and
perform a second detect read operation on remaining memories excluding a second memory among the plurality of memories, and compares a number of errors corrected in the first detect read operation with a number of errors corrected in the second detect read operation when the uncorrectable error does not occur in the first detect read operation and the second detect read operation (In one example, address control generates internal address information, shown as one of the inputs to compare. Compare represents an address comparator, or a comparison mechanism to compare generated addresses with addresses identified by the host as offline. The other input to compare is excluded address memory. In one example, compares the address generated by address control to all entries in excluded address memory. It will be understood that up to N address can be stored in excluded address memory, but there can be as few as zero addresses excluded, or any integer between 1 and N. If any address in excluded address memory matches with the generated address, the output of compare is set to true, or set to 1. If the addresses do not match, compare will output a zero; p. 0106, 0116).
Regarding claim 8, BAINS discloses all of the limitations of claim 7. BAINS also discloses wherein the number of errors corrected in the first detect read operation is different from the number of errors corrected in the second detect read operation (In one example, address control generates internal address information, shown as one of the inputs to compare. Compare represents an address comparator, or a comparison mechanism to compare generated addresses with addresses identified by the host as offline. The other input to compare is excluded address memory. In one example, compare compares the address generated by address control to all entries in excluded address memory. It will be understood that up to N address can be stored in excluded address memory, but there can be as few as zero addresses excluded, or any integer between 1 and N. If any address in excluded address memory matches with the generated address, the output of compare is set to true, or set to 1. If the addresses do not match, compare will output a zero; p. 0106, 0116).
Regarding claim 9, BAINS discloses all of the limitations of claim 7. BAINS also discloses wherein when a number of errors corrected in the first detect read operation and a number errors corrected in the second detect read operation are identical to each other and corresponds to the smallest number of errors, the controller is configured to notify an external device of that the uncorrectable error has occurred (In one example, address control generates internal address information, shown as one of the inputs to compare. Compare represents an address comparator, or a comparison mechanism to compare generated addresses with addresses identified by the host as offline. The other input to compare is excluded address memory. In one example, compare compares the address generated by address control to all entries in excluded address memory. It will be understood that up to N address can be stored in excluded address memory, but there can be as few as zero addresses excluded, or any integer between 1 and N. If any address in excluded address memory matches with the generated address, the output of compare is set to true, or set to 1. If the addresses do not match, compare will output a zero. In one example, excluded address memory is part of address control. In one example, excluded address memory is separate from address control but part of the ECS engine (external device); p. 0106, 0113 0116).
Regarding claim 10, BAINS discloses all of the limitations of claim 1. BAINS also discloses wherein when the error memory is set, the controller is configured to perform the data read operation on the remaining memories excluding the error memory among the plurality of memories (system can perform ECS operations, which include ECC operations to read, correct, and write back memory locations for all selected or specified addresses. In one example, the ECS system can read the memory array, correct errors with internal ECC (error checking and correction) logic, and write back corrected data. Excluded address memory is separate from address control and separate from the ECS engine, but accessible by the ECS engine. During scrubbing, address control can check the address to be scrubbed against the list of excluded addresses in excluded address memory. If the address is not contained in the list of excluded addresses, then the ECS operation can continue without any modifications what is described previously; p. 0044, 0113, 0134-135).
Regarding claim 11, BAINS discloses all of the limitations of claim 1. BAINS also discloses wherein when the error memory is set, the controller is configured to transmit an error memory setting notification signal to an external device (In one example, the host can provide an indication to the on-memory error scrubbing engine of rows of memory that have been offlined by the host. For an error scrubbing engine with ECS logic with transparency that counts and reports on errors detected, the indication of the offlined errors can enable the error scrubbing engine to skip the offlined rows in ECS operation counts (p. 0033). In one example, system includes a patrol scrub finished indication to mark the end of a scrub operation for a given hint/region. The indication can be programmable to support various usage models such as SMI (system management interrupts) for platform level handling, BMC (baseboard management controller) for indication to the motherboard service processor, or CMCI (corrected machine check interrupt) to notify of a corrected event, or SCI (serial communication interface) to provide direct messaging to the host OS (p. 0152).)
Regarding claim 13, BAINS discloses a memory system comprising: a plurality of memories; and a controller configured to (Memory controller represents the host for system 200, and memory module represents a module that includes multiple memory devices 260; p. 0058-0059)
perform a data read operation on remaining memories excluding an error memory, among the plurality of memories (perform scrubbing on selected rows that are not sequential, or to exclude selected addresses from scrubbing or from error counting; p. 0103-0106. 0108),
perform a test read operation on the error memory (In another example, another mode may indicate that error scrubbing should be performed for excluded addresses, but the result should be excluded from counting; p. 0104-0106, 0114), and
sequentially perform detect read operations on memories other than one memory selected in rotation among the plurality of memories when a number of errors detected in the test read operation is smaller than a preset number (system can perform ECS operations, which include ECC operations to read, correct, and write back memory locations for all selected or specified addresses. In one example, the ECS system can read the memory array, correct errors with internal ECC (error checking and correction) logic, and write back corrected data. Excluded address memory is separate from address control and separate from the ECS engine, but accessible by the ECS engine. During scrubbing, address control can check the address to be scrubbed against the list of excluded addresses in excluded address memory. If the address is not contained in the list of excluded addresses, then the ECS operation can continue without any modifications what is described previously; p. 0044, 0113, 0134-135).
Regarding claim 14, BAINS discloses all of the limitations of claim 13. BAINS also discloses wherein the controller is configured to skip performing the detect read operations on the error memory (In one example, address generation logic receives as an input an ECS mode check, which represents the ECS mode configured for the ECS logic to execute. For example, one mode may indicate that error scrubbing should be skipped for excluded addresses; p. 0104).
Regarding claim 15, BAINS discloses all of the limitations of claim 13. BAINS also discloses wherein the controller is configured to:
perform a first detect read operation on memories other than a first memory among the plurality of memories (Thus, memory controller can determine whether a row hammer attack is happening on memory , can determine whether to provide hints and what hints to provide to ECS control, can determine what weights to apply to logic within ECS control , can adjust a rate of error scrubbing operations by ECS control of the memory, or other operations, or a combination of operations (first and second operation), based on operations performed by ECS control; p. 0080-0081, 0105);
perform a second detect read operation on memories other than a second memory among the plurality of memories, and compares a number of errors corrected in the first detect read operation with a number of errors corrected in the second detect read operation when an uncorrectable error does not occur in the first detect read operation and the second detect read operation (In one example, address control generates internal address information, shown as one of the inputs to compare. Compare represents an address comparator, or a comparison mechanism to compare generated addresses with addresses identified by the host as offline. The other input to compare is excluded address memory. In one example, compare compares the address generated by address control to all entries in excluded address memory. It will be understood that up to N address can be stored in excluded address memory, but there can be as few as zero addresses excluded, or any integer between 1 and N. If any address in excluded address memory matches with the generated address, the output of compare is set to true, or set to 1. If the addresses do not match, compare will output a zero; p. 0106, 0116).
Regarding claim 16, BAINS discloses all of the limitations of claim 15. BAINS also discloses wherein the number of error corrected in the first detect read operation is different from the number of errors corrected in the second detect read operation (In one example, address control generates internal address information, shown as one of the inputs to compare. Compare represents an address comparator, or a comparison mechanism to compare generated addresses with addresses identified by the host as offline. The other input to compare is excluded address memory. In one example, compare compares the address generated by address control to all entries in excluded address memory. It will be understood that up to N address can be stored in excluded address memory, but there can be as few as zero addresses excluded, or any integer between 1 and N. If any address in excluded address memory matches with the generated address, the output of compare is set to true, or set to 1. If the addresses do not match, compare will output a zero; p. 0106, 0116).
Regarding claim 17, BAINS discloses all of the limitations of claim 15. BAINS also discloses wherein when the number of errors corrected in the first detect read operation is smaller than the number of errors corrected in the second detect read operation, the controller is configured to set the first memory as a new error memory, and perform the data read operation on the memories other than the first memory (In one example, address control generates internal address information, shown as one of the inputs to compare. Compare represents an address comparator, or a comparison mechanism to compare generated addresses with addresses identified by the host as offline. The other input to compare is excluded address memory. In one example, compare compares the address generated by address control to all entries in excluded address memory. It will be understood that up to N address can be stored in excluded address memory, but there can be as few as zero addresses excluded, or any integer between 1 and N. If any address in excluded address memory matches with the generated address, the output of compare is set to true, or set to 1. If the addresses do not match, compare will output a zero. In one example, excluded address memory is part of address control. In one example, excluded address memory is separate from address control but part of the ECS engine (external device); p. 0106, 0113 0116).
Regarding claim 19, BAINS discloses a controller comprising:
a control circuit configured to perform a first read operation on a plurality of memories (ECS control 110 represents logic or control circuitry to generate control scrubbing operations within system; p. 0038, 0242, 0280, 0304, 0310); and
an error correction circuit configured to correct an error which occurs in the first read operation (Memory scrubbing is a background operation that fixes correctable errors and detects uncorrectable errors with the help of error checking and correction (ECC) mechanisms. Correction can detect and correct errors in data from multiple memory devices. Correction can be error correction logic or an error correction circuit within memory controller to perform operations on data received from memory devices related to error checking and correction; p. 0003, 0044, 0059), wherein the control circuit is configured to:
sequentially perform second read operations on memories excluding at least one memory selected in rotation among the plurality of memories when an uncorrectable error occurs in the first read operation (Scrubbing operations include a read to memory, detection and correction of errors, followed by a write to memory. (the adaptation to the realtime detected error information can result in the intelligent application of error scrubbing or other error mitigation (“excluding”) techniques, resulting in fewer uncorrectable errors in memory. In one example, the ECS operations include operations related to detection of uncorrectable errors and reporting the uncorrectable errors such as indication to the host or poisoning the data. System provides an example of applying memory address exclusion during internal memory scrubbing operations; p. 0004, 0031, 0038, 0108), and
set, as an error memory, a memory which is excluded in a second read operation in which a smallest number of errors is corrected, among the second read operations (the scrubbing operations are described below as ECS operations, referring to operations that check for errors, correct correctable errors that are found (correct detected errors), and write corrected data back to memory (“set as error memory”); p. 0038).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over BAINS in view of CHOI et al (U.S. Patent Application Publication No. 2019012973 A1), hereinafter referenced as CHOI.
Regarding claim 12, BAINS discloses all of the limitations of claim 1. BAINS also discloses wherein data read from the plurality of memories includes user data metadata and parity data (Memory can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of system; p. 0273).
Bains mentions a parity detect but does not explicitly teach wherein a size of the parity data is smaller than two times the unit size.
However, CHOI in the analogous art teaches wherein a size of the parity data is smaller unit size, but does not specifically teach 2 times smaller (a basic size unit of data and a parity that are input to the main memory or are output from the main memory may correspond to the size of 32 bytes or 64 bytes. Below, “current data” that are data that the processor currently writes or reads may mean data (e.g., 4 bytes), the size of which is smaller than 32 bytes being a reference size used in the main memory; p. 0030, 0032)
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the invention, to modify the system of BAINS with the teachings of Choi by choosing a size below the basic size of bits for detecting an error.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ the size of parity data which is smaller than 32 bytes being a reference size used in the main memory in the system of BAINS because CHOI teaches a main memory storing data and parity for detecting an error occurring in data upon writing the data to the memory or reading the data from the memory. (p. ABST, 0003).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over BAINS in view of Chen et al (U.S. Patent Application No 2024/0194283), hereinafter referenced as Chen.
Regarding claim 18, BAINS discloses all of the limitations of claim 16. BAINS fails to teach wherein the number of errors corrected in the first detect read operation is smallest among numbers of errors corrected in each of the detect read operations.
However, Chen in the analogous art teaches wherein the number of errors corrected in the first detect read operation is smallest among numbers of errors corrected in each of the detect read operations (in the another of the plurality of subsets to determine a second quantity of the read errors of the memory cells while pre-charging ones of the plurality of bit lines associated with the another of the plurality of subsets using the error correction algorithm; determine whether the first quantity is less than the second quantity; instruct the memory apparatus to pre-charge ones of the plurality of bit lines associated with the one of the plurality of subsets and read the memory cells associated therewith during the scan operation in response to the first quantity being less than the second quantity; p. 0152, 0163; Claims 2, 9, 15)
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of BAINS with the teachings of Chen by having the numbers of errors corrected in the first read operation be the smallest amongst the numbers of errors corrected in the other operations.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ during the scan operation in response to the first quantity being less than the second quantity in the system of BAINS because Chen teaches memory apparatus that includes an error correction algorithm with scan/read operations to improve bit line settling time (p. 0137).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over BAINS in view of Sforzin et al (U.S. Patent Application Publication 2025/0239320A1) hereinafter referenced as Sforzin.
Regarding claim 20, BAINS discloses all of the limitations of claim 19. BAINS also discloses wherein the control circuit is configured to perform the first read operation on memories excluding the error memory among the plurality of memories (ECS control represents logic or control circuitry to generate control scrubbing operations within system; p. 0038, 0242, 0280, 0304, 0310).
BAINS fails to teach wherein the control circuit is configured to perform a third read operation on the error memory.
However, Sforzin in the analogous art teaches wherein the control circuit is configured to perform the first read operation on memories excluding the error memory among the plurality of memories, and perform a third read operation on the error memory. (In some examples, the access component may be configured as or otherwise support a means for reading third data from one or more third memory cells of the memory system. In some examples, the error correction component may be configured as or otherwise support a means for determining that the third data includes zero errors based on reading the third data from the one or more third memory cells of the memory system. In some examples, the communication component may be configured as or otherwise support a means for transmitting the third data to the host device based on determining that the third data includes zero errors; p. 0055).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of BAINS with the teachings of Sforzin to perform a third read operation.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ the access component may be configured as or otherwise support a means for reading third data from one or more third memory cells of the memory system. in the system of BAINS because Sforzin teaches a third read in an error correction disablement memory system to improve the system's capability to identify and correct errors, which may improve the overall performance of the memory system (p. 0051-0055).
Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. This information has been detailed in the PTO 892 attached (Notice of References Cited).
The prior arts made of record teach:
LEE (US Patent Application No 2021/0311830 A1) teaches a storage device having improved original data recovery capability may include a memory device including a plurality of memory cells, and configured to perform a read operation on data stored in the plurality of memory cells according to read mode information, and to output read data associated with the read operation and a memory controller configured to receive the read data, change the read mode information when error correction decoding for the read data fails, and control the memory device to perform the read operation again according to the changed read mode information.
HALBERT (US Patent Application No 2019/0073261 A1) teaches an error check and scrub (ECS) mode enables a memory device to perform error checking and correction (ECC) and count errors. An associated memory controller triggers the ECS mode with a trigger sent to the memory device. The memory device includes multiple addressable memory locations, which can be organized in segments such as wordlines. The memory locations store data and have associated ECC information. In the ECS mode, the memory device reads one or more memory locations and performs ECC for the one or more memory locations based on the ECC information. The memory device counts error information including a segment count indicating a number of segments having at least a threshold number of errors, and a maximum count indicating a maximum number of errors in any segment.
SONG (US Patent Application No 2023/0280930 A1) teaches a memory system may include: a memory device including a plurality of memory cells; and a memory controller configured to store, as a fail address, a first internal address that is generated during a first read operation when at least one memory cell that is accessed during the first read operation among the plurality of memory cells is determined to be a fail, and store, as alternative data, internal read data that is generated during the first read operation.
JANG (US Patent Application No 2023/0056231 A1) teaches a memory system includes a memory; and a memory controller which includes a spare buffer suitable for storing an error location in the memory and data at the location, and commands the memory to perform a spare read operation when a read operation needs to be performed in a region of the memory including the error location.
EUN (US Patent Application No 2010/0287447 A1) teaches a read method for a memory system. The read method determines whether a read data error is correctable. The read method applies a plurality of read operations at a set read voltage level to identify erasure candidates, when the error is uncorrectable. The read method performs erasure decoding using an error correction code or an error detection code for the erasure candidates.
Conclusion
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/JAYLUN A JACKSON/Examiner, Art Unit 2112
/Shelly A Chase/Primary Examiner, Art Unit 2112
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