DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-14 filed on January 28, 2025 are pending.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1, 11 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12175936 in view of He (US 2024/0321198 A1, Filed June 29, 2022) and Shikata (US 11,151,941 B1, Patented October 19, 2021).
Present Application
US Patent 12175936
1. A display device comprising:
a display panel including:
a subpixel having a light emitting device configured to emit light according to an on duty ratio of an emission control signal and
a driving transistor configured to supply a driving current to the light emitting device, and
a data line connected to the subpixel;
a controller configured to: obtain a compensation value for compensating for an abnormal luminance variation of the display panel
based on coupling between a gate node of the driving transistor and the data line when a voltage of the data line is switched from a data voltage to a bias voltage in a vertical blank period of one frame, and
correct a data signal which is to be written in the display panel, based on the compensation value; and a data driver configured to convert a corrected data signal into a data voltage and output the data voltage to the data line.
1. A display apparatus, comprising:
a display panel in which a display region including first to third regions arranged in a horizontal direction is defined, and which includes a first data line and a second data line extending in a vertical direction and respectively connected to
first pixels of the first region and second pixels of the second region;
a driving transistor, a sampling transistor, and a data supply transistor included in each of the first and second pixels, the driving transistor having a gate electrode connected to a first node, the sampling transistor connected between a first electrode of the driving transistor and the first node and turned on during a sampling section, and the data supply transistor connected to a second electrode of the driving transistor at a second node and turned on during a data writing section within the sampling section;
a vertical link line disposed in the first region, extending in the vertical direction, and
a horizontal link line disposed in the third region between the first and second regions, and connecting the vertical link line and the second data line; and
a data compensation circuit which calculates a voltage coupling amount caused in the first pixel according to a change of data voltage that is applied to the vertical link line and provided to the second pixels during the sampling section after the data writing section of the first pixel,
calculates a compensation value for the voltage coupling amount, and
[the vertical link line] forming a parasitic capacitance with the first node of the first pixel;
applies the compensation value to a first input image data of the first pixel to generate a compensated image data.
1. A display device comprising:
a display panel including:
a subpixel having a light emitting device configured to emit light according to an on duty ratio of an emission control signal and a driving transistor configured to supply a driving current to the light emitting device, and
a data line connected to the subpixel;
a controller configured to: obtain a compensation value for compensating for an abnormal luminance variation of the display panel based on coupling between a gate node of the driving transistor and the data line when a voltage of the data line is switched from a data voltage to a bias voltage in a vertical blank period of one frame, and
correct a data signal which is to be written in the display panel, based on the compensation value; and a data driver configured to convert a corrected data signal into a data voltage and output the data voltage to the data line.
11. A display apparatus, comprising:
a display panel in which a first region and a second region disposed outside the first region in a horizontal direction are defined; a first data line and a second data line which extend in a vertical direction, and are connected to first pixels of the first region and second pixels of the second region, respectively;
a driving transistor, a sampling transistor, and a data supply transistor included in each of the first and second pixels, the driving transistor whose gate electrode is connected to a first node, the sampling transistor connected between a first electrode of the driving transistor and the first node, and the data supply transistor connected to a second electrode of the driving transistor at a second node;
a vertical link line disposed between the first data lines adjacent to each other in the first region, and
forming a parasitic capacitance with the first node of the first pixel;
a horizontal link line disposed between the first and second regions, and connecting the vertical link line and the second data line; and
a data compensation circuit which calculates a voltage coupling amount by applying a coupling gain to an amount of change in second input image data of the second pixels during a turn-on section of the sampling transistor of the first pixel after a horizontal period of the first pixel,
calculates a compensation value by applying a compensation gain to the voltage coupling amount, and generates a compensated image data by applying the compensation value to a first input image data of the first pixel.
Although the claims at issue are not identical, they are not patentably distinct from each other because the scope of claim 1 of the present application overlaps and encompasses the scope of claims 1, 11 of US Patent 12175936, and vice-versa, with the exception that the scope of claims 1, 11 of US Patent 12175936 does not expressly disclose the claimed aspect of: when a voltage of the data line is switched from a data voltage to a bias voltage in a vertical blank period of one frame, and correct a data signal which is to be written in the display panel, based on the compensation value.
However, He does disclose when a voltage of the data line is switched from a data voltage to a bias voltage in a vertical blank period of one frame, and correct a data signal which is to be written in the display panel, based on the compensation value (He at Claim 5 (including claim 1) discloses “The display panel according to claim 1, wherein the compensator compensates the currently displayed picture according to the sense result of the sense compensation circuit in the blank time of the currently displayed picture, comprising: the compensator calculates a voltage difference value corresponding to an amount of charge according to the amount of charge flowing through the element to be driven acquired by the sense compensation circuit in the blank time of the currently displayed picture; the compensator obtains a compensation gain value of the element to be driven according to the calculated voltage difference value.” ¶ [0054]).
US Patent 12175936 discloses a base display device upon which the claimed invention is an improvement. He discloses a comparable display device which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to US Patent 12175936 the teachings of He for the predictable result of preventing a problem of lateral fine stripes (He at ¶ [0061]).
The combination of US Patent 121745936 and He is silent as to the claimed aspect of: a light emitting device configured to emit light according to an on duty ratio of an emission control signal.
However, Shikata does disclose a light emitting device configured to emit light according to an on duty ratio of an emission control signal (Shikata at Figs. 2-3, emission control signal ESTV; col. 14, ll. 48-53 discloses “The variable control of the emission pulse control signal ESTV may include controlling the duty ratio of the emission control signal ESTV not to be constant. The control of the duty ratio of the emission control signal ESTV may be based on the emission control data stored in the storage 37.”).
The combination of US Patent 121745936 and He discloses a base display device upon which the claimed invention is an improvement. Shikata discloses a comparable display device which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to The combination of US Patent 121745936 and He the teachings of Shikata for the predictable result of reducing power consumption (Shikata at col. 1, ll. 19-20).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 13-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As to claim 13, Examiner is unable to locate in Applicant’s originally filed disclosure, the claimed aspect of “a scan line connected to a gate node of the driving transistor; a data line connected to a first node of the driving transistor.[]” Therefore, claim 13 fails to particularly point out and distinctly claim what Applicant regards as his invention.
For compact prosecution purposes and in accordance with Fig. 5 and Specification Paragraph [0118], Examiner will assume the claim 13 language recites “a scan line connected to a gate node of a first transistor.” Examine will also assume that the claim 13 language recites “a data line connected to a first node of a second transistor.”
Allowable Subject Matter
Subject to the Double Patenting rejection above, claims 1-12 are allowed.
Subject to the rejection of claims under 35 USC 112 above, claims 13-14 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 1, Koo (US 2023/0144298 A1, Published May 11, 2023) discloses a display device comprising:
a display panel including: a subpixel having a light emitting device configured to emit light according to an on duty ratio of an emission control signal (Koo at Figs. 1, 2, 7, EM) and
a driving transistor configured to supply a driving current to the light emitting device (Koo at Figs. 2, 7, D-TFT), and
a data line connected to the subpixel (Koo at Figs. 2, 7, Vdata);
a controller configured to: obtain a compensation value for compensating for an abnormal luminance variation of the display panel based on coupling between a gate node of the driving transistor and the data line when a voltage of the data line is switched from a data voltage to a bias voltage in a vertical blank period of one frame (Koo at Fig. 7, Anode Reset Frame is analogous to a vertical blank period of one frame; ¶ [0121]-[0122] discloses “As the parasitic capacitance Cpara is formed between the data line DL and the second node N2 of the driving transistor D-TFT during the anode reset frame period, it is possible to prevent a variation in the voltage level of the second node N2 of the driving transistor D-TFT by applying a preset level of voltage to the data line DL”), and
correct a data signal which is to be written in the display panel, based on the compensation value; and
a data driver configured to convert a corrected data signal into a data voltage and output the data voltage to the data line (Koo at Fig. 1).
However, none of the prior art found by the Examiner discloses the bolded and italicized claim language highlighted above in claim 1.
As to claim 7, claim 7 is allowable for similar reasoning given above for claim 1.
As to claim 13, Koo (US 2023/0144298 A1, Published May 11, 2023) discloses a display device comprising: a display panel (Koo at Fig. 1) including:
a subpixel having a light emitting device (Koo at Fig. 2 OLED),
an emission control transistor (Koo at Fig. 2, T5), and
a driving transistor (Koo at Fig. 2, D-TFT);
a scan line connected to a gate node of [a first transistor] the driving transistor (Koo at Fig. 2, T3);
a data line connected to a first node of [a second transistor] the driving transistor (Koo at Fig. 2, T1); and
a controller (Koo at Fig. 1),
wherein a first node of the emission control transistor is connected to a second node of the driving transistor (Koo at Fig. 2, node N3 where T5 and D-TFT are connected),
a second node of the emission control transistor is connected to the light emitting device (Koo at Fig. 2, node N4), and
an emission control signal is applied to a gate node of the emission control transistor (Koo at Fig. 2, EM(n).
However, none of the prior art found by the Examiner discloses the claimed aspect of: wherein the controller obtains a compensation value by integrating the emission control signal over a vertical blank period.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Baek (US 2025/0148982 A1, Published May 8, 2025)1 is made of record for its relevance to claims 1, 7 by its disclosure of the following at ¶ [0236]:
“[0236] Meanwhile, since the park voltage Vpark is a voltage supplied through the data line during the anode reset frame period, and the data voltage Vdata is a voltage supplied through the data line during the refresh frame period, when the luminance deviation in the refresh frame period is compensated, the compensated voltage supplied through the data line may be the data voltage Vdata.”
Joo (US 2024/0233615 A1, Published July 11, 2024)2 is made of record for its relevance to claim 13 by its disclosure of the following at ¶ [0119]:
“Referring to FIGS. 19 and 20, like the first embodiment described above, in the third embodiment of the present disclosure, an average luminance of a blank period BLK and an average luminance of an active period ACT may be adjusted to be equal to each other. In the third embodiment, in order to enable average luminance to be more easily adjusted in the blank period BLK, the blank period BLK may be subdivided into a plurality of blanks periods B1 to B3 which are continuous without another active period between the plurality of blank periods B1 to B3, an on duty ratio of an emission control signal EM in some blank periods B1 and B2 of the plurality of blank periods B1 to B3 may be controlled to be less than the active period ACT, and an on duty ratio of the emission control signal EM in the other blank period B3 of the plurality of blank periods B1 to B3 may be controlled to be greater than the active period ACT.”
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Sanjiv D Patel whose telephone number is (571)270-5731. The examiner can normally be reached Monday - Friday, 9:00 am - 5:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Boddie can be reached at 571-272-0666. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Sanjiv D. Patel/Primary Examiner, Art Unit 2625
12/28/2025
1 Not qualified as prior art.
2 Not qualified as prior art.