DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on January 28, 2025 has been considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claims 1, 2, 4 and 9-14 are objected to because of the following informalities: In Claim 1, line 1, please change “A LED” to “An LED”.
Please change every instance of “date” found in claims 1, 2, 4, 9, 10 and 14 to “data”. Claims 10-14 depend upon claim 9 and thus are also objected. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 15-16 and 18-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang et al. (U.S. Patent 11,783,765—hereinafter “Chang”).
As to Claim 1, Chang teaches a LED matrix driving system (Fig. 2A at 2000 and Col. 5, lines 23-48) with a micro controller (Fig. 2A at 20), comprising:
a monolithic integrated circuit switch device (Fig. 2A at 50), comprising:
a first terminal configured to receive a power supply voltage (Fig. 2A at VLED);
M scan terminals (Fig. 2A at Scan1-Scanm) configured to be respectively coupled to M scan lines (Fig. 2A at SL1-SLm) of the LED matrix;
a second digital interface (Fig. 2A at 51) configured to be connected to a first digital interface of the micro controller (Fig. 2A at 20) for receiving a date write transaction pack, wherein the date write transaction pack at least comprises M switch control codes for determining M switch control signals (Col. 5, line 49 – Col. 6, line 4); and
M power switches (Fig. 2A at S1-Sm) configured to be respectively connected to the M scan terminals (Fig. 2A at Scan1-Scanm), wherein in response to the M switch control signals, the first terminal of the monolithic integrated circuit switch device is successively connected to a corresponding scan terminal for controlling the LEDs of the M scan lines ON successively row by row (Col. 5, line 49 – Col. 6, line 4).
As to Claim 2, Chang teaches a monolithic integrated circuit drive device (Fig. 2A at 60), comprising: a third digital interface (Fig. 2A at 60) configured to be connected to the second digital interface (Fig. 2A at 51) of the monolithic integrated circuit switch device for receiving the date write transaction pack, wherein the date write transaction pack at least comprises N grayscale control codes for determining LED grayscale of N channels of the LED matrix (Col. 7, lines 4-19); and N drive terminals (Fig. 2A at DL1-DLn) configured to be respectively coupled to the N channels of the LED matrix and to provide N driving currents for the N channels of the LED matrix (Fig. 2A at IDr1-IDrn).
As to Claim 15, Chang teaches a method of driving a LED matrix (Fig. 2A at 2000 and Col. 5, lines 23-48), comprising:
connecting a first terminal of a monolithic integrated circuit switch device (Fig. 2A at 50) to a power supply circuit for receiving a power supply voltage (Fig. 2A at VLED);
connecting M scan terminals (Fig. 2A at Scan1-Scanm) of the monolithic integrated circuit switch device to M scan lines (Fig. 2A at SL1-SLm) of the LED matrix;
connecting a digital interface of the monolithic integrated circuit switch device (Fig. 2A at 51) to a digital interface of a micro controller (Fig. 2A at 20) to receive a data write transaction pack, wherein each bit of code of the data write transaction pack is transmitted during each clock cycle of a system clock signal (Col. 5, line 49 – Col. 6, line 4); and
loading M switch control codes of the data write transaction pack into a first storage unit (Fig. 2A at S1-Sm and Fig. 2A at 30 and Col. 5, line 49 - Col. 6, line 4) of the monolithic integrated circuit switch device for determining M switch control signals; and wherein
in response to the M switch control signals, successively connecting the first terminal of the monolithic integrated circuit switch device to a corresponding scan terminal for controlling the LEDs of the M scan lines ON successively row by row (Col. 5, line 49 – Col. 6, line 4).
As to Claim 16, Chang teaches respectively connecting N drive terminals (Fig. 2A at DL1-DLn) of a monolithic integrated circuit drive device (Fig. 2A at 60) to N channels of the LED matrix (Fig. 2A at IDr1-IDrn); connecting a digital interface of the monolithic integrated circuit drive device to the digital interface of the monolithic integrated circuit switch device for receiving the data write transaction pack (Col. 7, lines 4-19); and loading N grayscale control codes of the data write transaction pack into a second storage unit (Col. 5, line 49 – Col. 6, line 4) of the monolithic integrated circuit drive device for providing N driving currents for the N channels of the LED matrix (Col. 7, lines 4-19).
As to Claim 18, Chang teaches that the loading of the N grayscale control codes and the loading of the M switch control codes are both performed when a load control signal is asserted (Fig. 2B).
As to Claim 19, Chang teaches that the monolithic integrated circuit switch device comprises M power switches (Fig. 2A at S1-Sm), the first terminal of the monolithic integrated circuit switch device (Fig. 2A at Scan1) is connected to the corresponding scan terminal by turning on the corresponding power switch of the M power switches (Col. 5, line 49 – Col. 6, line 4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang in view of Han (USPGPUB 2021/0312843—hereinafter “Han”).
As to Claim 7, Chang fails to teach that the monolithic integrated circuit switch device further comprises a fault indication terminal for providing a fault indication signal, the micro controller is configured to receive the fault indication signal and to control the operation of the integrated circuit switch device based on the fault indication signal. Examiner cites Han to teach a display device comprising a fault indication terminal for providing a fault indication signal, the micro controller is configured to receive the fault indication signal and to control the operation of the integrated circuit switch device based on the fault indication signal (Pgs. 1-2, ¶ 7 and Pg. 5, ¶ 58). At the time of the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to incorporate a fault indication terminal for providing a fault indication signal, as taught by Han, in the LED matrix driving system taught by Chang, in order to properly detect faults in the system (Pg. 2, ¶ 8).
As to Claim 8, Chang, as modified by Han, teaches that the monolithic integrated circuit switch device further comprises a short-circuit detection circuit, wherein the short-circuit detection circuit is configured to determine if a voltage between the corresponding scan terminal and the first terminal of the monolithic integrated circuit switch device is less than a short-circuit threshold voltage during an off period of the corresponding power switch and to provide the fault indication signal based on the determination (Han, Pgs. 1-2, ¶ 7 and Pg. 5, ¶ 58).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang in view of Miyata (USPGPUB 2023/0397310—hereinafter “Miyata”).
As to Claim 5, Chang fails to teach that the monolithic integrated circuit switch device further comprises: M discharge circuits, each discharge circuit of the M discharge circuits is coupled between a corresponding scan terminal and a ground terminal of the monolithic integrated circuit switch device and is configured to provide a discharge path from the corresponding scan terminal to the ground terminal when the corresponding power switch is turned off. Examiner cites Miyata to teach an LED matrix driving system comprising M discharge circuits (Fig. 1 at 442), each discharge circuit of the M discharge circuits is coupled between a corresponding scan terminal (AL(1) – AL(n)) and a ground terminal of the monolithic integrated circuit switch device and is configured to provide a discharge path from the corresponding scan terminal to the ground terminal when the corresponding power switch is turned off (Col. 7, ¶ 123). At the time of the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to incorporate M discharge circuits, as taught by Miyata, in the LED matrix driving system taught by Chang, in order to properly discharge the scan lines.
Allowable Subject Matter
Pending corrections to the objections above, Claims 9-14 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: As to Claim 9, the prior art of record fails to teach or suggest, either alone or in combination, “A driving system for a LED matrix being arranged in K*M scan lines and L*N channels, the driving system comprising: K integrated circuit switch devices, wherein the K*M scan lines are divided into K groups and each one of the K groups has M scan lines, each one of the K integrated circuit switch devices has a respective digital interface for receiving a date write transaction pack and is configured to control the LEDs of the M scan lines of the corresponding group successively ON row by row; L integrated circuit drive devices, wherein the L*N channels are divided into L groups and each one of the L groups has N channels, each one of the L integrated circuit drive devices has a respective digital interface configured to receive the data write transaction pack and is configured to provide N driving currents for the LEDs of the N channels of the corresponding group; and a micro controller having a processor, a memory and a digital interface for providing the data write transaction pack, wherein the digital interface of the micro controller, K digital interfaces of the K integrated circuit switch devices, and L digital interfaces of the L integrated circuit drive devices are coupled in series and configured in a daisy-chain architecture, the data write transaction pack is transmitted from a previous digital interface in the daisy-chain architecture to a latter digital interface in the daisy chain architecture.” (As claimed, emphasis added).
Claims 10-14 depend upon Claim 9 and thus are also allowed.
Claims 3, 4, 6, 17 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Togashi et al. USPGPUB 2003/0184237
Nam et al. USPGPUB 2008/0291181
Chao et al. USPGPUB 2022/0223099
Park USPGPUB 2025/0265971
Inquiries
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RODNEY AMADIZ whose telephone number is (571)272-7762. The examiner can normally be reached Mon - Thurs; 9AM - 5PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Patrick Edouard can be reached at 571-272-7603. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/RODNEY AMADIZ/Primary Examiner, Art Unit 2622
Prosecution Insights