Prosecution Insights
Last updated: August 17, 2026
Application No. 19/039,548

HYBRID COMPARATOR CIRCUIT DEVICE

Non-Final OA §112
Filed
Jan 28, 2025
Priority
Mar 19, 2024 — RE 10-2024-0037826
Examiner
NGUYEN, LONG T
Art Unit
2842
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Korea University Research and Business Foundation
OA Round
1 (Non-Final)
89%
Grant Probability
Favorable
1-2
OA Rounds
4m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
839 granted / 940 resolved
+21.3% vs TC avg
Moderate +8% lift
Without
With
+8.3%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 10m
Avg Prosecution
22 currently pending
Career history
973
Total Applications
across all art units

Statute-Specific Performance

§101
0.8%
-39.2% vs TC avg
§103
19.0%
-21.0% vs TC avg
§102
37.2%
-2.8% vs TC avg
§112
32.9%
-7.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 940 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Drawings The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: “VL,B”, “SL,B” and “SH,B”. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. The drawings are also objected to because: in Figure 5, the signal at gates N6-N7 is not provided with any label, so it is not clear what is the signal at the gates of N6-N7; it is not clear why the gate of P6 is labeled with signal “SL,B” while the specification recites that signal “SL” is at the gate of transistor P6 (see lines 8-10 on page 7 of the specification); and it is also not clear why the gate of transistor P7 is labeled with signal “SH,B” while the specification recites that signal “SH” is at the gate of transistor P7 (see line 25 of page 7 to line 2 of page 8 of the specification). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification The disclosure is objected to because of the following informalities: on page 3 (line 20) and on page 9 (lines 13-14), it is suggested that “- input terminal” be changed to “inverting input terminal”, and “+ input terminal” be changed to “non-inverting input terminal”. Appropriate correction is required. Claim Objections Claims 1-5 are objected to because of the following informalities: In claims 1-5, the claims are objected to because they include reference characters which are not enclosed within parentheses. Reference characters corresponding to elements recited in the detailed description of the drawings and used in conjunction with the recitation of the same element or group of elements in the claims should be enclosed within parentheses so as to avoid confusion with other numbers or characters which may appear in the claims. See MPEP § 608.01(m). Also, in claim 5, it is suggested that “+ input terminal” (line 2) and “- input terminal” (line 3) be changed to “non-inverting input terminal” and “inverting input terminal”, respectively. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-5 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. For claim 1, the recitation “a first mode operation circuit unit detecting a first point where a first reference signal VREG is the same as a low AC input signal by receiving the low AC input signal VINN; a second mode operation circuit unit detecting a second point where a second reference signal VREG is the same as a high AC input signal by receiving the high AC input signal VINN” recites on lines 2-5 of the claim is indefinite because it is not clear how can an reference signal VREG can be two different signals of “a first reference signal VREG” and “a second reference signal VREG” since Figure 5 discloses and shows only a reference signal “VREG” connected to both the first mode operation circuit unit 510 and the second mode operation circuit 520 (see Figure 5). Further, it is also not clear how can an AC input signal VINN can be two different signals of “a low AC input signal VINN” and “a high AC input signal VINN” since Figure 5 discloses and shows only an AC input signal “VINN” connected to both the first mode operation circuit unit 510 and the second mode operation circuit 520 (see Figure 5). Therefore, the recitation “a first mode operation circuit unit detecting a first point where a first reference signal VREG is the same as a low AC input signal by receiving the low AC input signal VINN; a second mode operation circuit unit detecting a second point where a second reference signal VREG is the same as a high AC input signal by receiving the high AC input signal VINN” recites on lines 2-5 of the claim is not understood since the circuitry discloses the same “AC input signal VINN” (instead of low AC input signal VINN and high AC input signal VINN) and the same “reference signal VREG” (instead of first and second VREG), and thus it is not clear when the first mode operation circuit unit is operated for detecting a first point and when the second mode operation circuit unit is operated for detecting a first point. Clarification and/or appropriate correction is required. Claims 2-5 are indefinite because they depend on claim 1 and include the indefinite of claim 1. Also, in claim 2, the recitation “the input signal VINN” lacks clear antecedent basis. Further, the recitation “wherein the first transistor N1 and the second transistor N2 are any one of NMOS and PMOS, and the third transistor P1 and the fourth transistor P2 are the other one of NMOS and PMOS” on line 8-10 would also be misdescriptive when “the first transistor N1 and the second transistor N2 are PMOS, and the third transistor P1 and the fourth transistor P2 are NMOS” since the disclosure clearly discloses and shows that “the first transistor N1 and the second transistor N2 are NMOS, and the third transistor P1 and the fourth transistor P2 are PMOS” (see Figure 5 and its description of Figure 5). Clarification and/or appropriate correction is required. Also, in claim 3, the recitation “the reference signal VREG” (lines 2 and 4) lacks clear antecedent basis. Clarification and/or appropriate correction is required. Also, in claim 5, the recitation “inverting and receiving a control signal output by the first internal MUX M2” on line 7-8 is indefinite because it is not clear what applicant means by “inverting and receiving a control signal output by the first internal MUX M2”, and “a control signal output” is unclear antecedent basis (see line 5). Further, “a high control signal SH” on line 8 is unclear antecedent basis because it is not clear if it is the same signal as “a high mode control signal (see claim 4). Further, the recitation “inverting and receiving the inverted control signal again, and then a low control signal SL” on line 10-11 is indefinite because it is not clear what applicant means by “inverting and receiving the inverted control signal again”, and it is also not understood what it means by “and then a low control signal SL”. Further, the recitation “a low control signal SL” on line 11 is unclear antecedent basis because it is not clear if it is the same signal as “a low mode control signal (see claim 4). Further, the recitation “the inverted control signal” (lines 12 and 15) lacks clear antecedent basis and it is not clear which signal it is referred to. Further, “a detection result” is unclear antecedent basis (see line 6, claim 1). Clarification and/or appropriate correction is required. Conclusion Because the metes and bounds of the claims cannot be determined as discussed in the indefinite rejections above, no prior art rejection(s) can be applied against these claims at this time. Note that this is NOT an indication of allowability. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yano et al. (US 2026/0088810) discloses in Figure 1 a circuit including comparators 110 and 120, and a mux 160. Wu et al. (USP 10,707,821) discloses in Figure 1 a circuit including amplifiers 120 and 140, and a mux 160. Any inquiry concerning this communication or earlier communications from the examiner should be directly to Examiner Long Nguyen whose telephone number is (571) 272-1753. The Examiner can normally be reached on Monday to Friday from 8:30am to 5:00pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch, can be reached at (571) 270-7101. The fax number for this group is (571) 273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. /Long Nguyen/ Primary Examiner Art Unit 2836
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Prosecution Timeline

Jan 28, 2025
Application Filed
Jul 29, 2026
Non-Final Rejection mailed — §112 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
89%
Grant Probability
98%
With Interview (+8.3%)
1y 10m (~4m remaining)
Median Time to Grant
Low
PTA Risk
Based on 940 resolved cases by this examiner. Grant probability derived from career allowance rate.

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