Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4-6 and 10-12 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 4, 10 retie the limitation “wherein a second layer of the PCB assembly includes a 90-degree hybrid coupler” which renders the claimed indefinite because claim 1, line 11, recites “an intermediate layer between the first layer and the backing ground layer”. It is not clear whether the second layer is one of the intermediated layer between the first layer and the backing ground layer or additional layer outside the first layer and the backing ground layer.
Claims 5-6, 11-12 are rejected for being dependent on the indefinite claim .
Clarifications are required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Puzella et al (US 2010/0066631, IDS dated 4/2/25).
Regarding claims 1 and 7, Puzella discloses in Figures 1B-1C, 2, Fig. 3 and pars. 0153, 0155, an antenna assembly comprising:
a stack patch antenna assembly defining a plurality antenna cells (cells formed by wall26a, 26b, Fig. 1B and par. 0108);
a beamformer lattice (20, Fig. 1B and par. 0153) including one or more beamformers, wherein each beamformer corresponds to a subset of antenna cells of the plurality of antenna cells; and
a PCB assembly (36, Fig. 1B and par. 0153) coupled to the stack patch antenna assembly and the beamformer lattice, the PCB assembly made up from a plurality of layers, wherein
a first layer (101, Fig. 1c or 266a, Fig. 3) is an antenna ground layer having a slot feed (101a or 101b, Fig. 1 or 314a, 314b, Fig. 3, par. 0160) to electrically couple a plurality of antenna cells of the stack patch antenna assembly to one of the one or more beamformers in the beamformer lattice,
wherein the first layer (101, Fig. 1c or 266a, Fig. 3) is spaced from a backing ground layer (282b, Fig. 3 and par. 0170) defining a plurality of cavities between the first layer (266a, Fig. 3) and the backing ground layer (282b, Fig. 3),
each cavity associated with one of the plurality of antenna cells, and further including an intermediate layer (layers between 266a and 282b in Fig. 3) between the first layer and the backing ground layer,
wherein the intermediate layer includes cavity regions (regions between 290 and 304, see Fig. 3) and non-cavity regions (regions outside of cavity 290, 304, Fig. 3), wherein the non- cavity regions are configured to support electrical features disposed outside the plurality of cavities.
Regarding claims 2 and 8, as applied to claims 1 and 7, Puzella discloses in Figure 3,
wherein the PCB assembly includes a plurality of ground vias (290, 304) between the first layer (266a) and the backing ground layer (282b) defining the plurality of cavities.
Regarding claims 3 and 9, as applied to claims 1 and 7, Puzella discloses in Figure 3, wherein the slot feed is dual circularly polarized with separate receiving and transmitting ports (see pars. 0099 and 0157).
Regarding claims 4-6 and 10-12, as applied to claims 1 and 7, Puzella discloses in Figure 3,
wherein a second layer of the PCB assembly includes a 90-degree hybrid coupler (“a quadrature hybrid circuit 216”, see par. 0139 and Fig. 2; note that: upper multi-layer assembly UMLA 202 in Fig. 2 included UMLA 18 in Figs. 1a-1c, see par. 0139; thus, the hybrid circuit 216 including UMLB 18 of the UMLA 36);
wherein a third layer (270a) of the PCB assembly includes a partial ground layer (270a) to partially isolate the second layer (280b) from a fourth layer (282b) outside the cavity regions.
wherein the fourth layer 9272b) of the PCB assembly includes one or more calibration lines configured for coupling the stack patch antenna assembly and the beamformer lattice for calibration purposes.
Regarding claim 13, Puzella discloses in Figures 1B-1C, 2-3, an antenna assembly comprising:
a stack patch antenna assembly defining a plurality antenna cells (cells formed by wall 26a, 26b, Fig. 1B and par. 0108);
a PCB assembly coupled to the stack patch antenna assembly, the PCB assembly made up from a plurality of layers that define at least a first cavity (cavity formed by 290, 304, Fig. 3),
wherein the plurality of layers includes a first layer (101, Fig. 1c or 266a, Fig. 3),
a second layer (282b, Fig. 3), and
a third layer,
wherein the first layer (266a) is spaced apart from the second layer (282b) such that the first cavity (cavity formed by vias 290 and 304) is defined between the first and second layer,
wherein the third layer (layer between 266a and 282b, Fig. 3) is positioned between the first and second layer and includes a portion disposed outside of the first cavity, (portion outside of 290 and 304) and wherein the portion of the third layer is configured to support electrical features disposed outside of the first cavity.
Regarding claim 14, as applied to claim 13, Puzella discloses in Figure 3,
wherein the PCB assembly includes a plurality of ground vias (290, 304) between the first layer and the second layer.
Regarding claims 15-16, as applied to claim 13, Puzella discloses in Figures 1c, 3, wherein the third layer of the PCB assembly includes a 90-degree hybrid coupler (“a quadrature hybrid circuit 216”, see par. 0139 and Fig. 2; note that: upper multi-layer assembly UMLA 202 in Fig. 2 included UMLA 18 in Figs. 1a-1c, see par. 0139; thus, the hybrid circuit 216 including UMLB 18 of the UMLA 36).
Regarding claims 17-18, as applied to claim 13, Puzella discloses in Figure 3, wherein the first and second layers (266a, 282b) are ground layers;
wherein the first layer (266a) includes a slot feed (314a) to electrically couple a plurality of antenna cells of the stack patch antenna assembly to one or more beamformers (see par. 0153).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 13-17 of U.S. Patent No. 12,381,315. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims 1 and 13-17 of the above Patent recite all the limitation of claims 1-18 of the instant application.
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Breglia et al (US 6,492,949) discloses slot fed antenna array with cavity region and non-cavity region in Figure 11.
Ogilvie (US 9,755,306) discloses multi-layer phase array.
Inquiry
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/DIEU HIEN T DUONG/ Primary Examiner, Art Unit 2845
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