DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4,6-10 are rejected under 35 USC 103 as being unpatentable over Thacker et al; (US 7348786) in view of Lee et al; (TW I681196B).
Regarding claim 1, Thacker discloses an optoelectronic integrated circuit testing device configured to test an optoelectronic integrated circuit, (probe module for testing chips with both electrical and optical input/output signals, see figure 1) comprising: an automated testing equipment;(Automated test system 50 with automated test equipment (ATE) 130, see figure 1) an optical fiber connected to the automated testing equipment;( The ATE connection interface 170 can be implemented with, but not limited to, electrical wire, optical fiber, and/or fiber optic ribbon, see column 4, lines 9-11 and figure 1) a receiving interface module disposed on the automated testing equipment,( an ATE connection interface 170, see figure 1) and provided with an optical fiber through hole for the optical fiber to pass through; a plurality of probes, wherein each probe is connected to the receiving interface module;( Probes connected to metallized through-holes or vias can also be utilized to transfer both electrical and optical signals to the backside of the probe substrate 810 as shown in FIG. 14, see column 10, lines 44-47) and wherein the plurality of probes pressed against the optoelectronic integrated circuit when testing the optoelectronic integrated circuit, and the optical fiber receives optical communication signals transmitted from the optoelectronic integrated circuit ;( a waveguide 250, an optical fiber for optical routing and the waveguides 250 are commonly used to route optical signals at a substrate level 110 and 120, see column 5, lines 58-65).
However, Thacker does not explicitly disclose a guide plate module disposed on the receiving interface module, wherein the plurality of probes and the optical fiber pass through the guide plate module.
In a related field of endeavor, Lee discloses a guide plate module disposed on the receiving interface module, wherein the plurality of probes and the optical fiber pass through the guide plate module ;(the upper guide plate unit 11 includes a first guide plate 111, a second guide plate 112 spaced apart from the first guide plate 111 and a plurality of conductive probes 15, 15 a passing through the upper and lower guide plate units 11, 13 and the partition plate 14, see page 3, paragraph 6 and figure 1).
Thus, it would be obvious for one the ordinary skilled in the art before the effective filling date of the invention to combine the guide pate of Lee with Thacker to provide high precision testing in the integrated circuit and the motivation is to provide increased efficiency of testing of the integrated circuit.
Regarding claim 2, Thacker does not explicitly disclose the optoelectronic integrated circuit testing device according to claim 1, wherein the guide plate module comprises: a first guide plate disposed on the receiving interface module, wherein the first guide plate comprises a plurality of first guide plate through holes for the optical fiber and the plurality of probes to pass through; and a second guide plate disposed on the first guide plate, wherein the second guide plate comprises a plurality of second guide plate through holes for the optical fiber and the plurality of probes to pass through.
In a related field of endeavor, Lee discloses the optoelectronic integrated circuit testing device according to claim 1, wherein the guide plate module comprises: a first guide plate disposed on the receiving interface module, wherein the first guide plate comprises a plurality of first guide plate through holes for the optical fiber and the plurality of probes to pass through ;( the upper guide plate unit 11 includes a first guide plate 111, a second guide plate 112 spaced apart from the first guide plate 111, and clamped to the first guide plate A support plate 113 between 111 and the second guide plate 112 and a flexible board 114 (flexible board) disposed on the
second guide plate 112 and away from the first guide plate 111, see page 3, paragraph 6 and figure 1) a second guide plate disposed on the first guide plate, wherein the second guide plate comprises a plurality of second guide plate through holes for the optical fiber and the plurality of probes to pass through ;(the upper guide plate unit 11 includes a first guide plate 111, a second guide plate 112 spaced apart from the first guide plate 111 and a plurality of conductive probes 15, 15 a passing through the upper and lower guide plate units 11, 13 and the partition plate 14, see page 3, paragraph 6 and figure 1). Motivation same a claim 1.
Regarding claim 3, Thacker discloses the optoelectronic integrated circuit testing device according to claim 1, wherein portions where the plurality of probes are respectively provided with a probe elastic portion ;(the probe material has properties such as, , elasticity, high conductivity, and non-tarnishment, see column 14, lines 14,15).
However, Thacker does not explicitly disclose pass through the guide plate module.
In a related field of endeavor, Lee discloses pass through the guide plate module ;(the upper guide plate unit 11 includes a first guide plate 111, a second guide plate 112 spaced apart from the first guide plate 111 and a plurality of conductive probes 15, 15 a passing through the upper and lower guide plate units 11, 13 and the partition plate 14, see page 3, paragraph 6 and figure 1). Motivation same a claim 1.
Regarding claim 4, Thacker discloses the optoelectronic integrated circuit testing device according to claim 1, wherein the receiving interface module comprises: a printed circuit (probe substrate 110, see figure 1) board provided on the automated testing equipment, wherein the printed circuit board is provided with a first optical fiber through hole for the optical fiber to pass through;( a probe substrate 110 is the portion of the probe module 100 that interacts with the DUT I/O through electrical and optical probes 150 and 160 mounted on the face or front-side of the probe substrate 110, see column 4, lines 16-21 and figure 1) and a space converter provided on the printed circuit board, wherein the space converter is provided with a second optical fiber through hole for the optical fiber to pass through;(optical I/O can be accomplished through the use of optical elements 200 located on the probe substrates 110 and/or the distribution substrates 120 and various coupling mechanisms (e.g., free-space, quasi-free-space, waveguide, see column 4, lines 30-34) wherein each probe connected to the space converter, and each optical fiber through hole comprises the first optical fiber through hole and the second optical fiber through hole respectively ;( Probes connected to metallized through-holes or vias can also be utilized to transfer both electrical and optical signals to the backside of the probe substrate 810 as shown in FIG. 14, see column 10, lines 44-47).
Regarding claim 6, Thacker discloses the optoelectronic integrated circuit testing device according to claim 2, wherein the optical fiber further comprises an optical fiber head, and wherein the optical fiber head passes through the second guide plate through hole; (the probe module 100 provides an interface between the ATE 130 and the DUT 140. This can be accomplished using electrical probes 150, optical probes 160, optical elements 200, and combinations thereof, to acquire signals from and send signals to the DUT 140 and redistributing these signals to the ATE 130 through an ATE connection interface 170, see column 4, lines 3-9).
Regarding claim 7, Thacker discloses the optoelectronic integrated circuit testing device according to claim 2, wherein a first adhesive layer is coated on;(electrical I/O interconnections can be accomplished through the use of a suitable technology that can include, but is not limited to, solder bumps or conductive adhesives, see column 5, lines 49-51).
However, Thacker does not explicitly disclose an inside of the first guide plate through hole.
In a related field of endeavor, Lee discloses an inside of the first guide plate through hole ;( the upper guide plate unit 11 includes a first guide plate 111, a second guide plate 112 spaced apart from the first guide plate 111, and clamped to the first guide plate A support plate 113 between 111 and the second guide plate 112 and a flexible board 114 (flexible board) disposed on the second guide plate 112 and away from the first guide plate 111, see page 3, paragraph 6 and figure 1). Motivation same as claim 1.
Regarding claim 8, Thacker discloses the optoelectronic integrated circuit testing device according to claim 2, wherein a second adhesive layer is coated on; ;( Electrical I/O interconnections can be accomplished through the use of a suitable technology that can include, but is not limited to, solder bumps or conductive adhesives, see column 5, lines 49-51).
However, Thacker does not explicitly disclose an inside of the second guide plate through hole.
In a related field of endeavor, Lee discloses an inside of the second guide plate through hole ;( the upper guide plate unit 11 includes a first guide plate 111, a second guide plate 112 spaced apart from the first guide plate 111, and clamped to the first guide plate A support plate 113 between 111 and the second guide plate 112 and a flexible board 114 (flexible board) disposed on the second guide plate 112 and away from the first guide plate 111, see page 3, paragraph 6 and figure 1). Motivation same as claim 1.
Regarding claim 9, Thacker discloses the optoelectronic integrated circuit testing device according to claim 1, wherein the optical fiber is positioned around the plurality of probes ;( an optical signal is input into the DUT 840, an optical source 510 located on the probe substrate 810 or on the ATE 130 feeds an optical waveguide 250 where an optical element 200 bends the light in a surface normal direction into the polymer pillar probe 1670 where it is guided into the polymer pillar 1680 on the DUT 840, see column 11, lines 54-61 and figure 16c).
Regarding claim 10, Thacker does not explicitly disclose the optoelectronic integrated circuit testing device according to claim 2, wherein a third guide plate is disposed between the first guide plate and the second guide plate, and wherein the third guide plate comprises a plurality of third guide plate through holes for the optical fiber and the plurality of probes to pass through.
In a related field of endeavor, Lee discloses the optoelectronic integrated circuit testing device according to claim 2, wherein a third guide plate is disposed between the first guide plate and the second guide plate, and wherein the third guide plate comprises a plurality of third guide plate through holes for the optical fiber and the plurality of probes to pass through ;(the support plate 113 (third guide plate) has a ring shape and the support plate 113 is sandwiched between the outer portion of the first guide plate 111 and the outer portion of the second guide plate 112, so that the first A guide plate 111 and a second guide plate 112 can be kept spaced apart from each other, and the plurality of first through holes 1111 of the first guide plate 111 and the second through holes 1121 of the second guide plate 112 are all connected to the support plate 113 The space surrounded by the edge, see page 4 and paragraph 3). Motivation same as claim 1.
Claim 5 is rejected under 35 USC 103 as being unpatentable over Thacker et al; (US 7348786) in view of Lee et al; (TW I681196B) and further in view of Sato (US 11762008).
Regarding claim 5, the combination of Thacker and Lee does not explicitly disclose the optoelectronic integrated circuit testing device according to claim 1, wherein a length of the plurality of probes protruding from the guide plate module is longer than a length of the optical fiber protruding from the guide plate module.
In a related field of endeavor, Sato discloses the optoelectronic integrated circuit testing device according to claim 1, wherein a length of the plurality of probes protruding from the guide plate module is longer than a length of the optical fiber protruding from the guide plate module ;( a plurality of guide plates 31 and 32 arranged between the upper surface and the lower surface separately from each other in the vertical direction through which the electric contacts 10 (probe) and the optical contacts 20, (optical contact 20 to be used is an optical fiber) penetrate wherein electrical contacts 10 longer than optical contacts 10, see figure 2).
Thus, it would be obvious for one the ordinary skilled in the art before the effective filling date of the invention to combine the electrical and optical contacts of Sato with Thacker and Lee to provide electric contact 10 and the optical contact 20 connected to the signal terminals of the optoelectronic device and the motivation is to ensure a predetermined measurement accuracy.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is reproduced below.
a. Lu et al; (US 2025/0216419) discloses probe card that includes a substrate portion, and a probe head including a guide plate located below the substrate portion and having a plurality of openings through the guide plate, and a conductive trace on the guide plate that extends between a pair of the openings. A plurality of probe pins extend through the openings through the guide plate, where a pair of probe pins are electrically connected by the conductive trace to form a loopback signal path, see figure 1.
b. Bolt et al; (US 9804196) discloses probes including a beam portion and a probe tip that is configured to contact a device under test (DUT), and further include a fiducial mark formed on the beam portion that is configured to facilitate alignment of the probe and the DUT, see figure 14.
c. Hara et al; (US 9246579) discloses apparatus comprising a device mounting section on which the device under test is mounted; an optical connector that is connected to the optical interface of the device under test; and an optical signal detecting section that detects an optical signal output from at least one of the optical interface and the optical connector, before the optical interface of the device under test mounted on the device mounting section is connected to the optical connector, see figure 1.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMRITBIR K SANDHU whose telephone number is (571)270-1894. The examiner can normally be reached M-F 9am to 5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kenneth Vanderpuye can be reached at 571-272-3078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/AMRITBIR K SANDHU/ Primary Examiner, Art Unit 2634
Prosecution Insights