DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent No. 12,248,405. Although the claims at issue are not identical, they are not patentably distinct from each other because the differences are not material to patentability. Essentially all that has been done is remove limitations from the independent claims and put them in dependent claims. It is obvious to remove limitations from patented claims. Patented claim 1 is compared with instant claim 3 in the table below:
Instant claim 3 (including independent claim 1 and intervening claim 2)
Patented claim 1
1. An integrated circuit system comprising:
1. An integrated circuit for executing instructions comprising:
a processor configured to transmit a memory request to a target module over a bus of an integrated circuit,
a processor configured to transmit a memory request to a target module over a bus of the integrated circuit,
wherein the memory request requests access to one or more memory mapped resources, wherein the memory request includes a physical address;
wherein the memory request requests access to one or more memory mapped resources, wherein the memory request includes a physical address;
and a first boundary function circuit configured to translate the physical address to a relative address, wherein the relative address operates in or applies to a different address space than an address space that the physical address operates in or applies to,
a first boundary function configured to translate the physical address to a relative address, wherein the relative address operates in or applies to a different address space than an address space that the physical address operates in or applies to,
wherein the first boundary function circuit is programmed to identify the physical address, subtract a physical base address from the physical address, and add a relative base address to a subtracted physical address to generate the relative address.
wherein the first boundary function is programmed to identify the physical address, subtract a physical base address from the physical address, and add a relative base address to a subtracted physical address to generate the relative address;
2. The integrated circuit system of claim 1, further comprising: a second boundary function circuit configured to translate the relative address to the physical address, wherein the second boundary function circuit is programmed to identify the relative address, subtract the base relative address, and add the physical base address to a subtracted relative address to generate the physical address.
a second boundary function configured to translate the relative address to the physical address, wherein the second boundary function is programmed to identify the relative address, subtract the base relative address, and add the physical base address to a subtracted relative address to generate the physical address;
3. The integrated circuit system of claim 2, further comprising: a device configured to utilize the physical address transmitted by the second boundary function circuit.
and a device configured to utilize the physical address transmitted by the second boundary function.
Conclusion
Any inquiry concerning this Office action should be directed to the Examiner by phone at (571) 272-4214.
Any response to this Office action should be labeled appropriately (including serial number, Art Unit 2132, and type of response) and mailed to Commissioner for Patents, P.O. Box 1450, Alexandria, VA 22313-1450; hand-carried or delivered to the Customer Service Window at the Knox Building, 501 Dulany Street, Alexandria, VA 22314; faxed to (571) 273-8300; or filed electronically using the Patent Center.
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/Kevin Verbrugge/
Kevin Verbrugge
Primary Examiner
Art Unit 2132