Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are now pending in the application under prosecution and have been examined.
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors.
The specification should be amended to reflect the status of all related application, whether patented or abandoned. Therefore, applications noted by their serial number and/or attorney docket number should be updated with correct serial number and patent number if patented.
The first instance of all acronyms or abbreviation should be spelled out for clarity, whether or not considered well known in the art.
In the response to this Office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application.
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
37 C.F.R. § 1.83(a) requires the Drawings to illustrate or show all claimed features.
Applicant must clearly point out the patentable novelty that they think the claims present, in view of the state of the art disclosed by the references cited or the objections made, and must also explain how the amendments avoid the references or objections. See 37 C.F.R. § 1.111(c).
US 20230118797 (KIM et al) in view of US 20220398014 A1 (AMARO et al)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-9 and 13-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 20230118797 (KIM et al) in view of US 20200409856 (NAVON et al).
With respect to claim 1, US 20230118797 (KIM et al) teaches an internal memory reclaiming method, performed by a computer device that comprises at least two groups of SWAP devices (data swapping method including identifying swap devices among the plurality of swap devices classified into a plurality of data into groups) [Par. 0008-0014; Par. 0019-0020], the method comprising:
determining page access frequency information of an internal memory page
(instructions to, based on attributes of at least one swap device of the plurality of swap devices, generate association information between the attributes of the data and the attributes of the at least one swap device wherein attributes refers to an execution frequency of the data (based on data usage history information corresponding to each of the group), data integrity of the data in swapping, erasability of the data) [Par. 0008-0014; Par. 0074-0075] the mapping module 1113 may map the group and the swap device based on at least one of whether the UI is related, the execution frequency, the erasability, the memory range accessed per unit time, or the data integrity of the group attributes where the reclaim module to select (or determine), as the swapping target, at least one page having a low execution frequency (or the number of uses) or having the oldest last execution (or use) among the pages stored in the memory [Par. 0190-0193; Par. 0074-0075];
determining a target SWAP device from the at least two groups of SWAP devices based on the page access frequency information
(identifying, as a swapping target, at least a portion of data included in each of the groups, based on data usage history information corresponding to each of the groups) [Par. 0019; Par. 0008-0020; Par. 0074-0075]; the processor to determine the swap device for swapping data among the plurality of the swap devices, based on the attributes of the data and the attributes of each of the plurality of the swap devices [Par. 0081-0083];
transferring content data stored in the internal memory page to the target SWAP device
(swapping the identified at least the portion of data using the swap device corresponding to each of the groups) [Par. 0019]; Par. 0008-0020; Par. 0074-0075; Par. 0134-0135].
KIM fails to specifically teach internal memory page to be reclaimed based on receiving an internal memory reclaiming instruction. However, NAVON teaches input/output (IO) interface to receives commands from the host where examples of storage commands include garbage collection (data relocation commands), read scrub (refreshing of data values stored in memory cells) commands [Par. 0059]; cache utilization manager that manages and/or tracks a set of cache utilization metrics for the cache entries where partition access frequency and cache access frequency are possible cache utilization metrics [Par. 0061}, cache swap manager to identify a cache eviction candidate where the cache eviction candidate defines a level that a cache utilization metric satisfied to be evicted from a mapping table cache [Par. 0062-0065]; If a cache eviction candidate has been modified since it was last loaded from the address mapping table, the cache manager directs the store module to modify the cache eviction candidate to the non-volatile memory [Par. 0083-0087]. Therefore it would have been obvious to one having at least ordinary skill in the art before the effective filing date of the instant application to modify the data swapping method including identifying swap data, taught by KIM by determining access frequency information of an internal memory page to be reclaimed based on receiving an internal memory reclaiming instruction, as taught by NAVON, in order to carry the swapping to a modified scored data entry for the retrieved entry that has been modified (e.g., accessed a predetermined number of times) preserving the previous cache eviction candidate, as taught by NAVON [Par. 0087-0089].
With respect to claim 2, KIM and NAVON, combined teach the method wherein determining a target SWAP device matching the page access frequency information from the at least two groups of SWAP devices comprises: obtaining speed indication information of the at least two groups of SWAP devices, wherein the speed indication information represents an access speed of accessing content data from the SWAP device (processor to determine the swap device for swapping data among the plurality of the swap devices, based on the attributes of the data (access frequency) data having a high execution frequency) [KIM’s Par. 0081-0084]; and determining the target SWAP device from the at least two groups of SWAP devices based on the page access frequency information and the speed indication information, wherein the target SWAP device has a target access speed matching the page access frequency information (the processor to determine the swap device for swapping data among the plurality of the swap devices based on attributes of each of the plurality of the swap devices the processor to determine the swap device having high access availability) [KIM’s Par. 0081-0084; Par. 0134-0135].
With respect to claim 3, KIM and NAVON, combined the method wherein determining the target SWAP device from the at least two groups of SWAP devices based on the page access frequency information and the speed indication information (determining the swap device for swapping data among the plurality of the swap devices, based on the attributes of the data (access frequency) data having a high execution frequency) [KIM’s Par. 0081-0084] comprises: obtaining a partition parameter array that comprises the speed indication information of the at least two groups of SWAP devices (obtaining memory range accessed per unit time) [KIM’s Table 1; Par. 0081; Par. 0083]; and determining the target SWAP device from the at least two groups of SWAP devices based on the page access frequency information and the partition parameter array (the processor to determine, based on state information of each of the swap devices, and the state information of each of the swap devices may include at least one of a swap device available space, the swap device having high performance based on the attributes of the data and a type of each of the plurality of the swap devices) [KIM’s Par. 0107-0108; Par. 0081-0083; Par. 0134-0135].
With respect to claim 4, KIM and NAVON, combined the method wherein the speed indication information of the SWAP device comprises a frequency of the SWAP device, and the page access frequency information comprises a page access frequency; wherein determining the target SWAP device from the at least two groups of SWAP devices based on the page access frequency information and the partition parameter array (KIM’s Par. 0016 featuring the processor to determine: a swap device for swapping the data among the plurality of the swap devices based on the attributes of the data and the attributes of each of the plurality of the swap devices such that: if the data is data having a high execution frequency, the processor may determine a swap device having high performance as the swap device for swapping the data; if the data is optionally erasable data, the processor may determine a swap device having high access availability and a long lifespan as the swap device for swapping the data) [KIM’s Par. 0116-0117) comprises: selecting a frequency of a candidate SWAP device in the partition parameter array, wherein each frequency of the at least two groups of SWAP devices has at most one chance as the frequency of the candidate SWAP device; determining the candidate SWAP device as the target SWAP device, in a case that the page access frequency is greater than the frequency of the candidate SWAP device (based on attribute information, generating association information between the attributes of the data and the attributes of the at least one swap device, and determining the swap device may include determining a swap device for swapping the data from among the swap devices, based on the association information) [Par. 0157-0159]; and restarting selecting a frequency of a candidate SWAP device in the partition parameter array, in a case that the page access frequency is less than or equal to the frequency of the candidate SWAP device (process of changing the swap device for improving the data swapping performance based on system performance change where data attribute changes force a change of swapping device, where the processor calculates a swapping overhead value of each of the plurality of the swap devices where the processor to change (or redetermine) the swap device for swapping the data based on a swapping overhead value of each of the swap devices with respect to the data) [KIM’s Fig. 7-8; Par. 01Par. 0144-0148].
KIM teaches performance indicator change such that: if the performance indicator of the swap device attributes is greater than or equal to a designated value, the processor may determine that the ideal swap device has the high performance (high performance) attribute; if the lifespan indicator of the swap device attributes is equal to or greater than a designated value, the processor may determine that the ideal swap device has a long lifespan attribute [KIM’s Par. 0178-0179].
With respect to claim 5, KIM and NAVON, combined he method wherein the speed indication information of the SWAP device comprises: a frequency of the SWAP device and an age of the SWAP device; wherein the page access frequency information of the internal memory page comprises: a page access frequency and a frequency age (the processor to determine a swap device having high performance indicator as the swap device for swapping the data; if the data is optionally erasable data, the processor may determine a swap device having high access availability and a long lifespan as the swap device for swapping the data) [KIM’s Par. 0116-0117; Par. 0168-0170; Par. 0178-0179);
the processor to determine the swap device having high access availability and a long lifespan as the swap device for swapping the data. As still another example, if the data is data of a wide memory range (e.g., a great memory range accessed per unit time), the processor 230 may determine the swap device 210 having high performance and a long lifespan as the swap device 210 for swapping the data [KIM’s Par. 0081-0084].
With respect to claim 6, KIM and NAVON, combined the method wherein determining the target SWAP device from the at least two groups of SWAP devices based on the page access frequency information and the partition parameter array [the processor determining the swapping target, based on page attribute information (KIM’s Par. 0079-0084)] comprises: determining speed indication information of a candidate SWAP device in the partition parameter array, wherein the speed indication information of the at least two groups of SWAP devices has at most one chance as the speed indication information of the candidate SWAP device (processor to determine the swap device for swapping the data among the plurality of the swap devices, based on the attributes of the data and a type of each of the plurality of the swap devices, performance as the swap device for swapping the data) [KIM’s Par. 0081-0084]; determining the candidate SWAP device as the target SWAP device, in a case that the page access frequency is equal to the frequency of the candidate SWAP device and the frequency age is greater than or equal to an age of the candidate SWAP device (the processor to determine the swap device having high access availability and a long lifespan as the swap device for swapping the data) [KIM’s Par. 0081-0084].; and restarting determining speed indication information of a candidate SWAP device in the partition parameter array, in a case that the page access frequency is not equal to the frequency of the SWAP device and the frequency age is less than or equal to the age of the candidate SWAP device (process of changing the swap device for improving the data swapping performance based on system performance change where data attribute changes force a change of swapping device, where the processor calculates a swapping overhead value of each of the plurality of the swap devices where the processor to change (or redetermine) the swap device for swapping the data based on a swapping overhead value of each of the swap devices with respect to the data) [KIM’s Fig. 7-8; Par. 0167-0168; Par. 0131-0134].
With respect to claim 7, KIM and NAVON, combined the method, wherein the method further comprises: determining the target SWAP device based on priorities of the at least two groups of SWAP devices, in a case that the target SWAP device matching the page access frequency information is unable to be determined from the at least two groups of SWAP devices based on the page access frequency information, wherein the priority represents an order of selecting the target SWAP device from the at least two groups of SWAP devices (swap device for data swapping is selected from the plurality of the swap devices according to a priority set according to user setting or system setting or a free space size of a storage space where the processor classifies the selection process into one group of a plurality of groups (or classes) based on the attributes of the process, wherein, the processor compares attributes of each of the plurality of the groups with the attributes of the process to perform classification based on attributes of the process) [KIM’s Par. 0075-0079; Par. 0165-0169]; swap device for data swapping is selected from the plurality of the swap devices according to attributes with priority set: when plurality of groups having the identical attributes or attribute similarity over a designated size, the processor to generate (or recognize) the plurality of the swap devices, and set attributes (e.g., hardware properties) of each of the plurality of the swap devices, the attributes of the plurality of the swap devices to include at least one of the performance, the lifespan, the access availability, or the data integrity) [KIM’s Par. 0079-0081].
With respect to claim 8, KIM and NAVON, combined teach the method wherein the determining the target SWAP device based on priorities of the at least two groups of SWAP devices comprises: obtaining the priorities of the at least two groups of SWAP devices; and determining, from among SWAP devices with an idle capacity greater than a data amount of the content data stored in the internal memory page, a SWAP device with a highest priority as the target SWAP device in descending order of the priority, wherein the idle capacity represents available capacity in the SWAP device where content data is not stored (based on the data attributes (or the group attributes) and the attributes of each of the plurality of the swap devices, if identifying two or more swap devices for swapping the data (or data included in the group) among the plurality of the swap devices, the processor may apply the load balancing selecting any one of the first swap device and the second swap device identified, based on at least one of a currently available space or free space, or a data amount currently stored in each of the first swap device and the second swap device, selecting a swap device storing relatively less data among the first swap device and the second swap device; if the swap device lacks the currently available space or free space, stores considerable data, or is unavailable in connection, the processor may determine another swap device) KIM’s [Par. 0088-0089].
With respect to claim 9, KIM and NAVON, combined teach the method according to wherein the at least two groups of SWAP devices have buffer storage areas in the computer device; wherein transferring content data stored in the internal memory page to the target SWAP device comprises: caching the content data in a target buffer storage area, wherein the target buffer storage area is a buffer storage area that is configured for the target SWAP device; and transferring the content data from the internal memory to the target SWAP device, in a case that a total amount of content data that is stored in the target buffer storage area exceeds a cache capacity of the target buffer storage area (performance improvement denoting freeing up space to make available memory capacity if swapping the data using the swap device; using tuning parameters set to measure and estimate needed memory capacity if caching the data where the processor moved (or swap out) the data stored in the memory (or data included in the group) to the determined swap device and the processor moves (or swaps in) the data (or data included in the group) temporarily stored in the determined swap device to the memory) [KIM’s Par. 0095-0098; Par. 0015-0016].
With respect to claim 13, internal memory reclaiming apparatus, comprising: at least one memory configured to store computer program code; and at least one processor configured to read the program code and operate as instructed by the program code, the program code (electronic device (or a computing device) which performs data processing or operation may include a memory (e.g., a random access memory (RAM)) for storing data or instructions used by an executed application program, processor configured to execute the instructions) [Par. 0003] comprising: determining code configured to cause at least one of the at least one processor to determine page access frequency information of an internal memory page (instructions to, based on attributes of at least one swap device of the plurality of swap devices, generate association information between the attributes of the data and the attributes of the at least one swap device wherein attributes refers to an execution frequency of the data (based on data usage history information corresponding to each of the group), data integrity of the data in swapping, erasability of the data) [Par. 0008-0014; Par. 0074-0075] the mapping module 1113 may map the group and the swap device based on at least one of whether the UI is related, the execution frequency, the erasability, the memory range accessed per unit time, or the data integrity of the group attributes where the reclaim module to select (or determine), as the swapping target, at least one page having a low execution frequency (or the number of uses) or having the oldest last execution (or use) among the pages stored in the memory [Par. 0190-0193; Par. 0074-0075], and determine a target SWAP device from the at least two groups of SWAP devices based on the page access frequency information (identifying, as a swapping target, at least a portion of data included in each of the groups, based on data usage history information corresponding to each of the groups) [Par. 0019; Par. 0008-0020; Par. 0074-0075]; the processor to determine the swap device for swapping data among the plurality of the swap devices, based on the attributes of the data and the attributes of each of the plurality of the swap devices [Par. 0081-0083]; and transferring code configured to cause at least one of the at least one processor to transfer content data stored in the internal memory page to the target SWAP device (swapping the identified at least the portion of data using the swap device corresponding to each of the groups) [Par. 0019]; Par. 0008-0020; Par. 0074-0075; Par. 0134-0135].
KIM fails to specifically teach internal memory page to be reclaimed based on receiving an internal memory reclaiming instruction. However, NAVON teaches input/output (IO) interface to receives commands from the host where examples of storage commands include garbage collection (data relocation commands), read scrub (refreshing of data values stored in memory cells) commands [Par. 0059]; cache utilization manager that manages and/or tracks a set of cache utilization metrics for the cache entries where partition access frequency and cache access frequency are possible cache utilization metrics [Par. 0061}, cache swap manager to identify a cache eviction candidate where the cache eviction candidate defines a level that a cache utilization metric satisfied to be evicted from a mapping table cache [Par. 0062-0065]; If a cache eviction candidate has been modified since it was last loaded from the address mapping table, the cache manager directs the store module to modify the cache eviction candidate to the non-volatile memory [Par. 0083-0087]. Therefore it would have been obvious to one having at least ordinary skill in the art before the effective filing date of the instant application to modify the data swapping method including identifying swap data, taught by KIM by determining access frequency information of an internal memory page to be reclaimed based on receiving an internal memory reclaiming instruction, as taught by NAVON, in order to carry the swapping to a modified scored data entry for the retrieved entry that has been modified (e.g., accessed a predetermined number of times) preserving the previous cache eviction candidate , as taught by NAVON [Par. 0087-0089].
With respect to claim 14, KIM and NAVON, combined teach the apparatus wherein the determining code is further configured to cause at least one of the at least one processor to: obtain speed indication information of the at least two groups of SWAP devices, wherein the speed indication information represents an access speed of accessing content data from the SWAP device (processor to determine the swap device for swapping data among the plurality of the swap devices, based on the attributes of the data (access frequency) data having a high execution frequency) [KIM’s Par. 0081-0084]; and determine the target SWAP device based on the page access frequency information and the speed indication information, wherein the target SWAP device has a target access speed matching the page access frequency information(the processor to determine the swap device for swapping data among the plurality of the swap devices based on attributes of each of the plurality of the swap devices the processor to determine the swap device having high access availability) [KIM’s Par. 0081-0084; Par. 0134-0135].
With respect to claim 15, KIM and NAVON, combined teach the apparatus wherein the determining code is further configured to cause at least one of the at least one processor to: obtain a partition parameter array that comprises the speed indication information of the at least two groups of SWAP devices (determining the swap device for swapping data among the plurality of the swap devices, based on the attributes of the data (access frequency) data having a high execution frequency) [Par. 0081-0084]; obtaining memory range accessed per unit time) [Table 1; Par. 0081; Par. 0083]; and determine the target SWAP device based on the page access frequency information and the partition parameter array; and (the processor to determine, based on state information of each of the swap devices, and the state information of each of the swap devices may include at least one of a swap device available space, the swap device having high performance based on the attributes of the data and a type of each of the plurality of the swap devices) [KIM’s Par. 0107-0108; Par. 0081-0083; Par. 0134-0135].
With respect to claim 16, KIM and NAVON, combined teach the apparatus wherein the speed indication information of the SWAP device comprises a frequency of the SWAP device, and the page access frequency information comprises a page access frequency; wherein the determining code is further configured to cause at least one of the at least one processor to (Par. 0016 featuring the processor to determine: a swap device for swapping the data among the plurality of the swap devices based on the attributes of the data and the attributes of each of the plurality of the swap devices such that: if the data is data having a high execution frequency, the processor may determine a swap device having high performance as the swap device for swapping the data; if the data is optionally erasable data, the processor may determine a swap device having high access availability and a long lifespan as the swap device for swapping the data, KIM’s Par. 0116-0117): select a frequency of a candidate SWAP device in the partition parameter array, wherein each frequency of the at least two groups of SWAP devices has at most one chance as the frequency of the candidate SWAP device; determine the candidate SWAP device as the target SWAP device if the page access frequency is greater than the frequency of the candidate SWAP device (based on attribute information, generating association information between the attributes of the data and the attributes of the at least one swap device, and determining the swap device may include determining a swap device for swapping the data from among the swap devices, based on the association information) [KIM’s Par. 0157-0159]; and restart selecting a frequency of a candidate SWAP device in the partition parameter array if the page access frequency is less than or equal to the frequency of the candidate SWAP device (process of changing the swap device for improving the data swapping performance based on system performance change where data attribute changes force a change of swapping device, where the processor calculates a swapping overhead value of each of the plurality of the swap devices where the processor to change (or redetermine) the swap device for swapping the data based on a swapping overhead value of each of the swap devices with respect to the data) [KIM’s Fig. 7-8; Par. 01Par. 0144-0148].
With respect to claim 17, KIM and NAVON, combined teach the apparatus wherein the speed indication information of the SWAP device comprises a frequency of the SWAP device and an age of the SWAP device; wherein the page access frequency information of the internal memory page comprises a page access frequency and a frequency age (the processor to determine a swap device having high performance indicator as the swap device for swapping the data; if the data is optionally erasable data, the processor may determine a swap device having high access availability and a long lifespan as the swap device for swapping the data, [KIM’s Par. 0116-0117; Par. 0168-0170; Par. 0178-0179); the processor to determine the swap device having high access availability and a long lifespan as the swap device for swapping the data. As still another example, if the data is data of a wide memory range (e.g., a great memory range accessed per unit time), the processor 230 may determine the swap device 210 having high performance and a long lifespan as the swap device 210 for swapping the data [KIM’s Par. 0081-0084].
With respect to claim 18, KIM and NAVON, combined teach the apparatus wherein the determining code is further configured to cause at least one of the at least one processor to: determine speed indication information of a candidate SWAP device in the partition parameter array [the processor determining the swapping target, based on page attribute information (KIM’s Par. 0079-0084)], wherein the speed indication information of the at least two groups of SWAP devices has at most one chance as the speed indication information of the candidate SWAP device (processor to determine the swap device for swapping the data among the plurality of the swap devices, based on the attributes of the data and a type of each of the plurality of the swap devices, performance as the swap device for swapping the data) [KIM’s Par. 0081-0084]; determine the candidate SWAP device as the target SWAP device, in a case that the page access frequency is equal to the frequency of the candidate SWAP device and the frequency age is greater than or equal to an age of the candidate SWAP device (the processor to determine the swap device having high access availability and a long lifespan as the swap device for swapping the data) [KIM’s Par. 0081-0084]; and restart determining speed indication information of a candidate SWAP device in the partition parameter array, in a case that the page access frequency is not equal to the frequency of the SWAP device and the frequency age is less than or equal to the age of the candidate SWAP device (process of changing the swap device for improving the data swapping performance based on system performance change where data attribute changes force a change of swapping device, where the processor calculates a swapping overhead value of each of the plurality of the swap devices where the processor to change (or redetermine) the swap device for swapping the data based on a swapping overhead value of each of the swap devices with respect to the data) [KIM’s Fig. 7-8; Par. 0167-0168; Par. 0131-0134].
With respect to claim 19, KIM and NAVON, combined teach the apparatus wherein the determining code is further configured to cause at least one of the at least one processor to: determine the target SWAP device based on priorities of the at least two groups of SWAP devices, in a case that the target SWAP device matching the page access frequency information is unable to be determined from the at least two groups of SWAP devices based on the page access frequency information, wherein the priority represents an order of selecting the target SWAP device from the at least two groups of SWAP devices (swap device for data swapping is selected from the plurality of the swap devices according to a priority set according to user setting or system setting or a free space size of a storage space where the processor classifies process into one group of a plurality of groups (or classes) based on the attributes of the process, wherein, the processor compares attributes of each of the plurality of the groups with the attributes of the process where the processor to perform classification based on attributes of the process) [KIM’s Par. 0075-0079; Par. 0165-0169].
.
With respect to claim 20, KIM and NAVON, combined non-transitory computer-readable storage medium, storing computer code which, when executed by at least one processor, causes the at least one processor to execute the internal memory reclaiming method, as addressed above.
Allowable Subject Matter
Claims 10-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20220398014 A1 (AMARO et al) teaches memory segmented or subdivided into one or more blocks of memory, which are represented as pages , portions of memory can be stored to the swap device by writing one or more pages to the swap device to make those pages of memory available.
US 20210157646 A1 (YUDANOV et al) teaching enhancement or reduction of page migration to include operations that include scoring, in a computing device, each executable of at least a first group and a second group of executables in the computing device.
DE 112020002526 T5 (PLETKA et al) teaching computer-implemented method including: maintaining a block switch metric for each memory block in the memory system, according to a block swap metric corresponding to the first block, determining whether a first block in a first pool should be transferred to a second pool; in response to determining that the first block in the first pool should be transferred to the second pool according to the block swap metric corresponding to the first block, the first block is deleted, the first block is then transferred from the first pool to a second RTU queue corresponding to the second pool.
US 20210034286 A1 (CHUNG et al) teaching memory system may include a plurality of layers coupled through at least one through silicon via (TSV) channel and a swap controller configured to generate a swap control command in response to a request received from an external host and to device swap data into a plurality of data units having a predetermined size to perform a swap operation between a first layer and a second layer among the plurality of layers, wherein the first layer and the second layer include at least one swap buffer and control a movement of the plurality of data units in response to the swap control command.
US 10698837 B2 (FANG et al) teaching method includes acquiring reclaimable memory pages occupied by an application to be processed; acquiring an idle duration of the application to be processed for each reclaimable memory page; determining a duration threshold according to the idle durations for the reclaimable memory pages; and selecting from the reclaimable memory pages a memory page for which the idle duration exceeds the duration threshold and reclaiming the memory page. The above-mentioned method for processing a memory and apparatus, electronic device and computer-readable storage medium may minimize the adverse impact on each application, thereby maintaining the balance between reclaiming and operation of an application memory to be processed.
US 20190220418 A1 (CHEN et al) teaching method includes determining a memory page that needs to be swapped out of a memory, for each memory page that needs to be swapped out, generating, based on the memory page, a work task reclaiming the memory page, and allocating each work task to a dedicated worker thread for execution. In this way, a plurality of central processing units (CPUs) process memory reclaiming in parallel, thereby accelerating memory reclaiming, and improving user experience.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PIERRE MICHEL BATAILLE whose telephone number is (571)272-4178. The examiner can normally be reached Monday - Thursday 7-6 ET.
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/PIERRE MICHEL BATAILLE/Primary Examiner, Art Unit 2138
Prosecution Insights