Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/17/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9 and 11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 9, it is based off of the independent claim 8 that recites limitations that outline a process for determining how the received data should be written back to the memory location based on the status of various bits. The steps include choosing which specific bits to check and what condition they need to meet in order to make that determination; if all of the conditions are met, then the method ends by “inverting values of the received data and writing the inverted values of the received data to the memory location” (Claim 8). The first step in that process is performed “upon determining that one or more of the bits at the memory location remain in the first state…” (Claim 8), and the process continues onward until it reaches the final step. In reference to that first step of the process, Claim 9 recites the limitation “upon determining that one or more of the bits at the memory location do not remain in the first state, writing the received data to the memory location”. This step creates a conflict with Claim 8 because there could be a case where both conditions are met: one where “one or more of the bits at the memory location remain in the first state” (Claim 8) and also one where “one or more of the bits at the memory location do not remain in the first state” (Claim 9). For example, in an 8-bit data word, there could be a case where there are 2 bits that remain in the first state, and the rest of the bits do not remain in the first state. No details are given on how this overlap should be handled, specifically whether the received data should be inverted or not when being written back to the memory. The examiner has interpreted Claim 9 as the case where all of the bits at the memory location do not remain in the first state, meaning that none of the bits remain in the first state and thus, does not meet the condition of Claim 8. The examiner suggests that the claim be rewritten to reflect this condition, or that more limitations/steps are provided to handle the case where multiple bits meet the conditions of Claims 8 and 9.
Regarding Claim 11, it is also based off of the independent claim 8, and it is rejected using a similar reasoning for Claim 9 above. In this case, Claim 8 recites the limitation in the process “upon determining that one or more of the bits at the memory location that remain in the first state do not correspond to the state of the received data…”, and in reference to that step, Claim 11 recites “upon determining that one or more of the bits at the memory location that remain in the first state correspond to the state of the received data, writing the received data to the memory location”. As explained previously, the process of Claim 8 ends by inverting the bits and writing it to the memory location, and because Claim 11 doesn’t invert the bits and writes the received data to the memory, this creates an overlapping conflict because there could be a case where at least one bit meets the condition for both claims. The examiner has interpreted Claim 11 as the case where all of the bits at the memory location that remain in the first state do correspond to the state of the received data, meaning that none of the bits that remain in the first state don’t correspond to the state of the received data and thus, does not meet the condition of Claim 8. The examiner suggests that the claim be rewritten to reflect this condition, or that more limitations/steps are provided to handle the case where multiple bits meet the conditions of Claims 8 and 11.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al., hereafter referred to as Lee, US Pub. No. US 11625188 B2, in view of Park, US Pub. No. US 20240232003 A1.
Regarding Claim 1, Lee teaches a method comprising:
receiving data [“ The controller may be configured to receive a second data, which is a verify read from the resistive memory cell programmed with the first data, from the first nonvolatile memory in response to the first program command.”] (Column 1, Lines 50 - 54);
reading respective values of the bits at the memory location ["The nonvolatile memory 200 may perform the read operation (S343). In some example embodiments, the nonvolatile memory 200 may perform the read operation on the basis of the provided read command read CMD and address ADDR. A read voltage may be applied to the bit line BL connected to the memory cell MC to read the result thereof."] (Column 12, Lines 16 - 21);
determining an error correction based on the respective values ["The controller 100 may detect fail cells using the provided verify read result (S303). In some example embodiments, the inversion module 110 included in the controller 100 may detect fail cells using the transferred second data D2. Thus, the inversion module 110 may detect the number of bits having different logical values, by comparing the second data D2 with the first data D1. In some example embodiments, when the logical value of the specific bit of the first data D1 is ‘0’ and the logical value of the corresponding bit of the second data D2 is ‘1’, the inversion module 110 may detect the corresponding memory cell MC as a fail cell.
Referring to FIG. 8 again, the controller 100 may determine whether the number of detected fail cells is greater than a reference value, e.g., a reference number or positive integer (S304). In some example embodiments, the inversion module 110 of the controller 100 may determine whether the number of fail cells of the detected memory cells MC is greater than the reference value. ."] (Paragraphs 75 and 78);
and writing the received data to the memory location as received data or inverted data, based on the error correction [“In some example embodiments, the read/write circuit 240 may program the received data in the memory cell array 210. […] When the number of fail cells is equal to or less than the reference value (S304—NO), the process may end.”] (Column 5, Lines 56 – 59, and Column 9, Lines 13 – 14), [“In some example embodiments, when the number of fail cells is greater than the reference value (S304—YES), the controller 100 may inverse the first data D1 to generate the third data D3 (S306) [...] In some example embodiments, every bit of the first data D1 may be the inverse in corresponding bit locations in the third data D3. The third data D3 may be programmed in the memory cell(s) MC (S307). In some example embodiments, the third data D3 obtained by inversing the first data D1 may be programmed in the memory cell(s) MC…”] (Column 9, Lines 22 - 36).
However, Lee and Park do not teach a method of correcting one or more errors in a memory device, the method performed by one or more controllers and comprising: writing bits at a memory location to a first state. Park, in an analogous art, teaches a method of correcting one or more errors in a memory device, the method performed by one or more controllers [“According to an embodiment of the present disclosure, an operating method of a controller includes controlling a memory device to store therein a data chunk and a corresponding error correction code (ECC)…”] (Paragraph 7) and comprising:
writing bits at a memory location to a first state [“The bit included in the data 310 may be stored in a corresponding memory cell among the plurality of memory cells included in the memory device 200. Specifically, the memory device 200 may perform the write operation of programming the memory cell to have a program state corresponding to a bit-value. For example, when the memory device 200 performs the write operation using the SLC method, the memory cell may be programmed to have a first program state to store the first bit-value…”] (Paragraph 34). Lee and Park are considered to be analogous art because they’re in the same field of reading from and writing to memory based on an error correction/detection scheme.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Park with the teachings of Lee and Park, and add a step to write the respective value of the bits to a first state within the method performed by a memory controller. This modification would have been obvious because a person of ordinary skill in the art would have been motivated to use a memory controller so that they can operate the memory device to write or output data [“The memory controller 100 may control an operation of the memory device 200. The memory device 200 may store data or output stored data under the control of the memory controller 100.”], and they would have been motivated to set the value of the bits to a first state to indicate the initial status of the bit. For example, “the first program state may mean that a threshold voltage of the memory cell is lower than a reference level…” (Park, Paragraph 34).
Claims 2 - 6, 8 - 11, and 14 - 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee and Park as applied to claim 1 above, and further in view of Andre et al., hereafter referred to as Andre, US Pub. No. US 20190156878 A1.
Regarding Claim 2, Lee and Park teach all of the recited limitations in the independent Claim 1 as explained previously, and Lee also teaches determining whether one or more inversion bits for the memory location are in the second state ["In FIG. 10, although fail bits are detected only for data bits, fail bits may also be detected for the inversion flag bit or the ECC parity bit."] (Column 9, Lines 3 - 5), and determining whether one or more of the bits at the memory location that are in the second state correspond to a state of the received data ["Thus, the inversion module 110 may detect the number of bits having different logical values, by comparing the second data D2 with the first data D1. In some example embodiments, when the logical value of the specific bit of the first data D1 is ‘0’ and the logical value of the corresponding bit of the second data D2 is ‘1’, the inversion module 110 may detect the corresponding memory cell MC as a fail cell."].
However, Lee and Park do teach determining whether one or more of the bits at the memory location are in a second state different from the first state. Andre, in an analogous art, teaches determining whether one or more of the bits at the memory location are in a second state different from the first state ["With respect to the first set of bits, the memory device may be configured to apply a first up voltage across the tunnel junctions of the bit cells of the first set of bit cells to set at least a portion of the first set of bit cells to the high resistive state. The memory device may then evaluate the state of the first set of bit cells (for example, via a referenced read operation) to identify a first subset of the first set of bit cells remaining in the low resistive state."] (Paragraph 21). Lee, Park, and Andre are considered to be analogous art because they’re in the same field of reading from and writing to memory based on an error correction/detection scheme.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Andre with the teachings of Lee and Park, and add a step to check if the bits are in a first or second state different from the original state in the memory location (not comparing with the received data). This modification would have been obvious because a person of ordinary skill in the art would have been motivated to check if a bit is in a first or second state different from the original state to detect if an error has happened in the memory cell itself and address the error if needed. This would allow memory devices, like those that use magnetic tunnel junctions for example, to be “able to reduce the risk and speed at which at least some the MTJs are broken down or shorted, thereby extending the usable life of the device” (Andre, Paragraphs 21 & 22).
Regarding Claim 3, Lee and Park teach all of the recited limitations in the independent Claim 1 as explained previously, and Lee also teaches writing the received data to the memory location as the received data [“In some example embodiments, the read/write circuit 240 may program the received data in the memory cell array 210.”] (Column 5, Lines 56 - 59) based on the determination of the error in the bits [“When the number of fail cells is equal to or less than the reference value (S304—NO), the process may end.”] (Column 9, Lines 33 - 36).
However, Lee and Park do not teach the actual error determination being based on checking whether none of the bits at the memory location are in a second state different from the first state. Andre, in an analogous art, teaches determining that none of the bits at the memory location are in a second state different from the first state; ["With respect to the first set of bits, the memory device may be configured to apply a first up voltage across the tunnel junctions of the bit cells of the first set of bit cells to set at least a portion of the first set of bit cells to the high resistive state. The memory device may then evaluate the state of the first set of bit cells (for example, via a referenced read operation) to identify a first subset of the first set of bit cells remaining in the low resistive state."] (Paragraph 21). Lee, Park, and Andre are considered to be analogous art because they’re in the same field of reading from and writing to memory based on an error correction/detection scheme.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Andre with the teachings of Lee and Park, and add a step to check if the bits are in a first or second state different from the original state in the memory location (not comparing with the received data). This modification would have been obvious because a person of ordinary skill in the art would have been motivated to check if a bit is in a first or second state different from the original state to detect if an error has happened in the memory cell itself and address the error if needed. This would allow memory devices, like those that use magnetic tunnel junctions for example, to be “able to reduce the risk and speed at which at least some the MTJs are broken down or shorted, thereby extending the usable life of the device” (Andre, Paragraphs 21 & 22).
Regarding Claim 4, Lee and Park teach all of the recited limitations in the independent Claim 1 as explained previously, and Lee also teaches determining whether no inversion bits for the memory location are in the second state ["In FIG. 10, although fail bits are detected only for data bits, fail bits may also be detected for the inversion flag bit or the ECC parity bit."] (Column 9, Lines 3 - 5), and writing the received data to the memory location as the inverted data ["In some example embodiments, when the number of fail cells is greater than the reference value (S304—YES), the controller 100 may inverse the first data D1 to generate the third data D3 (S306) [...] In some example embodiments, every bit of the first data D1 may be the inverse in corresponding bit locations in the third data D3. The third data D3 may be programmed in the memory cell(s) MC (S307). In some example embodiments, the third data D3 obtained by inversing the first data D1 may be programmed in the memory cell(s) MC…"] (Column 9, Lines 22 - 36).
However, Lee and Park do not teach the actual error determination also being based on checking whether one or more of the bits at the memory location are in a second state different from the first state. Andre, in an analogous art, teaches determining whether one or more of the bits at the memory location are in a second state different from the first state ["With respect to the first set of bits, the memory device may be configured to apply a first up voltage across the tunnel junctions of the bit cells of the first set of bit cells to set at least a portion of the first set of bit cells to the high resistive state. The memory device may then evaluate the state of the first set of bit cells (for example, via a referenced read operation) to identify a first subset of the first set of bit cells remaining in the low resistive state."] (Paragraph 21). Lee, Park, and Andre are considered to be analogous art because they’re in the same field of reading from and writing to memory based on an error correction/detection scheme.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Andre with the teachings of Lee and Park, and add a step to check if the bits are in a first or second state different from the original state in the memory location (not comparing with the received data). This modification would have been obvious because a person of ordinary skill in the art would have been motivated to check if a bit is in a first or second state different from the original state to detect if an error has happened in the memory cell itself and address the error if needed. This would allow memory devices, like those that use magnetic tunnel junctions for example, to be “able to reduce the risk and speed at which at least some the MTJs are broken down or shorted, thereby extending the usable life of the device” (Andre, Paragraphs 21 & 22).
Regarding Claim 5, Lee and Park teach all of the recited limitations in the independent Claim 1 as explained previously, and Lee also teaches determining whether no inversion bits for the memory location are in the second state ["In FIG. 10, although fail bits are detected only for data bits, fail bits may also be detected for the inversion flag bit or the ECC parity bit."] (Column 9, Lines 3 - 5), determining whether one or more of the bits at the memory location that are in the second state correspond to a state of the received data ["Thus, the inversion module 110 may detect the number of bits having different logical values, by comparing the second data D2 with the first data D1. In some example embodiments, when the logical value of the specific bit of the first data D1 is ‘0’ and the logical value of the corresponding bit of the second data D2 is ‘1’, the inversion module 110 may detect the corresponding memory cell MC as a fail cell."] (Column 8, Lines 55 - 62), and writing the received data to the memory location as the received data [“In some example embodiments, the read/write circuit 240 may program the received data in the memory cell array 210.”] (Column 5, Lines 56 - 59) based on the determination of the error in the bits [“When the number of fail cells is equal to or less than the reference value (S304—NO), the process may end.”] (Column 9, Lines 13 - 14).
However, Lee and Park do not teach the actual error determination also being based on checking whether one or more of the bits at the memory location are in a second state different from the first state. Andre, in an analogous art, teaches determining whether one or more of the bits at the memory location are in a second state different from the first state ["With respect to the first set of bits, the memory device may be configured to apply a first up voltage across the tunnel junctions of the bit cells of the first set of bit cells to set at least a portion of the first set of bit cells to the high resistive state. The memory device may then evaluate the state of the first set of bit cells (for example, via a referenced read operation) to identify a first subset of the first set of bit cells remaining in the low resistive state."] (Paragraph 21). Lee, Park, and Andre are considered to be analogous art because they’re in the same field of reading from and writing to memory based on an error correction/detection scheme.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Andre with the teachings of Lee and Park, and add a step to check if the bits are in a first or second state different from the original state in the memory location (not comparing with the received data). This modification would have been obvious because a person of ordinary skill in the art would have been motivated to check if a bit is in a first or second state different from the original state to detect if an error has happened in the memory cell itself and address the error if needed. This would allow memory devices, like those that use magnetic tunnel junctions for example, to be “able to reduce the risk and speed at which at least some the MTJs are broken down or shorted, thereby extending the usable life of the device” (Andre, Paragraphs 21 & 22).
Regarding Claim 6, Lee and Park teach all of the recited limitations in the independent Claim 1 as explained previously, and Lee also teaches determining whether no inversion bits for the memory location are in the second state ["In FIG. 10, although fail bits are detected only for data bits, fail bits may also be detected for the inversion flag bit or the ECC parity bit."] (Column 9, Lines 3 - 5), determining that none of the bits at the memory location that are in the second state correspond to a state of the received data ["Thus, the inversion module 110 may detect the number of bits having different logical values, by comparing the second data D2 with the first data D1. In some example embodiments, when the logical value of the specific bit of the first data D1 is ‘0’ and the logical value of the corresponding bit of the second data D2 is ‘1’, the inversion module 110 may detect the corresponding memory cell MC as a fail cell."] (Column 8, Lines 55 - 62), and writing the received data to the memory location as the inverted data ["In some example embodiments, when the number of fail cells is greater than the reference value (S304—YES), the controller 100 may inverse the first data D1 to generate the third data D3 (S306) [...] In some example embodiments, every bit of the first data D1 may be the inverse in corresponding bit locations in the third data D3. The third data D3 may be programmed in the memory cell(s) MC (S307). In some example embodiments, the third data D3 obtained by inversing the first data D1 may be programmed in the memory cell(s) MC…"] (Column 9, Lines 22 - 36).
However, Lee and Park do not teach the actual error determination also being based on checking whether one or more of the bits at the memory location are in a second state different from the first state. Andre, in an analogous art, teaches determining whether one or more of the bits at the memory location are in a second state different from the first state ["With respect to the first set of bits, the memory device may be configured to apply a first up voltage across the tunnel junctions of the bit cells of the first set of bit cells to set at least a portion of the first set of bit cells to the high resistive state. The memory device may then evaluate the state of the first set of bit cells (for example, via a referenced read operation) to identify a first subset of the first set of bit cells remaining in the low resistive state."] (Paragraph 21). Lee, Park, and Andre are considered to be analogous art because they’re in the same field of reading from and writing to memory based on an error correction/detection scheme.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Andre with the teachings of Lee and Park, and add a step to check if the bits are in a first or second state different from the original state in the memory location (not comparing with the received data). This modification would have been obvious because a person of ordinary skill in the art would have been motivated to check if a bit is in a first or second state different from the original state to detect if an error has happened in the memory cell itself and address the error if needed. This would allow memory devices, like those that use magnetic tunnel junctions for example, to be “able to reduce the risk and speed at which at least some the MTJs are broken down or shorted, thereby extending the usable life of the device” (Andre, Paragraphs 21 & 22).
Regarding Claim 8, Lee teaches a method and comprising:
receiving data ["The controller may be configured to receive a second data, which is a verify read from the resistive memory cell programmed with the first data, from the first nonvolatile memory in response to the first program command."] (Column 1, Lines 50 - 54);upon determining that one or more of the bits at the memory location remain in the first state, determining whether one or more inversion bits for the memory location remain in the first state ["In FIG. 10, although fail bits are detected only for data bits, fail bits may also be detected for the inversion flag bit or the ECC parity bit."] (Column 9, Lines 3 - 5);
upon determining that no inversion bits for the memory location remain in the first state, determining whether one or more of the bits at the memory location that remain in the first state correspond to a state of the received data at a corresponding bit location ["Thus, the inversion module 110 may detect the number of bits having different logical values, by comparing the second data D2 with the first data D1. In some example embodiments, when the logical value of the specific bit of the first data D1 is ‘0’ and the logical value of the corresponding bit of the second data D2 is ‘1’, the inversion module 110 may detect the corresponding memory cell MC as a fail cell."] (Column 8, Lines 55 - 62);
upon determining that one or more of the bits at the memory location that remain in the first state do not correspond to the state of the received data at the corresponding bit location, inverting values of the received data and writing the inverted values of the received data to the memory location ["In some example embodiments, when the number of fail cells is greater than the reference value (S304—YES), the controller 100 may inverse the first data D1 to generate the third data D3 (S306) [...] In some example embodiments, every bit of the first data D1 may be the inverse in corresponding bit locations in the third data D3. The third data D3 may be programmed in the memory cell(s) MC (S307). In some example embodiments, the third data D3 obtained by inversing the first data D1 may be programmed in the memory cell(s) MC…"] (Column 9, Lines 22 - 36).
Park teaches a method of correcting one or more errors in a memory device, the method performed by one or more controllers [“According to an embodiment of the present disclosure, an operating method of a controller includes controlling a memory device to store therein a data chunk and a corresponding error correction code (ECC)…”] (Paragraph 7) and comprising:
writing bits at a memory location to a first state [“The bit included in the data 310 may be stored in a corresponding memory cell among the plurality of memory cells included in the memory device 200. Specifically, the memory device 200 may perform the write operation of programming the memory cell to have a program state corresponding to a bit-value. For example, when the memory device 200 performs the write operation using the SLC method, the memory cell may be programmed to have a first program state to store the first bit-value…”] (Paragraph 34).
However, Lee and Park do not teach the first step of the process of determining whether one or more of the bits at the memory location remain in the first state. Andre, in an analogous art, teaches determining whether one or more of the bits at the memory location remain in the first state ["With respect to the first set of bits, the memory device may be configured to apply a first up voltage across the tunnel junctions of the bit cells of the first set of bit cells to set at least a portion of the first set of bit cells to the high resistive state. The memory device may then evaluate the state of the first set of bit cells (for example, via a referenced read operation) to identify a first subset of the first set of bit cells remaining in the low resistive state."] (Paragraph 21). Lee, Park, and Andre are considered to be analogous art because they’re in the same field of reading from and writing to memory based on an error correction/detection scheme.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Andre with the teachings of Lee and Park, and Park and add a step to check if the bits are in a first or second state different from the original state in the memory location (not comparing with the received data). This modification would have been obvious because a person of ordinary skill in the art would have been motivated to check if a bit is in a first or second state different from the original state to detect if an error has happened in the memory cell itself and address the error if needed. This would allow memory devices, like those that use magnetic tunnel junctions for example, to be “able to reduce the risk and speed at which at least some the MTJs are broken down or shorted, thereby extending the usable life of the device” (Andre, Paragraphs 21 & 22).
Regarding Claim 9, Lee, Park, and Andre teach all of the recited limitations in the independent Claim 8 as explained previously. Lee also teaches writing the received data to the memory location [“In some example embodiments, the read/write circuit 240 may program the received data in the memory cell array 210.”] (Column 5, Lines 56 - 69) based on the determination of the error in the bits [“When the number of fail cells is equal to or less than the reference value (S304—NO), the process may end.”] (Column 9, Lines 13 - 14).
However, Lee and Park do not teach the actual error determination being based on checking whether one or more of the bits at the memory location do not remain in the first state. Andre, in an analogous art, teaches determining that one or more of the bits at the memory location do not remain in the first state ["With respect to the first set of bits, the memory device may be configured to apply a first up voltage across the tunnel junctions of the bit cells of the first set of bit cells to set at least a portion of the first set of bit cells to the high resistive state. The memory device may then evaluate the state of the first set of bit cells (for example, via a referenced read operation) to identify a first subset of the first set of bit cells remaining in the low resistive state."] (Paragraph 21). Lee, Park, and Andre are considered to be analogous art because they’re in the same field of reading from and writing to memory based on an error correction/detection scheme.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Andre with the teachings of Lee and Park, and add a step to check if the bits are in a first or second state different from the original state in the memory location (not comparing with the received data). This modification would have been obvious because a person of ordinary skill in the art would have been motivated to check if a bit is in a first or second state different from the original state to detect if an error has happened in the memory cell itself and address the error if needed. This would allow memory devices, like those that use magnetic tunnel junctions for example, to be “able to reduce the risk and speed at which at least some the MTJs are broken down or shorted, thereby extending the usable life of the device” (Andre, Paragraphs 21 & 22).
Regarding Claim 10, Lee, Park, and Andre teach all of the recited limitations in the independent Claim 8 as explained previously. Lee also teaches using the inversion bits for error determination ["In FIG. 10, although fail bits are detected only for data bits, fail bits may also be detected for the inversion flag bit or the ECC parity bit."] (Column 9, Lines 3 - 5), and inverting values of the received data, and writing the inverted values of the received data to the memory location ["In some example embodiments, when the number of fail cells is greater than the reference value (S304—YES), the controller 100 may inverse the first data D1 to generate the third data D3 (S306) [...] In some example embodiments, every bit of the first data D1 may be the inverse in corresponding bit locations in the third data D3. The third data D3 may be programmed in the memory cell(s) MC (S307). In some example embodiments, the third data D3 obtained by inversing the first data D1 may be programmed in the memory cell(s) MC…"] (Column 9, Lines 22 - 36).
However, Lee and Park do not teach the actual error determination being based on whether one or more inversion bits for the memory location remain in the first state. Andre, in an analogous art, teaches determining that one or more inversion bits for the memory location remain in the first state ["With respect to the first set of bits, the memory device may be configured to apply a first up voltage across the tunnel junctions of the bit cells of the first set of bit cells to set at least a portion of the first set of bit cells to the high resistive state. The memory device may then evaluate the state of the first set of bit cells (for example, via a referenced read operation) to identify a first subset of the first set of bit cells remaining in the low resistive state."] (Paragraph 21). Lee, Park, and Andre are considered to be analogous art because they’re in the same field of reading from and writing to memory based on an error correction/detection scheme.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Andre with the teachings of Lee and Park, and add a step to check if the bits are in a first or second state different from the original state in the memory location (not comparing with the received data). This modification would have been obvious because a person of ordinary skill in the art would have been motivated to check if a bit is in a first or second state different from the original state to detect if an error has happened in the memory cell itself and address the error if needed. This would allow memory devices, like those that use magnetic tunnel junctions for example, to be “able to reduce the risk and speed at which at least some the MTJs are broken down or shorted, thereby extending the usable life of the device” (Andre, Paragraphs 21 & 22).
Regarding Claim 11, Lee, Park, and Andre teach all of the recited limitations in the independent Claim 8 as explained previously. Lee also teaches upon determining that one or more of the bits at the memory location that remain in the first state correspond to the state of the received data ["Thus, the inversion module 110 may detect the number of bits having different logical values, by comparing the second data D2 with the first data D1. In some example embodiments, when the logical value of the specific bit of the first data D1 is ‘0’ and the logical value of the corresponding bit of the second data D2 is ‘1’, the inversion module 110 may detect the corresponding memory cell MC as a fail cell."] (Column 8, Lines 55 - 62), and writing the received data to the memory location [“In some example embodiments, the read/write circuit 240 may program the received data in the memory cell array 210.”] (Column 5, Lines 56 - 59) based on that determination [“When the number of fail cells is equal to or less than the reference value (S304—NO), the process may end.”] (Column 9, Lines 13 - 14).
Regarding Claim 14, Lee teaches a method) and comprising:
receiving data ["The controller may be configured to receive a second data, which is a verify read from the resistive memory cell programmed with the first data, from the first nonvolatile memory in response to the first program command."] (Column 1, Lines 50 - 56);and writing the received data to the memory location as received data or inverted data in response to determining the one or more bits at the memory location remain in the second state [“In some example embodiments, the read/write circuit 240 may program the received data in the memory cell array 210. […] When the number of fail cells is equal to or less than the reference value (S304—NO), the process may end.”] (Column 5, Lines 56 – 59, and Column 9, Lines 13 – 14), [“In some example embodiments, when the number of fail cells is greater than the reference value (S304—YES), the controller 100 may inverse the first data D1 to generate the third data D3 (S306) [...] In some example embodiments, every bit of the first data D1 may be the inverse in corresponding bit locations in the third data D3. The third data D3 may be programmed in the memory cell(s) MC (S307). In some example embodiments, the third data D3 obtained by inversing the first data D1 may be programmed in the memory cell(s) MC…”] (Column 9, Lines 22 - 36).
Park teaches a method of correcting one or more errors in a memory device, the method performed by one or more controllers [“According to an embodiment of the present disclosure, an operating method of a controller includes controlling a memory device to store therein a data chunk and a corresponding error correction code (ECC)…”] (Paragraph 7) and comprising:
writing bits at a memory location to a first state [“The bit included in the data 310 may be stored in a corresponding memory cell among the plurality of memory cells included in the memory device 200. Specifically, the memory device 200 may perform the write operation of programming the memory cell to have a program state corresponding to a bit-value. For example, when the memory device 200 performs the write operation using the SLC method, the memory cell may be programmed to have a first program state to store the first bit-value…”] (Paragraph 34).
However, Lee and Park do not teach determining whether one or more of the bits at the memory location remain in a second state different from the first state as part of the process. Andre, in an analogous art, teaches determining whether one or more of the bits at the memory location remain in a second state different from the first state ["With respect to the second set of bits, the memory device may be configured to apply a first down voltage across the tunnel junctions of the bit cells of the second set of bit cells to set at least a portion of the second set of bit cells to the low resistive state. The memory device may then evaluate the state of the second set of bit cells (for example, via a referenced read operation) to identify a second subset of the second set of bit cells remaining in the high resistive state."] (Paragraph 22). Lee, Park, and Andre are considered to be analogous art because they’re in the same field of reading from and writing to memory based on an error correction/detection scheme.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Andre with the teachings of Lee and Park, and add a step to check if the bits are in a first or second state different from the original state in the memory location (not comparing with the received data). This modification would have been obvious because a person of ordinary skill in the art would have been motivated to check if a bit is in a first or second state different from the original state to detect if an error has happened in the memory cell itself and address the error if needed. This would allow memory devices, like those that use magnetic tunnel junctions for example, to be “able to reduce the risk and speed at which at least some the MTJs are broken down or shorted, thereby extending the usable life of the device” (Andre, Paragraphs 21 & 22).
Regarding Claim 15, Lee, Park, and Andre teach all of the recited limitations in the independent Claim 14 as explained previously. Lee also teaches writing the received data to the memory location, which includes writing the one or more of the bits as the received data [“In some example embodiments, the read/write circuit 240 may program the received data in the memory cell array 210.”] (Column 5, Lines 56 - 69) based on the determination of the error in the bits [“When the number of fail cells is equal to or less than the reference value (S304—NO), the process may end.”] (Column 9, Lines 13 - 14).
However, Lee and Park do not teach the actual error determination being based on checking whether one or more of the bits at the memory location do not remain in the second state. Andre, in an analogous art, teaches determining that one or more of the bits at the memory location do not remain in the second state ["With respect to the second set of bits, the memory device may be configured to apply a first down voltage across the tunnel junctions of the bit cells of the second set of bit cells to set at least a portion of the second set of bit cells to the low resistive state. The memory device may then evaluate the state of the second set of bit cells (for example, via a referenced read operation) to identify a second subset of the second set of bit cells remaining in the high resistive state."] (Paragraph 22). Lee, Park, and Andre are considered to be analogous art because they’re in the same field of reading from and writing to memory based on an error correction/detection scheme.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Andre with the teachings of Lee and Park, and add a step to check if the bits are in a first or second state different from the original state in the memory location (not comparing with the received data). This modification would have been obvious because a person of ordinary skill in the art would have been motivated to check if a bit is in a first or second state different from the original state to detect if an error has happened in the memory cell itself and address the error if needed. This would allow memory devices, like those that use magnetic tunnel junctions for example, to be “able to reduce the risk and speed at which at least some the MTJs are broken down or shorted, thereby extending the usable life of the device” (Andre, Paragraphs 21 & 22).
Regarding Claim 16, Lee, Park, and Andre teach all of the recited limitations in the independent Claim 14 as explained previously. However, Lee and Park do not teach determining that one or more of the bits at the memory location remain in the second state, and determining whether the one or more bits at the memory location that remain in the second state include an inversion bit for the memory location.
Andre, in an analogous art, teaches determining that one or more of the bits at the memory location remain in the second state ["With respect to the second set of bits, the memory device may be configured to apply a first down voltage across the tunnel junctions of the bit cells of the second set of bit cells to set at least a portion of the second set of bit cells to the low resistive state. The memory device may then evaluate the state of the second set of bit cells (for example, via a referenced read operation) to identify a second subset of the second set of bit cells remaining in the high resistive state."] (Paragraph 22), and determining whether the one or more bits at the memory location that remain in the second state include an inversion bit for the memory location ["For example, if the minority state is the low resistive state, the data 402 is stored and one or more inversion bits are not set. However, if the minority state is the high resistive state, the data 402 is inverted before storing and the one or more inversion bits are set."] (Paragraph 68). Lee, Park, and Andre are considered to be analogous art because they’re in the same field of reading from and writing to memory based on an error correction/detection scheme.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Andre with the teachings of Lee and Park, and add a step to check if the bits are in a first or second state different from the original state in the memory location (not comparing with the received data) and determining whether there’s an inversion bit included to adjust the error detection. This modification would have been obvious because a person of ordinary skill in the art would have been motivated to check if a bit is in a first or second state different from the original state along with checking if inversion bits are present to detect if an error has happened in the memory cell itself and address the error if needed. This would allow memory devices, like those that use magnetic tunnel junctions for example, to be “able to reduce the risk and speed at which at least some the MTJs are broken down or shorted, thereby extending the usable life of the device” (Andre, Paragraphs 21 & 22).
Regarding Claim 17, Lee, Park, and Andre teach all of the recited limitations in the independent Claim 14 as explained previously. Lee also teaches determining that the one or more bits at the memory location that remain in the second state do not correspond to a state of the received data ["Thus, the inversion module 110 may detect the number of bits having different logical values, by comparing the second data D2 with the first data D1. In some example embodiments, when the logical value of the specific bit of the first data D1 is ‘0’ and the logical value of the corresponding bit of the second data D2 is ‘1’, the inversion module 110 may detect the corresponding memory cell MC as a fail cell."] (Column 8, Lines 55 - 62); and writing the received data to the memory location by inverting the received data; and writing the inverted received data to the memory location ["In some example embodiments, when the number of fail cells is greater than the reference value (S304—YES), the controller 100 may inverse the first data D1 to generate the third data D3 (S306) [...] In some example embodiments, every bit of the first data D1 may be the inverse in corresponding bit locations in the third data D3. The third data D3 may be programmed in the memory cell(s) MC (S307). In some example embodiments, the third data D3 obtained by inversing the first data D1 may be programmed in the memory cell(s) MC…"] (Column 9, Lines 22 - 36).
However, Lee and Park do not teach the actual error determination also being based on checking whether one or more of the bits at the memory location remain in the second state. Andre, in an analogous art, teaches determining that one or more of the bits at the memory location remain in the second state ["With respect to the second set of bits, the memory device may be configured to apply a first down voltage across the tunnel junctions of the bit cells of the second set of bit cells to set at least a portion of the second set of bit cells to the low resistive state. The memory device may then evaluate the state of the second set of bit cells (for example, via a referenced read operation) to identify a second subset of the second set of bit cells remaining in the high resistive state."] (Paragraph 22). Lee, Park, and Andre are considered to be analogous art because they’re in the same field of reading from and writing to memory based on an error correction/detection scheme.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Andre with the teachings of Lee and Park, and add a step to check if the bits are in a first or second state different from the original state in the memory location (not comparing with the received data). This modification would have been obvious because a person of ordinary skill in the art would have been motivated to check if a bit is in a first or second state different from the original state to detect if an error has happened in the memory cell itself and address the error if needed. This would allow memory devices, like those that use magnetic tunnel junctions for example, to be “able to reduce the risk and speed at which at least some the MTJs are broken down or shorted, thereby extending the usable life of the device” (Andre, Paragraphs 21 & 22).
Regarding Claim 18, Lee, Park, and Andre teach all of the recited limitations in the independent Claim 14 as explained previously. Lee also teaches determining whether the one or more bits at the memory location correspond to a state of the received data ["Thus, the inversion module 110 may detect the number of bits having different logical values, by comparing the second data D2 with the first data D1. In some example embodiments, when the logical value of the specific bit of the first data D1 is ‘0’ and the logical value of the corresponding bit of the second data D2 is ‘1’, the inversion module 110 may detect the corresponding memory cell MC as a fail cell."] (Column 8, Lines 55 - 62).
However, Lee and Park do not teach determining that one or more of the bits at the memory location remain in the second state, and determining whether the one or more bits at the memory location that remain in the second state include an inversion bit for the memory location. Andre, in an analogous art, teaches determining that one or more of the bits at the memory location remain in the second state ["With respect to the second set of bits, the memory device may be configured to apply a first down voltage across the tunnel junctions of the bit cells of the second set of bit cells to set at least a portion of the second set of bit cells to the low resistive state. The memory device may then evaluate the state of the second set of bit cells (for example, via a referenced read operation) to identify a second subset of the second set of bit cells remaining in the high resistive state."] (Paragraph 22), and determining whether the one or more bits at the memory location that remain in the second state include an inversion bit for the memory location ["For example, if the minority state is the low resistive state, the data 402 is stored and one or more inversion bits are not set. However, if the minority state is the high resistive state, the data 402 is inverted before storing and the one or more inversion bits are set."] (Paragraph 68). Lee, Park, and Andre are considered to be analogous art because they’re in the same field of reading from and writing to memory based on an error correction/detection scheme.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Andre with the teachings of Lee and Park, and add a step to check if the bits are in a first or second state different from the original state in the memory location (not comparing with the received data) and determining whether there’s an inversion bit included to adjust the error detection. This modification would have been obvious because a person of ordinary skill in the art would have been motivated to check if a bit is in a first or second state different from the original state along with checking if inversion bits are present to detect if an error has happened in the memory cell itself and address the error if needed. This would allow memory devices, like those that use magnetic tunnel junctions for example, to be “able to reduce the risk and speed at which at least some the MTJs are broken down or shorted, thereby extending the usable life of the device” (Andre, Paragraphs 21 & 22).
Regarding Claim 19, Lee, Park, and Andre teach all of the recited limitations in the independent Claim 14 as explained previously. Lee also teaches determining that one or more of the bits at the memory location that remain in the second state correspond to the state of the received data ["Thus, the inversion module 110 may detect the number of bits having different logical values, by comparing the second data D2 with the first data D1. In some example embodiments, when the logical value of the specific bit of the first data D1 is ‘0’ and the logical value of the corresponding bit of the second data D2 is ‘1’, the inversion module 110 may detect the corresponding memory cell MC as a fail cell."] (Column 8, Lines 55 - 62), and writing the received data to the memory location [“In some example embodiments, the read/write circuit 240 may program the received data in the memory cell array 210.”] (Paragraph 46) based on that determination [“When the number of fail cells is equal to or less than the reference value (S304—NO), the process may end.”] (Column 9, Lines 13 - 14). However, Lee and Park do not teach determining that one or more of the bits at the memory location remain in the second state, and determining whether the one or more bits at the memory location that remain in the second state do not include an inversion bit for the memory location. Andre, in an analogous art, teaches determining that one or more of the bits at the memory location remain in the second state ["With respect to the second set of bits, the memory device may be configured to apply a first down voltage across the tunnel junctions of the bit cells of the second set of bit cells to set at least a portion of the second set of bit cells to the low resistive state. The memory device may then evaluate the state of the second set of bit cells (for example, via a referenced read operation) to identify a second subset of the second set of bit cells remaining in the high resistive state."] (Paragraph 22), and determining whether the one or more bits at the memory location that remain in the second state do not include an inversion bit for the memory location ["For example, if the minority state is the low resistive state, the data 402 is stored and one or more inversion bits are not set. However, if the minority state is the high resistive state, the data 402 is inverted before storing and the one or more inversion bits are set."] (Paragraph 68). Lee, Park, and Andre are considered to be analogous art because they’re in the same field of reading from and writing to memory based on an error correction/detection scheme.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Andre with the teachings of Lee and Park, and add a step to check if the bits are in a first or second state different from the original state in the memory location (not comparing with the received data) and determining whether there’s an inversion bit included to adjust the error detection. This modification would have been obvious because a person of ordinary skill in the art would have been motivated to check if a bit is in a first or second state different from the original state along with checking if inversion bits are present to detect if an error has happened in the memory cell itself and address the error if needed. This would allow memory devices, like those that use magnetic tunnel junctions for example, to be “able to reduce the risk and speed at which at least some the MTJs are broken down or shorted, thereby extending the usable life of the device” (Andre, Paragraphs 21 & 22).
Regarding Claim 20, Lee, Park, and Andre teach all of the recited limitations in the independent Claim 14 as explained previously. Lee also teaches determining that the one or more bits at the memory location that remain in the second state do not correspond to a state of the received data ["Thus, the inversion module 110 may detect the number of bits having different logical values, by comparing the second data D2 with the first data D1. In some example embodiments, when the logical value of the specific bit of the first data D1 is ‘0’ and the logical value of the corresponding bit of the second data D2 is ‘1’, the inversion module 110 may detect the corresponding memory cell MC as a fail cell."] (Column 8, Lines 55 - 62); and writing the received data to the memory location by inverting the received data; and writing the inverted received data to the memory location ["In some example embodiments, when the number of fail cells is greater than the reference value (S304—YES), the controller 100 may inverse the first data D1 to generate the third data D3 (S306) [...] In some example embodiments, every bit of the first data D1 may be the inverse in corresponding bit locations in the third data D3. The third data D3 may be programmed in the memory cell(s) MC (S307). In some example embodiments, the third data D3 obtained by inversing the first data D1 may be programmed in the memory cell(s) MC…"] Column 9, Lines 22 - 36). However, Lee and Park do not teach determining that one or more of the bits at the memory location remain in the second state, and determining whether the one or more bits at the memory location that remain in the second state do not include an inversion bit for the memory location. Andre, in an analogous art, teaches determining that one or more of the bits at the memory location remain in the second state ["With respect to the second set of bits, the memory device may be configured to apply a first down voltage across the tunnel junctions of the bit cells of the second set of bit cells to set at least a portion of the second set of bit cells to the low resistive state. The memory device may then evaluate the state of the second set of bit cells (for example, via a referenced read operation) to identify a second subset of the second set of bit cells remaining in the high resistive state."] (Paragraph 22), and determining whether the one or more bits at the memory location that remain in the second state do not include an inversion bit for the memory location ["For example, if the minority state is the low resistive state, the data 402 is stored and one or more inversion bits are not set. However, if the minority state is the high resistive state, the data 402 is inverted before storing and the one or more inversion bits are set."] (Paragraph 68). Lee, Park, and Andre are considered to be analogous art because they’re in the same field of reading from and writing to memory based on an error correction/detection scheme.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Andre with the teachings of Lee and Park, and add a step to check if the bits are in a first or second state different from the original state in the memory location (not comparing with the received data) and determining whether there’s an inversion bit included to adjust the error detection. This modification would have been obvious because a person of ordinary skill in the art would have been motivated to check if a bit is in a first or second state different from the original state along with checking if inversion bits are present to detect if an error has happened in the memory cell itself and address the error if needed. This would allow memory devices, like those that use magnetic tunnel junctions for example, to be “able to reduce the risk and speed at which at least some the MTJs are broken down or shorted, thereby extending the usable life of the device” (Andre, Paragraphs 21 & 22).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Lee and Park as applied to claim 1 above, and further in view of Schaefer, US Pub. No. US 20230231574 A1.
Regarding Claim 7, Lee and Park teach all of the recited limitations in the independent Claim 1 as explained previously. However, Lee and Park do not teach the first state being a value corresponding to a logic 1. Schaefer, in an analogous art, teaches the first state is a value corresponding to a logic 1 ["Accordingly, the DED component 320 may include a first state (e.g., a high state, a logic “1” state) if an even quantity of bit errors are detected in data, and may include a second state (e.g., a low state, a logic “0” state) if an odd quantity of bit errors (e.g., one error, three errors) are detected in the data"] (Paragraph 49). Lee, Park, and Schaefer are considered to be analogous art because it’s in the same field of reading from and writing to memory based on an error correction/detection scheme.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Schaefer with the teachings of Lee and Park, and assign the first state to be a value corresponding to a logic 1. This modification would have been obvious because a person of ordinary skill in the art would have been motivated to assign this state distinction so that the system can read the data/output and determine if an error is present and if a correction is needed [“the output of the error control circuit 315 may be a first value (e.g., a high voltage, a logical “1”) if the error control circuit 315 detected an error in the data or attempted to correct an error in that data. Alternatively, the output of the error control circuit 315 may be a second value (e.g., a low voltage or logical “0”) if the error control circuit 315 did not detect an error in the data”] (Paragraph 50).
Claim 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee, Park, and Andre as applied to claim 8 above, and further in view of Villa et al., hereafter referred to as Villa, US Pub. No. US 20220091933 A1.
Regarding Claim 12, Lee, Park, and Andre teach all of the recited limitations in the independent Claim 8 as explained previously. However, Lee, Park, and Andre do not teach the first state being a value corresponding to a logic 0 and the second state being a value corresponding to a logic 1. Villa, in an analogous art, teaches the method of claim 8, wherein the first state is a value corresponding to a logic 0 and the second state is a value corresponding to a logic 1 ["For instance, a first state of a memory cell may represent a first binary value (e.g., a logic 0) and a second state of the memory cell may represent a second binary value (e.g., a logic 1)."] (Paragraph 17). Lee, Park, Andre, and Villa are considered to be analogous arts because they’re all in the same field of reading from and writing to memory based on an error correction/detection scheme.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Villa with the teachings of Lee and Park, and Andre and assign the first state to be a value corresponding to a logic 0 and the second state to be a value corresponding to a logic 1. This modification would have been obvious because a person of ordinary skill in the art would have been motivated to assign these states so that the memory cells can be grouped into sets, and this would allow the reading and operation of ECC on the memory to become much more efficient [“To increase speed, memory cells may be written to, and read from, in sets. When a set of data is written to a set of memory cells, an ECC may be used so that errors are detectable when the memory cell is read.”] (Paragraph 17).
Claim 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee, Park, and Andre as applied to claim 8 above, and further in view of Shin et al., hereafter referred to as Shin, US Pub. No. US 20200183777 A1.
Regarding Claim 13, Lee, Park, and Andre teach all of the recited limitations in the independent Claim 8 as explained previously. However, Lee, Park, and Andre do not teach the first state being a low-resistance state and the second state being a high-resistance state relative to the low-resistance state. Shin, in an analogous art, teaches the method of claim 8, wherein the first state is a low-resistance state and the second state is a high-resistance state relative to the low-resistance state ["The first state S1 may be a low-resistance state, and the second state S2 may be a high-resistance state."] (Paragraph 52). Lee, Park, Andre, and Shin are considered to be analogous arts because they’re all in the same field of reading from and writing to memory based on an error correction/detection scheme.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Villa with the teachings of Lee, Park, and Andre and assign the first state to be a low-resistance state and the second state to be a high-resistance state relative to the low-resistance state. This modification would have been obvious because a person of ordinary skill in the art would have been motivated to assign these states so that an ordinary level resistance value ROL could be used to determine the state of the memory cells and supply a row of selected target memory cells with the appropriate amount of voltage or current [“During the read operation, an ordinary level resistance value ROL may be used which is placed between a range of resistance values of the first memory cells MC1 of the first state S1 and a range of resistance values of the second memory cells MC2 of the second state S2. For example, an ordinary read level (e.g., a voltage or a current amount) corresponding to the ordinary level resistance value ROL may be supplied to a row of selected target memory cells. That is, the ordinary read level may be characterized as a read threshold level set between programmed states of the memory cells that may be used to determine whether the memory cells are in the first state S1 or the second state S2. The read block 115 may determine whether resistance values of the selected target memory cells are greater than the ordinary level resistance value ROL or are smaller than the ordinary level resistance value ROL, based on current amounts or voltages of columns of the selected target memory cells. When a resistance value of a selected target memory cell of a specific column is smaller than the ordinary level resistance value ROL, the selected target memory cell is determined as being in the first state S1. When the resistance value of the selected target memory cell of the specific column is greater than the ordinary level resistance value ROL, the selected target memory cell is determined as being in the second state S2.”] (Paragraphs 54 & 55).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROJO H RAMIANDRISOA whose telephone number is (571)270-0980. The examiner can normally be reached Monday-Friday 7:30 am-3:30 pm.
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/ROJO HARIVOLA RAMIANDRISOA/ Examiner, Art Unit 2112
/ALBERT DECADY/ Supervisory Patent Examiner, Art Unit 2112
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