DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/01/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Claims 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention Group II, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 09/02/2026.
Applicant's election with traverse of Group I corresponding to claims 1-14 in the reply filed on 09/02/2026 is acknowledged. The traversal is on the ground(s) that merely requiring a search of different classes or different electronic resources or employing different search strategies or search queries is not evidence of a serious search burden when searches are computed-assisted. This is not found persuasive because the MPEP § 808.02 indicates that serious search burden is demonstrated by searching different classes and employing different fields of search. The MPEP guidance remains effective even when searches are computer-assisted.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 5-6, and 10-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hung et al US 20080059768.
Regarding claim 1, Hung teaches a method comprising:
determining whether a software request at a microcontroller unit (MCU) (see figure 1, master 110) is pending, the software request being to read data from an serial peripheral interface (SPI) device or write the data to the SPI device, the SPI device being selected from a plurality of SPI devices arranged in an SPI device matrix (see figure 9, memory cell in the cell array 900) and being electrically connected to the MCU (see para 0041, the READ instruction code is sent which is associated with the use of a single SPI pin to communicate data);
responsive to determining that the software request is pending, driving, by the MCU, a column select signal and a row select signal with an SPI device address associated with the SPI device (see figure 9, address 905 is driven as a column select signal and a row select signal, also see para 0095, the address sent from the master integrated circuit to the slave integrated circuit);
decoding, by a chip select decoder logic, the column select signal and the row select signal, wherein the chip select decoder logic is electrically connected to each of the plurality of SPI devices (decoder including column decoder 903 and row decoder 901, also see para 0051, Addresses are supplied on bus 905 to column decoder 903 and row decoder 901); and
performing, by the MCU, an SPI transaction with the SPI device selected from the plurality of SPI devices, the SPI transaction being one of reading the data from the SPI device or writing the data to the SPI device (see para 0051, the arrangements for programming, erasing, and reading the memory cells, such as with DDR timing and/or parallel interleaved use of two SPI communication pins).
Regarding claim 2, Hung further teaches the MCU and the plurality of SPI devices form an SPI bus (see para 0035, an SPI interface configuration with a master integrated circuit device electrically connected to slave integrated circuit devices).
Regarding claim 5, Hung further teaches the SPI bus further comprises a master out/slave in (MOSI) line, a serial clock (SCLK) line, a master in/slave out (MISO) line, and a chip select (CS) line (see figure 1, signal lines from master 110).
Regarding claim 6, Hung further teaches the MCU is electrically connected to the plurality of SPI devices via at least the chip select decoder logic (see figures 1 and 9).
Regarding claim 10, Hung further teaches decoding, by the chip select decoder logic, the column select signal and the row select signal further comprises determining which of the plurality of SPI devices is the SPI device based at least in part on the column select signal and the row select signal (see para 0051, Addresses are supplied on bus 905 to column decoder 903 and row decoder 901).
Regarding claim 11, Hung further teaches a configuration of the chip select decoder logic is based at least in part on a number of SPI devices of the plurality of SPI devices (see figure 9).
Regarding claim 12, Hung further teaches the chip select decoder logic comprises a plurality of chip select decoders and a row address decoder (see figure 9, column decoder 903 and row decoder 901).
Regarding claim 13, Hung further teaches the chip select decoder logic comprises a plurality of chip select decoders and inversion logic (see figure 9, column decoder 903 and data logic structure 906).
Regarding claim 14, Hung further teaches the chip select decoder logic comprises a plurality of chip select decoders (see figure 9, column decoder 903 and row decoder 901).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Hung as applied to claims above, and further in view of Li et al US 20110246708.
Regarding claim 3, Hung teaches all the features with respect to claim 1 as outlined above.
But Hung fails to teach prior to determining whether the software request at the MCU is pending, the SPI bus is in an idle state.
However, Li teaches prior to determining whether the software request at the MCU is pending, the SPI bus is in an idle state (see para 0066, when an instruction enabling signal sent from the instruction enabling control module 33 is detected by the main state machine 34, the main state machine 34 transitions from the “idle” state).
Therefore, it would have been obvious to modify the SPI bus of Hung and further incorporate an idle state.
The motivation for doing so is to save power and prepare the bus for receiving transactions.
Regarding claim 4, Li further teaches determining whether the SPI transaction is complete; and responsive to determining that the SPI transaction is complete, returning the SPI bus to the idle state (see para 0066, when the transmission is completed, the main state machine may transition, according to the configuration of the register, to a next state or back to the “idle” state).
Claims 7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Hung as applied to claims above, and further in view of Chou et al US 20080307126.
Regarding claim 7, Hung teaches all the features with respect to claim 6 as outlined above.
But Hung fails to teach the MCU is further electrically connected to the plurality of SPI devices via at least a multiplexer and a buffer.
However, Chou teaches a MCU is electrically connected to the plurality of SPI devices via at least a multiplexer and a buffer (see figures 3 and 5, buffer 502 and multiplexer 504).
Therefore, it would have been obvious to modify the connection of Hung and further incorporate a multiplexer and a buffer.
The motivation for doing so is to provide buffering and data selection capability to the connection.
Regarding claim 9, Chou further teaches the multiplexer comprises a MISO multiplexer (see figure 5).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Hung and Chou as applied to claims above, and further in view of Barrenscheen US 20260067126.
Regarding claim 8, the combination of Hung and Chou teaches all the features with respect to claim 7 as outlined above.
But the combination of Hung and Chou fails to teach the buffer comprises a SCLK buffer and a MOSI buffer.
However, Barrenscheen teaches a SPI buffer comprises a SCLK buffer and a MOSI buffer (see figure 3, buffer stage 118 having SCLK buffer and MOSI buffer 138).
Therefore, it would have been obvious to modify the SPI buffer of Chou and further incorporate SCLK buffer and MOSI buffer of Barrenscheen.
The motivation for doing so is to provide buffering on both the clock and the data signals.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hansen US 20240119019 discloses sharing communication lines among multiple SPI buses
Carpenter et al US 20080282017 discloses an SPI switch providing address translation
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHONG H DANG whose telephone number is (571)272-0470. The examiner can normally be reached Monday-Friday 9:30AM - 6:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached at (571)272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PHONG H DANG/Primary Examiner, Art Unit 2184
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