DETAILED ACTION
Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
This Office Action is sent in response to Applicant’s Communication received on 01/29/2025 for application number 19/040,410.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required: amend the specification to include the claimed subject matter stated in claim 14, “wherein the controller is configured to determine accuracy of the exit latency received from the host device, and wherein the controller is configured to dynamically adjust the exit latency based upon the determined accuracy.” (emphasis added)
Claim Objections
Claim 16 is objected to because of the following informalities: “configured to manager L0p entry” (emphasis added) should read “configured to manage L0p entry” (emphasis added). Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “decryption module” in claim 6 and “means for storing data” in claim 18.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6 and 14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites the limitation "the group consisting of…" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim 14 recites the limitation “determine accuracy of the exit latency...” The term “accuracy” is not defined by the claim and the specification does not further limit the term. It is unclear what metric is being used to check for accuracy.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over Srivastava et al. (US 2024/0111354 A1) in view of Connor et al. (US 2021/0041929 A1).
Regarding claim 1, Srivastava teaches a data storage device (Figure 2), comprising:
a memory device (Figure 2, system memory 240, 274); and
a controller coupled to the memory device (Figure 2, PCIe controller 218, 262), wherein the controller is configured to:
record LOp exit latency of link partner, wherein the exit latency is a first period of time (“The host system memory 240 and the endpoint system memory 274 at the endpoint may be configured to contain registers for the status of each transmit line and receive line of the PCIe link 285.” Par 0036 and “bit 3 can indicate whether or not L0p is supported by a receiver, bits 4-6 can indicate the port L0p exit latency,” par 0067 and “whenever the PCIe link is inactive for the given L0s or L1 entry latency duration, a PCIe controller may request a link partner to enter a lower-power or standby link state (L0s or L1) in order to save power.” Par 0056) [the controller records the port L0p exit latency (first period of time) of its host/endpoint (link partner) by reading capability bits in the device capabilities 3 register, see Figure 9 and par 67];
initiate LOp request to save power (“a PCIe controller may request a link partner to enter a lower-power or standby link state (L0s or L1) in order to save power.” Par 0056);
However, Srivastava does not explicitly teach determine that data needs to be transferred to the link partner; initiate LOp exit request, wherein the initiation occurs at a second period of time, wherein the second period of time is before transferring the data to the link partner, and wherein the second period is equal to or greater than the first period of time; and transfer the data to the link partner.
In the analogous art, Connor teaches determine that data needs to be transferred to the link partner (“In the case of egress traffic … it will monitor the depth of a buffer or queue used to store packets that are to be transmitted out onto the network (e.g., to a link partner connected via an Ethernet link).” Par 0050);
initiate LOp exit request, wherein the initiation occurs at a second period of time (“a power manager (e.g., 125) may be equipped with latency manager logic (e.g., 350) to initiate latency mitigations to correspond to the triggering of corresponding power management transitions.” Par 0052), wherein the second period of time is before transferring the data to the link partner (“to buy time for the transition in data rate or link width, the I/O controller may additionally act to quiesce incoming network traffic, such as by sending a pause frame to the link partner to momentarily halt incoming traffic” par 0049), and wherein the second period is equal to or greater than the first period of time (“the maximum pause time request is 335.5 μs, which provides the requisite time to perform at least some of the power management transitions available to the controller (e.g., more than enough time to increase the number of lanes (˜180 μs)).” Par 0063) [the requested pause duration corresponds to the second period of time which is equal/greater than exit latency (first period, 180 μs) to ensure the L0p transition completes before data transfer]; and
transfer the data to the link partner (“it will monitor the depth of a buffer or queue used to store packets that are to be transmitted out onto the network (e.g., to a link partner connected via an Ethernet link)” par 0050).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Srivastava and Connor before him before the effective filing date of the claimed invention, to have modified Srivastava to incorporate the teachings of Connor to initiate the L0p request to ensure the transition occurs before the data transfer resumes with the link partner to reduce power without being detrimental to network performance. This will also yield a reduction in both power and thermal load on the system as well as battery life in mobile computing systems. (Connor, paragraph 44)
Regarding claim 2, Srivastava and Connor teach the data storage device of claim 1. Srivastava further teaches wherein the controller is configured to determine that the first period of time has changed and record the changed first period of time (“these registers include TX control, status, and capabilities registers 1062 and RX control, status, and capabilities registers 1064. These registers may be accessed and read at the start of link initialization and then updated with the result of the initialization. The registers may also be modified in response to power management and bandwidth negotiations or to change the status of one or more transmit lines or receive lines of the link 1002.” Par 0074 and “Bandwidth requests may cause a bandwidth negotiation followed by a change in values set to control, status, and capabilities registers.” Par 0076 and “The device capabilities 3 register can have 32 bits in which … bits 4-6 can indicate the port L0p exit latency,” par 0067).
Regarding claim 3, Srivastava and Connor teach the data storage device of claim 1. Srivastava further teaches wherein the controller comprises a LOp manager module (Figure 10, interface configuration 1018 and par 0069 and 0073).
Regarding claim 4, Srivastava and Connor teach the data storage device of claim 3. Srivastava further teaches wherein the LOp manager module comprises a timer (Figure 10, timer 1012 and par 0070).
Regarding claim 5, Srivastava and Connor teach the data storage device of claim 4. Connor further teaches wherein the LOp manager module is configured to maintain a table comprising data corresponding to time for events to occur (“Tables 3 and 4 show example exit latencies for such transitions in an example system (e.g., a PCIe 4.0 device). For instance, Table 3 shows example latencies for changing PCIe bus bandwidth (link width).” Par 0060 and par 52) [the latency manager logic (which the power manager) uses these tables to determine data corresponding to time (exit latencies) for events to occur, such as transitioning between different link widths].
Regarding claim 7, Srivastava and Connor teach the data storage device of claim 4. Srivastava further teaches wherein the initiating the LOp exit request is triggered by the timer (“The timer circuitry 1012 can be configured for various timing-related functions, for example, timing for latency, inactivity, acknowledgment, and transition between PCIe states (e.g., L0, L0p, L0ps, L1, L2, and L3).” Par 0070).
Regarding claim 8, Srivastava and Connor teach the data storage device of claim 1. Srivastava further teaches wherein the controller is configured to measure the exit latency of the link partner (“The timer circuitry 1012 can be configured for various timing-related functions, for example, timing for latency, inactivity, acknowledgment, and transition between PCIe states (e.g., L0, L0p, L0ps, L1, L2, and L3)… The timer circuitry 1012 may … determine transition timing between PCIe link states.” Par 0070).
Regarding claim 9, Srivastava and Connor teach the data storage device of claim 1. Srivastava further teaches wherein the initiating the LOp request comprises requesting the link partner to move one or more lanes of the link into an electrical idle state (“The interface configuration circuitry 1018 may modify the configuration in response to the power management circuitry 1014. For example, the interface configuration circuitry 1018 can change the link state (e.g., L0, L0p, L0ps) of the link 1002.” Par 0073 and “A message may then be sent to the connected device (e.g., the host or endpoint) through the link 1002.” Par 0076 and “In L0p, some lanes of a link may be in an electrical idle (EI) state while other lanes remain available for transferring PCIe traffic.” Par 0057) [the controller initiates an L0p request by sending a message to the link partner (connected device) to transition the link into the partial width state where some lanes are moved to EI state].
Regarding claim 10, Srivastava and Connor teach the data storage device of claim 1. Connor further teaches wherein the controller is configured to determine whether a next data transfer time is more than the exit latency (“the maximum pause time request is 335.5 μs, which provides the requisite time to perform at least some of the power management transitions available to the controller (e.g., more than enough time to increase the number of lanes (˜180 μs)).” Par 0063) [the controller determines if the maximum pause time (delay before next data transfer resumes) is greater than the exit latency (180 μs) to ensure the link transition completes before the traffic continues].
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Srivastava and Connor in view of Heller et al. (US 2022/0011965 A1).
Regarding claim 6, Srivastava and Connor teach the data storage device of claim 5. Connor further teaches entry to a decoder (“A core 802 may include a decode module coupled to a fetch unit to decode fetched elements” par 0071), entry to a decryption module (“VNF 134 may comprise a software implementation of a functional building block … collectively provide specific functionalities (e.g., wide area network (WAN) optimization, virtual private network (VPN) termination, firewall operations … security functions, etc.).” par 0025) [this shows routing of tasks into functional security modules for different functions (e.g. VPN termination)].
However, Srivastava and Connor do not explicitly teach wherein the events are selected from the group consisting of memory device sense time, start of memory device transfer time, end of memory device transfer time, entry to a redundant array of inexpensive/independent disks (RAID), entry to a decryption module, and entry to a host interface module (HIM).
In the analogous art, Heller teaches wherein the events are selected from the group consisting of memory device sense time (“A sensor of the controller remains active to detect a wakeup signal from the host that causes the data storage device to transition to a higher power state.” Par 0025) [this shows sensor based signal detection for device transitions], start of memory device transfer time (“the controller 108 temporarily stores the data associated with the write command in the internal memory before sending the data to the NVM 110.” Par 0037) [data is queued before sending it to NVM, corresponding to a start of a transfer event], end of memory device transfer time (“controller 108 may initiate a data storage command to store data to the NVM 110 and monitor the progress of the data storage command” par 0037), entry to a redundant array of inexpensive/independent disks (RAID) (“the storage system 100 may include a plurality of data storage devices 106 configured as a redundant array of inexpensive/independent disks (RAID) that collectively function as a mass storage device for the host device 104.” Par 0026), and entry to a host interface module (HIM) (“FIG. 10 is a schematic block diagram 1000 illustrating signaling of a host interface module (HIM) 1004 to enter and exit an L1 sub-state” par 0063).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Srivastava, Connor and Heller before him before the effective filing date of the claimed invention, to have modified Srivastava and Connor to incorporate the teachings of Heller to include events such as memory sense time, memory device transfer time, and RAID and HIM entries and include signals that instruct the components to enter a low power or L1 state/wake up from low power or L1 state to enable power efficiency and include L1 sub-state support which have low power requirements. (Heller, paragraphs 5-6)
Claims 11, 12, 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Heller et al. (US 2022/0011965 A1) in view of Connor et al. (US 2021/0041929 A1).
Regarding claim 11, Heller teaches a data storage device (Figures 1, 10), comprising:
a memory device (Figure 1, volatile memory 112, buffer 116 and nonvolatile memory 110); and
a controller coupled to the memory device (Figure 1, controller 108), wherein the controller is configured to:
maintain a link between a host interface module (HIM) and a host device (“The HIM 1004 may be a component of the controller 108 of FIG. 1. A host device 1002 is electrically coupled to the HIM 1004,” par 0063), and wherein the link has an exit latency (“each power state has an associated power requirement and an exit latency.” Par 0042).
However, Heller does not explicitly teach wherein the link comprises a plurality of lanes; determine whether one or more lanes of the plurality of lanes needs to be woken up; send a LOp exit request to the host device, wherein the sending occurs at a first point in time; transfer data to the host device, wherein the transferring occurs as a second point in time, and wherein a difference between the second point in time and the first point in time is equal to or greater than the exit latency.
In the analogous art, Connor teaches wherein the link comprises a plurality of lanes (“A link may support one or more lanes—each lane representing a set of differential signal pairs (one pair for transmission, one pair for reception). To scale bandwidth, a link may aggregate multiple lanes” par 0053);
determine whether one or more lanes of the plurality of lanes needs to be woken up (“the I/O controller may determine whether the traffic has passed above (at 735) a threshold for which an increase in speed and/or link width is to be triggered (e.g., to accommodate accelerating network traffic).” Par 0066);
send a LOp exit request to the host device, wherein the sending occurs at a first point in time (“the I/O controller may additionally act to quiesce incoming network traffic, such as by sending a pause frame to the link partner to momentarily halt incoming traffic” Par 0049 and “The I/O controller 205 may couple to another device 310 (e.g., a host processor, board, memory device, accelerator, etc.) via a link” par 0045); and
transfer data to the host device, wherein the transferring occurs as a second point in time (“Operation of the I/O controller may continue at the adjusted link characteristics, with network traffic continuing to be monitored (at 710)” par 0066 and Figures 3, 4A, 4B, 7), and wherein a difference between the second point in time and the first point in time is equal to or greater than the exit latency (“the maximum pause time request is 335.5 μs, which provides the requisite time to perform at least some of the power management transitions available to the controller (e.g., more than enough time to increase the number of lanes (˜180 μs)).” Par 0063) [the controller starts a transition (such as L0p exit to increase lanes) and sends a pause frame to ensure the delay before the data resumes (second time) is equal to (requisite) or greater than the transition’s exit latency].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Heller and Connor before him before the effective filing date of the claimed invention, to have modified Heller to incorporate the teachings of Connor to initiate the L0p request to ensure the transition occurs before the data transfer resumes with the link partner to reduce power without being detrimental to network performance. This will also yield a reduction in both power and thermal load on the system as well as battery life in mobile computing systems. (Connor, paragraph 44)
Regarding claim 12, Heller and Connor teach the data storage device of claim 11. Connor further teaches wherein the controller is configured to send a request to the host device to move one or more lanes of the plurality of lanes into an electrically idle state (“As shown in FIG. 4B, a subset of lanes (e.g., Lanes 4-7) of the link 405 may be disabled or placed in a low power or idle link state to save power and consequently reduce the bandwidth of the link.” Par 0054 and “training sequences may be exchanged to negotiate the link width that is to be applied in the link… changing the link width (e.g., in response to detecting a traffic threshold) may involve initiating upconfiguration or downconfiguration of the link width (e.g., as implemented by the I/O controller 205 or device 310),” par 0056).
Regarding claim 15, Heller and Connor teach the data storage device of claim 11. Connor further teaches wherein the controller comprises a LOp manager module (“a power manager of an I/O controller may trigger automatic transition of a link from one link width (e.g., a full link width) to another link width (e.g., partial link width) to dynamically manage power based on traffic detected at the I/O controller.” Par 0054), wherein the LOp manager module comprises a timer (“determine (at 730) whether this threshold is met … for a defined threshold amount of time.” Par 0066), and wherein the LOp manager module is configured to initiate the sending of the LOp exit request (“If the threshold is met for the defined period of time, a power management transition may be initiated by causing the link (e.g., using state machine or protocol logic of the I/O controller interface implementing the link (e.g., a PCIe interface or port)) to adjust the link width (or lane width) of the link and/or the data rate used on the link (at 740).” Par 0066) [the controller uses a power manager (L0p manager module) to monitor traffic thresholds against a time threshold (timer) to start a power management transition (L0p exit request)].
Regarding claim 16, Heller and Connor teach the data storage device of claim 11. Connor further teaches wherein the controller is configured to manager LOp entry and exit timing based upon the exit latency and timing of events that occur during read command processing (“the I/O controller may monitor a transmit descriptor queue. In such implementations, transmit packets are queued in the transmit descriptor ring before they are transferred across the PCIe bus … If the number of packets (or number of descriptors) in the descriptor ring meets a particular DAPLS transmit threshold then (similar to when a receive threshold is crossed) the I/O controller automatically adjusts the number of enabled lanes” par 0050 and “the maximum pause time request is 335.5 μs, which provides the requisite time to perform at least some of the power management transitions available to the controller (e.g., more than enough time to increase the number of lanes (˜180 μs)).” Par 0063) [the controller manages the L0p timing (adjusting active lanes) by parsing a transmit descriptor ring (read command) to initiates preemptive transitions based on traffic events; pause frames are used to ensure data delay matches the exit latency].
Regarding claim 17, Heller and Connor teach the data storage device of claim 16. Connor further teaches wherein the controller is configured to maintain a table of the timing of the events in a LOp manager module (“Tables 3 and 4 show example exit latencies for such transitions in an example system (e.g., a PCIe 4.0 device). For instance, Table 3 shows example latencies for changing PCIe bus bandwidth (link width).” Par 0060 and par 52) [the latency manager logic (which the power manager) uses these tables to determine data corresponding to time (exit latencies) for events to occur, such as transitioning between different link widths].
Claims 13 are rejected under 35 U.S.C. 103 as being unpatentable over Heller and Connor in view of Yi et al. (US 2024/0020035 A1).
Regarding claim 13, Heller and Connor teach the data storage device of claim 11. However, Heller and Connor do not explicitly teach wherein the determining occurs after parsing a read command and wherein the transferred data is for the read command.
In the analogous art, Yi teaches wherein the determining occurs after parsing a read command and wherein the transferred data is for the read command (“when receiving a data reading request from the driver 213, the host controller 215 may provide the reading request to the device 220 through the host interface 217 and receive data from the device 220.” Par 0066 and “when an output request indicating data output (e.g., reading) is monitored, the lane determination module 255 may determine to operate the second group of lanes that can cover the required performance (e.g., 1.8 GB/s) in the reading operation.” Par 0086 and “process the data through a second group of lanes in which a greater number of lanes than the first group of lanes are activated when the input/output request indicates data output (reading)” par 0008 and “detect a lane increase event… [which] may include a situation in which an output request indicating data output (e.g., reading) is detected.” Par 0188).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Heller, Connor and Yi before him before the effective filing date of the claimed invention, to have modified Heller and Connor to incorporate the teachings of Yi because all three references are directed at optimizing lane activation for data processing. Incorporating the teachings of Yi to Heller and Connor to parse a read command to determine whether one or more lanes need to be woken up may allow the controller to adjust the data processing performance based on the read command and reduce overall power consumption.
Claims 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ishiguro (US 2024/0248645 A1) in view of Srivastava et al. (US 2024/0111354 A1).
Regarding claim 18, Ishiguro teaches a data storage device (Figure 1), comprising:
means for storing data (Figure 1, DRAM 5 and NAND 4); and
a controller coupled to the means for storing data (Figure 1, controller 6), wherein the controller is configured to:
parse and schedule a read command (“the PCIe link controller 22 receives a packet from the host 2 … [and] processes the packet, thereby acquiring, for example … a read command” par 0040 and “the NVMe controller 23 manages command information 231 … commands that have been issued by the host 2 but for which corresponding processes have not yet been performed in the memory system 3 are referred to as outstanding commands … commands that have been issued by the host 2 and accepted by the memory system 3 but for which corresponding processes have not yet been executed in the memory system 3” Par 0043) [the controller parses incoming host packets to identify read commands and schedules them by tracking their progress as outstanding commands to coordinate data transfer with link state management];
determine a point in time for sending a LOp exit request to a host device (“The link width control unit 221 determines the link width based on the command information 231.” Par 0061 and “ in response to the output preparation completion information 121 indicating that user data (read data) to be read from the NAND flash memory 4 in accordance with a read command is ready to be output to the SRAM 16, the link width control unit 221 may widen the current link width xn to the link width x(2n).” par 0126), wherein the point in time is during execution of the read command and before data for the read command reaches a host interface module (HIM) (“The NAND I/F 12 sends the output preparation completion information 121 to the host I/F 15, for example, in response to completion of a sense operation in accordance with the read command.” Par 0030 and “This is because the read data to be output from the NAND flash memory 4 is data to be transferred from the memory system 3 to the host 2 after being stored in the SRAM 16” par 0126 and Figure 1, host interface 15) [the controller determines specific point in time to initiate a link width expansion (exiting reduced L0p width) by detecting when a read command’s NAND sensing is complete, allowing the link to expand while data is still held in the internal buffer before it reaches the HIM];
send the LOp exit request to the host device (“the link width control unit 221 transitions the link 31 from the link power state L0p to the link power state L0” par 0108); and
send the data for the read command to the host device (“The NVMe controller 23 also performs an operation to transmit data that includes a response to a command, to the host 2 via the PCIe link controller 22 and the PCIe PHY 21” par 0042).
However, Ishiguro does not explicitly teach compare LOp exit latency to values in a table containing time before seeing traffic on a link.
In the analogous art, Srivastava teaches compare LOp exit latency to values in a table containing time before seeing traffic on a link (“The timer circuitry 1012 may also access registers maintained in the storage medium 1008 (and/or memory 1021) [table] that contain receive (RX) traffic timing thresholds 1034 and transmit (TX) traffic timing thresholds 1036, which can be used to determine transition timing between PCIe link states.” Par 0070 and “ bit 3 can indicate whether or not L0p is supported by a receiver, bits 4-6 can indicate the port L0p exit latency, and bits 7-9 can indicate the retimer L0p exit latency.” Par 0067) [the controller uses the registers that have timing threshold information to manage transitions for the L0p state based on link traffic and exit latency].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Ishiguro and Srivastava before him before the effective filing date of the claimed invention, to have modified Ishiguro to incorporate the teachings of Srivastava to compare the latency values to a table before seeing traffic on a link to determine transition timing between PCIe link states, allowing for unused lanes to be placed in an idle state, ultimately conserving power.
Regarding claim 20, Ishiguro and Srivastava teach the data storage device of claim 18. Srivastava further teaches wherein the controller is configured to dynamically adjust the LOp exit latency (“Bandwidth requests may cause a bandwidth negotiation followed by a change in values set to control, status, and capabilities registers.” Par 0076 and “ bits 4-6 can indicate the port L0p exit latency, and bits 7-9 can indicate the retimer L0p exit latency.” Par 0067 and Figure 9).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Ishiguro and Srivastava in view of Halleck et al. (US 2017/0109300 A1).
Regarding claim 19, Ishiguro and Srivastava teach the data storage device of claim 18. However, Ishiguro and Srivastava do not explicitly teach wherein a difference between a first time when the sending of the data for the read command to the host device and a second time when sending the LOp exit request to the host device is equal to or greater than the LOp exit latency.
In the analogous art, Halleck teaches wherein a difference between a first time when the sending of the data for the read command to the host device and a second time when sending the LOp exit request to the host device is equal to or greater than the LOp exit latency (“An L0 entry (or L0p exit) request can be sent within the interval 1410 [second time], prompting the ports A and B to prepare for exiting the L0p state…After the close of the L0c interval 1410, additional flits 1415 can be sent [first time] prior to the point at which the L0p exit is to occur … Flit data (e.g., 1315) can continue to be sent to maximize data transfer while the devices anticipate to enter the state transition.” Par 0110 and “The SDS includes a byte number field to indicate a number of a bytes measured from a previous control interval of the link, and an end of the SDS is sent to coincide with a clean flit boundary on the active lanes” Abstract) [the read command corresponds to the host request for data that the device fulfills by sending flits; the system tracks the interval between the exit request and final reconfiguration using the SDS byte number field, which ensures data flits are sent for a time period equal to or greater than the latency so the link only expands when the idle lanes are synchronized which is limited by the L0p timeout, see paragraphs 74-77, 80-81].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Ishiguro, Srivastava and Halleck before him before the effective filing date of the claimed invention, to have modified Ishiguro and Srivastava to incorporate the teachings of Halleck to have a difference between the time of sending data to the host device and the time of sending the L0p exit request to be equal/greater than the L0p exit latency to maximize data transfer to ensure the idle lanes have enough time to train and deskew before the link transitions to full width. This prevents errors/resets that may occur if the idle lanes were used before synchronization.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Richter et al. (US 2021/0026559 A1) teaches a device for improving data read request scheduling in storage devices. The controller sets a maximum outstanding read requests for the storage device which can be dynamically adjusted based on changes in a host-device connection protocol and a latency tracker included in the controller.
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/AYMAN FATIMA/Examiner, Art Unit 2176
/JAWEED A ABBASZADEH/Supervisory Patent Examiner, Art Unit 2176
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