DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Terminal Disclaimer
The terminal disclaimer filed has been accepted and the double patenting rejection withdrawn.
Response to Amendment
The amendments filed 5/22/2026 have been accepted. Claims 1-20 are still pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8-14, and 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Chou (US PGPub 2018/0189174) in view of Joshi et al. (US PGPub 2014/0013059, hereafter referred to as Joshi).
Regarding claim 1, Chou teaches a system comprising: a memory device having an associated logical address space, and a processing device, operatively coupled with the memory device (Fig. 1 and Paragraphs [0016]-[0017], show the device that has a memory device and a controller connected to the memory device. Paragraph [0020], shows there is a logical address space associated with the memory), to perform operations comprising: configuring a first partition of the logical address space for a first logical address mapping granularity and a second partition of the logical address space for a second logical address mapping granularity (Paragraph [0020], states the host can send a create request back with a particular configurations of namespaces which can include a formatted logical block addresses (LBA), which can have LBAs size (granularity). Paragraph [0021], states that a global mapping table which defines the partitions can be created thereby configuring the partitions). Chou does not explicitly teach a second partition of the logical address space for a second logical address mapping granularity, and processing a plurality of memory access operations directed to the first partition and the second partition of the logical address space according to the first and second logical address mapping granularities
Joshi teaches a second partition of the logical address space for a second logical address mapping granularity (Paragraph [0059] and [0064], states that a cache can support multiple page sizes and that the cache can be divided up into sections (partitions) each of which supports different page sizes), processing a plurality of memory access operations directed to the first partition and the second partition of the logical address space according to the first and second logical address mapping granularities (Paragraph [0024] states that the data and access to the data are then managed based on the created table and configured partitions. Paragraph [0059] and [0064], since the cache is being partitioned into different sections that have different page granularities it means that the configurations would be finalized as they are put into use and that access operations to those partitions would be done using the configured page size as that is how the partitions have been set up to be used. It should be noted that this is true for any system that utilizes partitions of any kind and different granularities). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Chou to also support multiple different pages sizes (and thus having logical address granularity configurations) as taught in Joshi so to improve utilization of system resources (Joshi, Paragraph [0061]).
Regarding claim 2, Chou and Joshi teach all the limitations to claim 1. Chou further teaches wherein the first logical address mapping granularity defines a first number of logical block addresses that are associated with one physical address of the memory device, and wherein the first logical address mapping granularity defines a second number of logical block addresses that are associated with one physical address of the memory device (Paragraph [0028], shows that the LBAs are associated with a block and page ID. Since blocks can contain multiple pages it means that there can be multiple LBAs associated with a particular block). Joshi further teaches multiple logical address mapping granularities (Paragraph [0059] and [0064], as stated in the rejection to claim 1). The combination of and reason for combining are the same as those given in claim 1.
Regarding claim 3, Chou and Joshi teach all the limitations to claim 1. Chou further teaches a volatile memory device storing data (Fig. 1 and Paragraph [0017], shows the volatile storage medium for storing data).
Chou also teaches storing a logical-to-physical (L2P) mapping data structure for the logical address space, the L2Pmapping data structure comprising a number of entries (Fig. 4 and Paragraph [0022], shows the global H2F mapping table which maps the logical addresses to physical memory locations. However, it is not stated where specifically in the system the mapping table is stored). Since Chou/Joshi teaches a volatile memory for storing data and storing a mapping table it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the storage location of the mapping table with the volatile memory to obtain the predictable result of a volatile memory device storing a logical-to-physical (L2P) mapping data structure for the logical address space (as all this does is specify where the mapping table is stored).
Regarding claim 4, Chou teaches all the limitations of claim 3. Chou further teaches wherein the number of entries in the L2P mapping data structure is based on logical address mapping granularities of partitions of the logical address space (Fig. 4 and Paragraph [0022], as the mapping table is based on the configuration command which specifies the number of LBAs for a partition and the size of the LBAs for a partition it means the entries in the table will be based on this information). The combination of and reason for combining are the same as those given in claim 3.
Regarding claim 5, Chou and Joshi teach all the limitations to claim 1. Joshi further teaches wherein the first partition and the second partition comprise at least one of a boot partition, a system partition, a cache partition, an application partition, an application data partition, or a media partition (Paragraphs [0059] and [0064], the cache is partitioned for use by applications making the partitions application partitions). The combination of and reason for combining are the same as those given in claim 1.
Regarding claim 6, Chou and Joshi teach all the limitations to claim 1. Chou further teaches wherein the processing device is to perform operations further comprising: obtaining, from a host system, a logical address granularity configuration for at least one of the first partition or the second partition of the logical address space, the logical address granularity configuration defining at least one of the first logical address mapping granularity or the second logical address mapping granularity (Paragraph [0020], states the host can send a create request back with a particular configurations of namespaces which can include a formatted logical block addresses (LBA), which can have LBAs size. Since the size of the namespace can be expressed in terms of number of LBAs the host and controller would have to know the size of the LBA to know how much space is being requested and eventually allocated so as to create a proper mapping). The combination of and reason for combining are the same as those given in claim 1.
Regarding claims 8-13, claims 8-13 are the method claims associated with claims 1-6. Since Chou and Joshi teach all the limitations to claims 1-6, they also teach all the limitations to claims 8-13; therefore the rejections to claims 1-6 also apply to claims 8-13.
Regarding claims 15-19, claims 15-19 are the system claims associated with claims 1-6. Since Chou and Joshi teach all the limitations to claims 1-6 and further teaches a memory device having an associated logical address space arranged in a plurality of partitions; and a processing device, operatively coupled with the memory device (Fig. 1 and Paragraphs [0016]-[0017] and [0020], as stated in the rejection to claim 1, the memory that is coupled to the controller (processing device) is shown to be divided into several namespaces), they also teach all the limitations to claims 15-19; therefore the rejections to claims 1-6 also apply to claims 15-19.
Claims 7, 14, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chou and Joshi in further view of Yang et al. (US PGPub 2022/0107743, hereafter referred to as Yang).
Regarding claim 7, Chou and Joshi teach all the limitations of claim 6. Chou and Joshi do not teach wherein the logical address granularity configuration is based on a write workload size of the host system.
Yang teaches wherein the logical address granularity configuration is based on a write workload size of the host system (Paragraph [0040], describes the use of workload zones that can have different granularities (particularly virtual zones meaning they are using a logical address space) and be based on things like a workload set size or ratio of reads (and writes)). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Chou and Joshi to use the partitions of Yang so to improve or optimize the overall performance of a storage system and/or ensure fairness to storage clients (Yang, Paragraph [0036]).
Regarding claim 14, claim 14 is the method claim associated with claim 7. Since Chou, Joshi, and Yang teach all the limitations to claim 7, they also teach all the limitations to claim 14; therefore the rejection to claim 7 also applies to claim 14.
Regarding claim 20, claim 20 is the system claim associated with claim 7. Since Chou, Joshi, and Yang teach all the limitations to claim 7 and Chou further teaches a memory device having an associated logical address space arranged in a plurality of partitions; and a processing device, operatively coupled with the memory device (Fig. 1 and Paragraphs [0016]-[0017] and [0020], as stated in the rejection to claim 1, the memory that is coupled to the controller (processing device) is shown to be divided into several namespaces), they also teach all the limitations to claim 20; therefore the rejections to claim 7 also applies to claim 20.
Response to Arguments
Applicant’s arguments, filed 5/22/2026, with respect to the rejections of claims 1-20 under USC 102 and 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new grounds of rejection is made in view of Chou and Joshi.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/NICHOLAS A. PAPERNO/Examiner, Art Unit 2132
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