The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are presented for examination
Claim Interpretation - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
Claim 9 limitation means for decoding multibit data words in a serial datastream received from a data communication link in accordance with timing provided by a bit clock signal has/have been interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because it uses/they use a generic placeholder means for coupled with functional language decoding multibit data words in a serial datastream received from a data communication link in accordance with timing provided by a bit clock without reciting sufficient structure to achieve the function. Furthermore, the generic placeholder is not preceded by a structural modifier.
the limitation means for generating a parallel clock signal configured has/have been interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because it uses/they use a generic placeholder means for coupled with functional language generating a parallel clock signal configured without reciting sufficient structure to achieve the function. Furthermore, the generic placeholder is not preceded by a structural modifier.
the limitation a means for powering off the hardware macro as requested by executing a power down flow if the collected current environmental condition information of the hardware macro exceeds a configurable threshold has/have been interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because it uses/they use a generic placeholder means for coupled with functional language powering off the hardware macro as requested by executing a power down flow if the collected current environmental condition information of the hardware macro exceeds a configurable threshold without reciting sufficient structure to achieve the function. Furthermore, the generic placeholder is not preceded by a structural modifier.
Since the claim limitation(s) invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, claim(s) 23 has/have been interpreted to cover the corresponding structure described in the specification that achieves the claimed function, and equivalents thereof.
A review of the specification shows that the following appears to be the corresponding structure described in the specification for the 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph limitation: paragraph 0019 shows the structures or the steps mentioned above can be implemented in hardware, software, or a combination of both.
If applicant wishes to provide further explanation or dispute the examiner’s interpretation of the corresponding structure, applicant must identify the corresponding structure with reference to the specification by page and line number, and to the drawing, if any, by reference characters in response to this Office action.
If applicant does not intend to have the claim limitation(s) treated under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112 , sixth paragraph, applicant may amend the claim(s) so that it/they will clearly not invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, or present a sufficient showing that the claim recites/recite sufficient structure, material, or acts for performing the claimed function to preclude application of 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
For more information, see MPEP § 2173 et seq. and Supplementary Examination Guidelines for Determining Compliance With 35 U.S.C. 112 and for Treatment of Related Issues in Patent Applications, 76 FR 7162, 7167 (Feb. 9, 2011).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over Sugita (US Patent Application 20100027728) in the view of Ware (US Patent Application 20110239031).
As per claim 1, Sugita teaches a communication interface circuit [220, fig. 6], comprising: 19040704
a deserializer [138, fig. 3] configured to convert a serial datastream received from a data communication link to multibit data words and to output the multibit data words in accordance with timing provided by a parallel clock signal [0073-0074, as shown in figure 3 an explained from the listed paragraphs serial data is received from serializer 134 where it is converted to parallel data by reserialize 138 that provide parallel data output based on the timing of the clock generator 178. For example, the serial signal is transmitted to the deserializer 138 by the differential transmission method according to LVDS. The serial signal is received by the receiver 172. The serial signal that is received by the receiver 172 is input to the decoder 174 and to the clock regeneration portion 178. The decoder 174 detects the beginning portion of the data by referring to the header in the input serial signal and inputs the signal to the S/P conversion portion 176. The S/P conversion portion 176 converts the input serial signal into the parallel signal (P-DATA). The parallel signal that has been converted by the S/P conversion portion 176 is output to the LCD 104].
a clock generation circuit [178, fig. 3] configured to generate the parallel clock signal by dividing a bit clock signal that is coupled to a clock input of the deserializer [0074, as pointed out the clock generator 178 is used to generate a parallel clock. For example, the clock regeneration portion 178 uses the built-in PLL portion 180 to regenerate the parallel signal clock from the serial signal clock by referring to a reference clock].
Sugita does not teach a synchronization circuit configured to: suppress output of the parallel clock signal when the data communication link is idle for a predefined first period of time; and re-establish output of the parallel clock signal after a predefined second period of time that follows detection of a pulse on the data communication link, wherein the clock generation circuit is reset when the pulse is detected on the data communication link.
However, Ware teaches a synchronization [10, fig. 1A] circuit configured to:
suppress output of the parallel clock signal when the data communication link is idle for a predefined first period of time [0047, 0051, 0057, as pointed out and shown in figure 1B, during the idle period the clock can be sopped and restart during normal operation. For example, a strobeless synchronous memory system that permits mesochronous transmit and receive clocks to be stopped and restarted during idle periods between memory access transactions is disclosed in several embodiments].
re-establish output of the parallel clock signal after a predefined second period of time that follows detection of a pulse on the data communication link [0057, as shown in figure 1B, below follow a period of no activity, then after that period with normal activity, the clock can then start. For example, assuming that a final memory transaction is commenced at clock cycle "0", the power-mode controller notes the empty transaction queue and begins counting clock cycles until a time at which internal operations of the memory device and controller-side I/O circuitry are complete. In this example, that time occurs 24 system-clock cycles after the transaction is commenced, and thus at system clock cycle 24. Shortly thereafter, in this case, long enough to ensure transmission of a final no-operation (NOP) command to the memory device, the system clock and controller I/O clocks are stopped cleanly and remain in a logic high or low state].
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wherein the clock generation circuit is reset when the pulse is detected on the data communication link [0057, a pointed out above, when the data is detected the clock started or reset. For example, in this example, a transaction is queued sometime shortly before system clock cycle 44. Accordingly, the power-mode controller, detecting the queued transaction, restarts the signaling clocks (the system clock and controller-side I/O clocks) at clock cycle 44, enabling a no-operation command to be sent to the memory device, and thereafter permitting the active command transfer shown, in this example, as an activation command directed to a selected bank (B) of the core storage array].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the design of Sugita to include the method of Ware in order to add a circuit that can enable and disable the clock when data is detected in the interface. Doing so, will enable the system to manage power consumption.
As per claim 2, Sugita teaches he clock generation circuit comprises a clock divider configured to count cycles of the bit clock signal [0074, as shown in figure 1, clock 178 is dividing the clock received from the reference clock and or line 173 and also provide clock signal to circuit 182].
As pe claim 3, Sugita teaches a number of the cycles of the bit clock signal counted by the clock divider corresponds to a number of serial bits used to generate a single multibit data word [0072, 0094 as pointed out timing control portion control the timing of the clock].
As per claim 4, Sugita does not teach the first period of time is defined as a number of cycles of the parallel clock signal.
However, Ware teaches the first period of time is defined as a number of cycles of the parallel clock signal [0057, count the cycle of the clock for example sixteen clock cycles].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the design of Sugita to include the method of Ware to provide a circuit that can count the clock cycles and make determination.
As per claim 5, Sugita does not teach the second period of time is defined as a number of cycles of the parallel clock signal.
However, Ware teaches the second period of time is defined as a number of cycles of the parallel clock signal [0057, specific cycles the clock start and stop].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the design of Sugita to include the method of Ware to provide a circuit that can count the clock cycles and make determination.
As per claim 6, Sugita does not teach the second period of time is greater than one cycle of the parallel clock signal.
However, Ware teaches the second period of time is greater than one cycle of the parallel clock signal [0057, multiple clock cycles are identified where for example a 44 clock cycles and a 24 clocks cycles].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the design of Sugita to include the method of Ware to provide a circuit that can count the clock cycles and make determination.
As per claim 7, Sugita does not teach the pulse has a duration that is defined as a number of cycles of the bit clock signal.
However, Ware teaches the pulse has a duration that is defined as a number of cycles of the bit clock signal [0142, pulse duration].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the design of Sugita to include the method of Ware to provide a circuit that can count the clock cycles and make determination.
As per claim 8, Sugita does not teach the pulse is detected in a pattern of bits clocked through the deserializer.
However, Ware teaches the pulse is detected in a pattern of bits clocked through the deserializer [0093, pattern of detection of the pulse].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the design of Sugita to include the method of Ware to provide a circuit that can count the clock cycles and make determination.
Claim Rejections - 35 USC § 103
Claims 9-20 are rejected under 35 U.S.C. 103 as being unpatentable over Sugita (US Patent Application 20100027728) in the view of Shivnaraine (US Patent Application 20260003388).
As per claim 9, Sugita teaches an apparatus [130, fig. 3], comprising:
means for decoding multibit data words in a serial datastream received from a data communication link in accordance with timing provided by a bit clock signal [0073-0074, as shown in figure 3 an explained from the listed paragraphs serial data is received from serializer 134 where it is converted to parallel data by reserialize 138 that provide parallel data output based on the timing of the clock generator 178. For example, the serial signal is transmitted to the deserializer 138 by the differential transmission method according to LVDS. The serial signal is received by the receiver 172. The serial signal that is received by the receiver 172 is input to the decoder 174 and to the clock regeneration portion 178. The decoder 174 detects the beginning portion of the data by referring to the header in the input serial signal and inputs the signal to the S/P conversion portion 176. The S/P conversion portion 176 converts the input serial signal into the parallel signal (P-DATA). The parallel signal that has been converted by the S/P conversion portion 176 is output to the LCD 104].
means for generating a parallel clock signal configured to [0074, as pointed out the clock generator 178 is used to generate a parallel clock. For example, the clock regeneration portion 178 uses the built-in PLL portion 180 to regenerate the parallel signal clock from the serial signal clock by referring to a reference clock]:
Sugita does not teach suppress output of the parallel clock signal when the data communication link is idle for a predefined first period of time;
reestablish output of the parallel clock signal after a predefined second period of time that follows detection of a pulse on the data communication link,
wherein the multibit data words are decoded in accordance with timing provided by the parallel clock signal.
However, Shivnaraine teaches suppress output of the parallel clock signal when the data communication link is idle for a predefined first period [W=10: 0100] of time [0037, 0101, 0104, fig. 7, as pointed out and shown in figure 7 when the data link is idle, the clock is disable. For example, this allows the clock to be shut off when the data link is idle, saving power. In turn, the clock signal can inform a receiver whether the data link is idle or active, thereby eliminating the need for a separate valid signal and saving space. Where figure 7 at the bottom shows the clock diagram when the clock is enabled and disable at specific time based on link data].
reestablish output of the parallel clock signal after a predefined second period of time [detected as ON, W=10 cycles of txSClk3: 0102] that follows detection of a pulse on the data communication link [0037, 0102, as pointed out when there is data during the specific time period it is detected where transmission can be resumed. For example, parallel clock cycle 713A operates similarly to cycle 711A. Because txV2 is detected as ON, W=10 cycles of txSClk3 and txD3[ ] are outputted responsive to edge 723, as shown by arrows 733, 743. Thus, parallel data word D2 is transmitted across the illustrated data link as 14 lanes of serial data].
wherein the multibit data words are decoded in accordance with timing provided by the parallel clock signal [0131, asp out the data is decoded to identify valid and invalid bits. For example, Correspondingly, deserializer 1230 can decode valid bits 1281, 1283, 1285 to recognize subsequent bits 1282, 1284, 1286 as valid, and can decode bit 1287 to recognize that there is no valid data for parallel cycle P+1, and similarly for other parallel cycles up to P+Q].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify of Sugita to include the method of Shivnaraine in order to enable and disable output data from the serializer. Doing so, enable power management for the overall system.
As per claim 16, Sugita teaches a method [900, fig. 9] for synchronizing a communication interface circuit [220, fig. 6], comprising:
generating multibit data words by converting a serial datastream received from a data communication link in accordance with timing provided by a bit clock signal [0073-0074, as shown in figure 3 an explained from the listed paragraphs serial data is received from serializer 134 where it is converted to parallel data by reserialize 138 that provide parallel data output based on the timing of the clock generator 178. For example, the serial signal is transmitted to the deserializer 138 by the differential transmission method according to LVDS. The serial signal is received by the receiver 172. The serial signal that is received by the receiver 172 is input to the decoder 174 and to the clock regeneration portion 178. The decoder 174 detects the beginning portion of the data by referring to the header in the input serial signal and inputs the signal to the S/P conversion portion 176. The S/P conversion portion 176 converts the input serial signal into the parallel signal (P-DATA). The parallel signal that has been converted by the S/P conversion portion 176 is output to the LCD 104].
dividing the bit clock signal to obtain a parallel clock signal [0074, as pointed out the clock generator 178 is used to generate a parallel clock. For example, the clock regeneration portion 178 uses the built-in PLL portion 180 to regenerate the parallel signal clock from the serial signal clock by referring to a reference clock]:
Sugita does not teach suppressing output of the parallel clock signal when the data communication link is idle for a predefined first period of time;
reestablishing output of the parallel clock signal after a predefined second period of time that follows detection of a pulse on the data communication link; a
outputting the multibit data words in accordance with timing provided by the parallel clock signal.
However, Shivnaraine teaches suppressing output of the parallel clock signal when the data communication link is idle for a predefined first period of time [0037, 0101, 0104, fig. 7, as pointed out and shown in figure 7 when the data link is idle, the clock is disable. For example, this allows the clock to be shut off when the data link is idle, saving power. In turn, the clock signal can inform a receiver whether the data link is idle or active, thereby eliminating the need for a separate valid signal and saving space. Where figure 7 at the bottom shows the clock diagram when the clock is enabled and disable at specific time based on link data].
reestablishing output of the parallel clock signal after a predefined second period of time that follows detection of a pulse on the data communication link [0037, 0102, as pointed out when there is data during the specific time period it is detected where transmission can be resumed. For example, parallel clock cycle 713A operates similarly to cycle 711A. Because txV2 is detected as ON, W=10 cycles of txSClk3 and txD3[ ] are outputted responsive to edge 723, as shown by arrows 733, 743. Thus, parallel data word D2 is transmitted across the illustrated data link as 14 lanes of serial data].
outputting the multibit data words in accordance with timing provided by the parallel clock signal [0131, asp out the data is decoded to identify valid and invalid bits. For example, Correspondingly, deserializer 1230 can decode valid bits 1281, 1283, 1285 to recognize subsequent bits 1282, 1284, 1286 as valid, and can decode bit 1287 to recognize that there is no valid data for parallel cycle P+1, and similarly for other parallel cycles up to P+Q].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify of Sugita to include the method of Shivnaraine in order to enable and disable output data from the serializer. Doing so, enable power management for the overall system.
As pe claim 10, Sugita teaches the means for generating a parallel clock signal comprises a clock divider configured to count cycles of the bit clock signal that has a period that corresponds to a number of cycles of the bit clock signal used to capture a number of serial bits in a single multibit data word [0074, as pointed out, the clock regeneration portion 178 uses the built-in PLL portion 180 to regenerate the parallel signal clock from the serial signal clock by referring to a reference clock. Where the timing control 182 can be viewed as a counter that control or count the clock signals].
As per claim 11, Sugita does not teach the first period of time is defined as a first number of cycles of the parallel clock signal.
However, Shivnaraine teaches the first period of time is defined as a first number of cycles of the parallel clock signal [0100, duration number of cycles. For example, a duration equal to five periods of txSClk2, which is W=10 edges of txSClk2].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify of Sugita to include the method of Shivnaraine in order to enable and disable output data from the serializer. Doing so, enable power management for the overall system.
As per claim 12, Sugita does not teach the second period of time is defined as a second number of cycles of the parallel clock signal.
However, Shivnaraine teaches the second period of time is defined as a second number of cycles of the parallel clock signal [0232, having specific duration like W which means valid data. For example, defining parallel clock cycles, each having duration equal to W cycles of the serial clock; to receive a valid signal indicating validity of parallel data provided to the N serializers for each of the parallel clock cycles].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify of Sugita to include the method of Shivnaraine in order to enable and disable output data from the serializer. Doing so, enable power management for the overall system.
As per claim 13, Sugita teaches decoding multibit data words comprises a deserializer clocked by the bit clock signal [0073, the deserializer used serial input data then convert the received serial into to parallel].
As per claim 14, Sugita teaches the pulse is detected in a pattern of bits in the serial datastream [0073, as pointed out, the decoder 174 detects the beginning portion of the data by referring to the header in the input serial signal and inputs the signal to the S/P conversion portion 176].
As per claim 15, Sugita does not teach the pulse has a duration that is defined as a number of cycles of the bit clock signal.
However, Shivnaraine teaches the pulse has a duration that is defined as a number of cycles of the bit clock signal
[0232, having specific duration like W which means valid data. For example, defining parallel clock cycles, each having duration equal to W cycles of the serial clock; to receive a valid signal indicating validity of parallel data provided to the N serializers for each of the parallel clock cycles].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify of Sugita to include the method of Shivnaraine in order to enable and disable output data from the serializer. Doing so, enable power management for the overall system.
As per claims 17-20, they do not teach or further define over the limitations recited in the rejected claims above. Therefore, claims 17-20 are also rejected as being unpatentable over Sugita in view of Shivnaraine for the same reasons set forth in the rejected claims above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim (US 20180156870) teaches Test Apparatus
Sherwood (US 20130221215) teaches Timing Device and Method.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VOLVICK DEROSE whose telephone number is (571)272-6260. The examiner can normally be reached on Monday-Friday 9AM-6PM.
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/VOLVICK DEROSE/Primary Examiner, Art Unit 2176
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