DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/20/25 has been considered by the examiner.
Drawings
The drawings received on 01/29/25 are acceptable.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-14 are rejected under 35 U.S.C. 103 as being unpatentable over McCaughan et al. (US 2016/0028403 A1) in view of Goupil et al. (US 2011/0254053 A1).
Regarding claim 1, McCaughan et al. discloses the circuit of claim 1, but fails to disclose wherein the gate component is separated from the superconductor component by an electrically-insulating, thermally-conductive coupling component. McCaughan et al. disclose an electric circuit (para [0001]- The technology relates to integrated, superconducting, three-terminal devices that operate like transistors and to related circuit elements including logic), comprising: a superconductor (201) component (222) having a first terminal at a first end (220) and a second terminal at a second end (240) (Fig. 2A; para [0071]- a superconducting, three-terminal device 200 may be formed from a single layer of superconducting material 201... two main terminals 220, 240 may connect to the main channel 222.); a gate component (212) thermally-coupled to the superconductor component at a first location (proximate to 215) between the first terminal (220) and the second terminal (240), wherein the gate component (212) is thermally-coupled via a first section (215) of the gate component (Fig. 2A shows gate 212 between the first terminal 220 and the second terminal 240; para (0071]- The gate channel 212 may connect to the main channel 222 in a “T" configuration, though other configurations may be used: para [0072]- a patterned superconducting nanowire or nanostrip 215 within the gate channel 212, and located near the main channel 222. The nanostrip may comprise tine-narrowing geometries, and may have low thermal dissipation to the surrounding environment (e.g., to air or material adjacent the gate channel)... The nanostrip may be referred to as a "choke" or "constriction"; para [0103]- If the gate current | is increased to values greater than the critical current of the choke, then a hotspot forms in the choke and the system transitions from S1 to S2 (Therefore, the gate is thermally coupled via choke 215).); and wherein the gate component (212) has a smallest width (Wck) at the first section (215) so as to focus resistive heating toward the superconductor component (Fig. 2A shows gate 212 has the smallest width Wek; Para [0139]- The hotspot appears in FIG. 7B as the darkened area at the choke, and represents a region of increased resistance. The extent of the hotspot along the channel was about initially about three times the narrowest width of the choke). Goupil, drawn to superconductor transistor, discloses a gate component (8) is separated from the superconductor component (12) by an electrically-insulating, thermally-conductive coupling component (10) (Fig. 1; para [0037]- The gate electrode 8 is electrically insulated from the remainder of the transistor by a gate insulating layer 10; para [0041]- The insulating layer 10 is manufactured in a thermal oxide, e.g. silicon dioxide (SiO2). (It is noted SiO2 has a thermal! conductivity around 1.3 W/m. K which can conduct heat).). It would have been obvious to a person having ordinary skill in the art at the time of the filing the invention to combine the component disclosed by Goupil to the circuit disclosed by McCaughan et al. to allow control over strong currents and to increase the current gain between the source and the drain of the circuit (See Goupil, para [0007]).
Regarding claim 2, McCaughan et al. disclose the circuit of claim 1, McCaughan et al further discloses wherein the gate component (212) has a first end (the part near 220) and a second end (the part near 240), opposite the first end, and wherein the gate component is tapered between the first end and the first section (215) and between the second end and the first section (215) (Fig. 2A shows the gate 212 has a first end near 220 opposite to a second end near 240, and gate 212 tapered between first end to choke 25, and between second end to choke 215; para [0072)- the choke 215 is proximal an intersection of the gated channel 212 with the main channel! 222 and located between the main terminals 220, 240; para [0075} the choke 215 may be located proximal to the main channel 222).
Regarding claim 3, McCaughan et al. disclose the circuit of claim 1. McCaughan et al further discloses wherein the gate component has a non-zero resistance (para (0119]- the gate terminal 210 may be formed of gold, aluminum, titanium, copper, or any combination thereof. The gate terminal, in some cases, may be a superconducting material, a non-superconducting material, a semiconducting material, or any
suitable conductor that can carry current into the device).
Regarding claim 4, McCaughan et al. disclose the circuit of claim 1. McCaughan et al. discloses wherein the gate component is composed of a metal and/or semiconductor (see paragraph 83).
Regarding claim 5, McCaughan et al. disclose wherein the thermally-conductive electrically insulating coupling component is composed of aluminum nitride (see paragraph 119).
Regarding claim 6, McCaughan et al. disclose the circuit of claim 1. McCaughan et al further discloses wherein the electric circuit includes: a first layer comprising the superconductor component (para [0071]- three-terminal device 200 may be formed from a single layer of superconducting material 201), but fails to disclose a first layer comprising the superconductor component; a second layer comprising the gate component; and a third layer arranged between the first layer and the second layer, third layer comprising a thermal coupling component. Goupil, drawn to superconductor transistor, discloses a first layer (12) comprising the superconductor component; a second layer (8) comprising the gate component; and a third layer (10) arranged between the first layer (12) and the second layer (8), third layer (10) comprising a thermal coupling component (Fig, 1shows the layer 10 arranged between layer 12 and layer 8; para [0037)- a field-effect superconductor transistor 2 comprises a source electrode 4, a drain electrode 6 and a gate electrode 8. The gate electrode 8 is electrically insulated from the remainder of the transistor by a gate insulating layer 10. The source 4 and drain 6 electrodes are connected by a superconducting channel 12; para [0041)- The insulating layer 10 is manufactured in a thermal oxide, e.g. silicon dioxide (SiO2). (It is noted SiO2 has a thermal conductivity around 1.3 W/m. K which can conduct heat).). It would have been obvious to a person having ordinary skill in the art at the time of filing the invention to combine the structure disclosed by Goupil to the circuit disclosed by McCaughan et al to allow control over strong currents and to increase the current gain between the source and the drain of the circuit (See Goupil, para [0007})
Regarding claim 7, McCaughan et al in view of Goupil discloses the circuit of claim 6. Goupil further discloses wherein the first (12), second (8) and third (10) layers are vertically stacked (Fig. 1 shows layers 12, 8 and 10 are vertically stacked; para (0037]- a field-effect superconductor transistor 2 comprises a source electrode 4, a drain electrode 6 and a gate electrode 8. The gate electrode 8 is electrically insulated from the remainder of the transistor by a gate insulating layer 10. The source 4 and drain 6 electrodes are connected by a superconducting channel 12).
Regarding claim 8, McCaughan et al. disclose the circuit of claim 1, McCaughan et al further comprising a first current source coupled to the superconductor component (222), the first current source configured to supply a first current to the superconductor component (222) (Fig. 2A; para [0074]- The term "downstream" is used with reference to the direction of current flow in the main channel 222; para [0080]- the main current-carrying terminals 220, 240 may be labeled "C, “and "C .,", respectively. In some cases, the main terminals may be labeled “D" or “drain” and "S" or “source).
Regarding claim 9, McCaughan et al. disclose the circuit of claim 8. McCaughan et al further discloses where the first current is adapted to maintain the superconductor component in a superconducting state in the absence of heat from the gate component (para (0087)-little or no bias current is applied to the gate terminal (therefore, no heat generated from the gate component), and current applied to the main channel! 222 will flow through the main channel without resistance since the main channel is superconducting).
Regarding claim 10, McCaughan et al. disclose the circuit of claim 8. McCaughan et al further discloses further comprising a component (112) coupled in parallel with the superconductor component (110) such that at least a portion of the first current is redirected to the component (112) while the superconductor component (110) is in a non-superconducting state (Fig.1; para [0004]- parallel channels 110, 112; para [0005]-Since the first channel 110 is biased near its critical current level, the resulting current in the first channel then exceeds the critical current for the first channel. Because of the excess current, superconductivity is no longer supported by the first channel, so that current from that channel is diverted to the second channel 112). Massachusetts fails to disclose the parallel channel is a non-superconductor. Goupil, drawn to superconductor transistor, discloses a non-superconductor component (14) coupled in parallel with the superconductor component (12) (Fig. 1; para [0039}- A layer of semiconductor material 14 is arranged between the channel 12 and the insulating layer 10 of the gate electrode.). It would have been obvious to a person having ordinary skill in the art at the time of filing the invention to combine the non-superconductor component disclosed by Goupil to the circuit disclosed by McCaughan et al to allow control over strong currents and to increase the current gain between the source and the drain of the circuit (See Goupil, para [0007)).
Regarding claim 11, McCaughan et al. disclose the circuit of claim 1. McCaughan et al further discloses further comprising a second current source coupled to the gate component, the second current source configured to selectively supply a second current, wherein the second current is adapted so as to cause the gate component to generate sufficient heat at the first section to cause the superconductor component to transition from a superconducting state to a non-superconducting state (para [0089]- Applying an appropriate gate current can cause the device 200 to pass through a transition state (as depicted in FIG. 3B) to a resistive or normal ohmic conduction state,
depicted in FIG. 3C. The transition state initiates when a hotspot 218 forms at the choke 215. To toggle the main channel 222 to an ohmic conduction state, a signal (e.g., gate current |) may be applied to the gate channel 212, such that the critical current density J is exceeded at the choke 215).
Regarding claim 12, McCaughan et al. disclose the circuit of claim 1. McCaughan et al further disclose wherein the superconductor component has a width in a range from 100 nanometers to 50 microns (see paragraph 78).
Regarding claim 13, McCaughan et al. discloses the circuit of claim 1, but fails to disclose wherein the gate component is thermally-coupled to the thermally-conductive electrically-insulating coupling component via a first section of the gate component. ). Goupil, drawn to superconductor transistor, discloses a gate component (8) is separated from the superconductor component (12) by an electrically-insulating, thermally-conductive coupling component (10) (Fig. 1; para [0037]- The gate electrode 8 is electrically insulated from the remainder of the transistor by a gate insulating layer 10; para [0041]- The insulating layer 10 is manufactured in a thermal oxide, e.g. silicon dioxide (SiO2). (It is noted SiO2 has a thermal! conductivity around 1.3 W/m. K which can conduct heat).). It would have been obvious to a person having ordinary skill in the art at the time of the filing the invention to combine the component disclosed by Goupil to the circuit disclosed by McCaughan et al. to allow control over strong currents and to increase the current gain between the source and the drain of the circuit (See Goupil, para [0007]).
Regarding claim 14, McCaughan et al. disclose the circuit of claim 1. McCaughan et al further disclose wherein the gate component has a smallest width as the first section so as to focus resistive heating toward the superconductor component (see paragraph 78).
Claims 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over McCaughan et al. (US 2016/0028403 A1) and Goupil et al. (US 2011/0254053 A1).
Regarding claim 15. McCaughan et al. disclose the claimed invention except for a constricted region adjacent to the first section of the gate component. It would have been obvious matter of design choice to constricted region adjacent to the first section of the gate component, since such a modification would have involved a mere change is the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Regarding claim 16. McCaughan et al. disclose the claimed invention except for a superconductive component shaped so as to promote self-heating in response to transitioning to the non-superconducting state. It would have been obvious matter of design choice to superconductive component shaped so as to promote self-heating in response to transitioning to the non-superconducting state, since such a modification would have involved a mere change is the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Regarding claim 17. McCaughan et al. disclose the claimed invention except wherein the superconductor component has a non-linear shape. It would have been obvious matter of design choice superconductor component has a non-linear shape, since such a modification would have involved a mere change is the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Najafi et al. (US 12,245,524 B2) disclose a superconducting switch.
Najafi et al. (US 11,980,105 B2) disclose a superconducting switch.
Najafi et al. (US 10,461,445 B2) disclose a method and device for impedance multiplication.
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/ADOLF D BERHANE/Primary Examiner, Art Unit 2838
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