Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the application filed on 01/30/2025.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/30/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The disclosure is objected to because of the following informalities: In paragraph [0002], “a flyback converter that having an auxiliary switch and an absorb capacitor in the primary side besides the main power switch” appears that it should read as “a flyback converter that has an auxiliary switch and an absorb capacitor in the primary side besides the main power switch”, because the phrase is grammatically incorrect.
In paragraph [0025], “charging the floating capacitor by the power supply voltage when the main power switch is turned on. and” appears that it should read as “charging the floating capacitor by the power supply voltage when the main power switch is turned on; and”, because a sentence-ending period appears before the conjunction joining the recited steps. Appropriate correction is required.
Claim Objections
Claims 5, 11, and 17 are objected to because of the following informalities: Regarding claim 5, in line 2, “the current mirror circuit having” appears that it should read as “the current mirror circuit has”;
in line 4, “the connect switch” appears that it should read as “the connecting switch”, because claim 2 recites “a connecting switch” and there is no antecedent basis for a “connect switch”.
Regarding claim 11, in line 2, “the current mirror circuit having” appears that it should read as “the current mirror circuit has”;
in line 4, “the connect switch” appears that it should read as “the connecting switch”, because claim 8 recites “a connecting switch” and there is no antecedent basis for a “connect switch”.
Regarding claim 17, in line 2, “the current mirror circuit having” appears that it should read as “the current mirror circuit has”;
in line 4, “the connect switch” appears that it should read as “the connecting switch”, because claim 14 recites “a connecting switch” and there is no antecedent basis for a “connect switch”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over EVL8017 (Monolithic Power Systems, “EVL8017-L-00B – IEEE 802.3af-Compliant, PoE PD Solution with PSR Flyback Converter Evaluation Board,” Rev. 1.0, November 18, 2021) in view of Liu et al. (US Patent Application Publication US 2020/0007041 A1, hereinafter “Liu”), further in view of Koo et al. (US Patent Application Publication US 2018/0069480 A1, hereinafter “Koo”), and further in view of Li (US Patent Application Publication US 2019/0238051 A1).
Regarding claim 1, EVL8017 discloses (see Fig. 3) an active clamp flyback converter (see p. 1 of EVL8017 “The MP8017 flyback converter is specifically designed for active-clamp, primary-side regulation (PSR) in a flyback topology”), comprising: a transformer (T1), including a primary winding (NP) configured to receive an input voltage (the VBUS rail at pins 18 and 19), and a secondary winding (NS) configured to generate an output voltage (VOUT, rectified by D1); and an IC chip (U1, MP8017, in a QFN-19 package), having: a first pin (SW, pin 14), coupled to the primary winding (SW pin 14 is coupled to the primary winding NP of T1); a second pin (SNBR, pin 17), a) configured to receive the input voltage via a buffer capacitor (C4, 4.7 µF, is coupled between the VBUS rail and SNBR pin 17); a third pin (BST, pin 13), coupled to the first pin via a floating capacitor (C6, 0.22 µF, is coupled between BST pin 13 and SW pin 14); and a fourth pin (VCC, pin 10), configured to provide a power supply voltage to the IC chip (VCC pin 10 is bypassed to PGND by C8, 2.2 µF).
EVL8017 does not disclose a first pin, coupled to a main power switch and an auxiliary switch, and a second pin, b) coupled to the first pin via the auxiliary switch.
However, Liu teaches (see Fig. 2 and Fig. 4) a first pin, coupled to a main power switch and an auxiliary switch (the node at the drain of power switch transistor S1 and the source of active clamp switch transistor S2) (see [0022] of Liu “A negative plate for bootstrap capacitor CB connects to the source of active clamp switch transistor S2 and to the drain of power switch transistor S1”), and a second pin, b) coupled to the first pin via the auxiliary switch (the positive plate of active clamp capacitor Ca is coupled to that node through active clamp transistor S2) (see [0022] of Liu “Active clamp transistor S2 couples between the drain of power switch transistor S1 and a positive plate for active clamp capacitor Ca”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the active clamp flyback converter of EVL8017 to include a first pin, coupled to a main power switch and an auxiliary switch, and a second pin, b) coupled to the first pin via the auxiliary switch, as taught by Liu, because it can store and reclaim the leakage energy of the transformer in the buffer capacitor instead of dissipating it (see [0003] of Liu “In active clamp operation, the leakage energy in the transformer is stored and reclaimed in an active clamp capacitor that is coupled to a terminal for the power switch transistor through an active clamp switch transistor”).
EVL8017 does not disclose a first charge path from the power supply voltage to the floating capacitor is enabled, and a second charge path from the second pin to the floating capacitor is enabled.
However, Liu teaches (see Fig. 2 and Fig. 4) a first charge path from the power supply voltage to the floating capacitor is enabled (diode D1 is forward biased so that power supply capacitor VCC charges the positive plate of bootstrap capacitor CB) (see [0022] of Liu “As part of the first charging path, a diode D1 is forward biased by the power supply voltage VCC so as to charge a driver power supply voltage across a bootstrap capacitor CB”), and a second charge path from the second pin to the floating capacitor is enabled (transistor S3 is cycled on so that a charging path is activated from the positive plate of active clamp capacitor Ca, which couples to the input power rail supplying the input voltage Vin, to the positive plate of bootstrap capacitor CB) (see [0025] of Liu “Thus, when transistor S3 is cycled on, a charging path is activated from active clamp capacitor Ca through resistor R7, transistor S3, and resistor R7 to charge bootstrap capacitor CB”, Examiner’s Note: the second recitation of “resistor R7” appears to be a typographical error for “resistor R6,” which [0025] of Liu identifies as coupling the source of transistor S3 to the positive plate of bootstrap capacitor CB).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the active clamp flyback converter of EVL8017 wherein a first charge path from the power supply voltage to the floating capacitor is enabled, and a second charge path from the second pin to the floating capacitor is enabled, as taught by Liu, because it can recover the leakage inductance energy accumulated on the buffer capacitor and use that energy to sustain the voltage across the floating capacitor, instead of allowing the energy to raise the voltage on the buffer capacitor to a damaging level (see [0005] of Liu “The resulting voltage rise across active clamp capacitor Ca may damage it and cause safety issues”).
EVL8017 does not disclose when the main power switch is turned on, a first charge path from the power supply voltage to the floating capacitor is enabled, and the first charge path is disabled.
However, Li teaches (see Fig. 3) when the main power switch is turned on, a first charge path from the power supply voltage to the floating capacitor is enabled (when the third power switch 13 is turned on, the first switching node SW1 is pulled to the reference ground and power supply VCC charges the first bootstrap capacitor 23 through the first charging switch 21) (see [0034] of Li “The first switching node SW1 is connected to the reference ground, and the power supply VCC may be configured to charge the first bootstrap capacitor 23 via the first charging switch 21 to refresh the first bootstrap voltage signal VBST1”), and the first charge path is disabled (the first charging switch 21 opens whenever the third power switch 13 opens) (see [0031] of Li “on and off switching of the first charging switch 21 is simultaneous with on and off switching of the third power switch 13”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the active clamp flyback converter of EVL8017 wherein when the main power switch is turned on, a first charge path from the power supply voltage to the floating capacitor is enabled, and the first charge path is disabled, as taught by Li, because it can confine charging of the floating capacitor to the interval during which the node shared by the floating capacitor and the main power switch is held at the reference ground, so that the power supply voltage is not exposed to the elevated voltage present at that node while the main power switch is off.
EVL8017 does not disclose when a voltage at the second pin is higher than a reference voltage, the main power switch is turned off.
However, Koo teaches (see Fig. 1 and Fig. 3) when a voltage at the second pin is higher than a reference voltage (comparator 340 compares the voltage sensed at HV terminal 181, which is connected to the second terminal of clamp capacitor 153, with threshold voltage VTH) (see [0031] of Koo “In this manner, ACF controller 180 uses OVP circuit 188 to detect when the value of VCLAMP is too high”), the main power switch is turned off (low side switch 151 is deactivated) (see [0048] of Koo “In one example of the OVP operation, ACF controller 180 deactivates both switches 151 and 152 and otherwise shuts down power supply system 100 to protect the system and the load”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the active clamp flyback converter of EVL8017 wherein when a voltage at the second pin is higher than a reference voltage, the main power switch is turned off, the first charge path is disabled, and a second charge path from the second pin to the floating capacitor is enabled, as taught by Koo, because it can hold the voltage at the second pin below the level at which the IC chip would be damaged (see [0003] of Koo “This buildup in voltage across the clamp capacitor will eventually cause the ACF converter to be damaged or otherwise to fail”), while recovering the charge accumulated at that pin into the floating capacitor instead of dissipating it, the transistor that establishes the second charge path in Liu already being switched by the output of a comparator that compares a sensed voltage with a reference voltage (see [0026] of Liu “To control whether transistor S4 is on or off, a comparator C1 compares a reference voltage Vref to a divided version of the driver power supply voltage stored across bootstrap capacitor CB”), and Koo already conducting the charge accumulated at the second pin away through a switch closed by the output of such a comparator (see [0043] of Koo “In response to the activation of the OVP signal, switch 310 closes and starts to discharge clamp capacitor 153”) (Examiner’s Note: turning off the main power switch necessarily disables the first charge path, which claim 1 recites as being enabled when the main power switch is turned on).
Regarding claim 2, EVL8017 does not disclose wherein the IC chip further comprises: a connecting switch, coupled between the second pin and the third pin.
However, Liu teaches (see Fig. 4) a connecting switch, coupled between the second pin and the third pin (NMOS transistor S3 is coupled between the positive plate of active clamp capacitor Ca and the positive plate of bootstrap capacitor CB) (see [0025] of Liu “A source of the transistor S3 couples through a resistor R6 to the positive plate of bootstrap capacitor CB. A drain of transistor S3 couples through a resistor R7 to the positive plate of active clamp capacitor Ca”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the IC chip of EVL8017 to comprise a connecting switch, coupled between the second pin and the third pin, as taught by Liu, because it can establish the second charge path through an active device that conducts only when required, thereby avoiding the continuous resistive loss of a permanently conducting path (see [0025] of Liu “An active circuit embodiment for charge path circuit 205 in which the charge path circuit 205 comprises an NMOS transistor S3 such as shown in FIG. 4 for a flyback converter 400 avoids such resistive losses”).
EVL8017 does not disclose wherein the connecting switch is configured to be turned on when the voltage at the second pin is higher than the reference voltage.
However, Koo teaches (see Fig. 3) wherein the connecting switch is configured to be turned on when the voltage at the second pin is higher than the reference voltage (switch 310 is closed by the output of comparator 340, which compares the voltage sensed at HV terminal 181 with threshold voltage VTH) (see [0043] of Koo “In response to the activation of the OVP signal, switch 310 closes and starts to discharge clamp capacitor 153”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the IC chip of EVL8017 wherein the connecting switch is configured to be turned on when the voltage at the second pin is higher than the reference voltage, as taught by Koo, because it can transfer the charge accumulated at the second pin only when that pin reaches the voltage at which the IC chip would otherwise be placed at risk.
Regarding claim 3, EVL8017 does not disclose wherein the IC chip further comprises: a current source, series coupled with the connecting switch between the second pin and the third pin.
However, Li teaches (see Fig. 5) a current source (first current regulating circuit 49, which generates the first charging current signal i11), series coupled with the connecting switch (switch 471) between the second pin and the third pin (switch 471 and the first current regulating circuit 49 are coupled in series between the input voltage signal VIN and the first bootstrap node BST1) (see [0050] of Li “The switch 471 may have a first terminal configured to receive the input voltage signal VIN, a second terminal coupled to the first current regulating circuit 49 via the diode 481, and a control terminal configured to receive the logic signal CP11”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the IC chip of EVL8017 to comprise a current source, series coupled with the connecting switch between the second pin and the third pin, as taught by Li, because it can hold the charging current delivered through the connecting switch to a controlled magnitude and thereby prevent an excessive inrush current from being drawn when the connecting switch is turned on.
Regarding claim 4, EVL8017 does not disclose wherein the IC chip further comprises: a current source, configured to provide a current signal; and a current mirror circuit, configured to deliver the current signal to the floating capacitor when the connecting switch is turned on.
However, Li teaches (see Fig. 5 and Fig. 7) a current source (the source of bias current signal IB within the first subtracting circuit 61), configured to provide a current signal (bias current signal IB) (see [0066] of Li “The first subtracting circuit 61 may be configured to receive the first feedback signal iBST1_F, and conduct a subtraction operation to the first feedback signal iBST1_F and a bias current signal IB to generate a first difference signal IB-iBST1_F”); and a current mirror circuit (current mirror circuit 62), configured to deliver the current signal to the floating capacitor when the connecting switch is turned on (current mirror circuit 62 delivers the first charging current signal i11 to the first bootstrap node BST1, and the first current regulating circuit 49 generates no such current while switch 471 is off) (see [0053] of Li “When the first feedback signal iBST1_F or the second feedback signal iBST2_F is larger than the first refresh threshold iTH1, both the switch 471 and the switch 472 are turned off. The first current regulating circuit 49 is unable to generate the first charging current signal i11 and the second charging current signal i12”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the IC chip of EVL8017 to comprise a current source, configured to provide a current signal; and a current mirror circuit, configured to deliver the current signal to the floating capacitor when the connecting switch is turned on, as taught by Li, because it can replicate a single reference current onto the charging path without placing the reference current source itself at the elevated potential of the second pin.
Regarding claim 5, EVL8017 does not disclose wherein the current mirror circuit having an input terminal coupled to the current source, and an output terminal configured to provide a mirrored current proportional to the current signal when the connect switch is turned on, to charge the floating capacitor.
However, Li teaches (see Fig. 7) the current mirror circuit having an input terminal coupled to the current source (a first current terminal of current mirror circuit 62 receives the first difference signal IB-iBST1_F generated from bias current signal IB), and an output terminal configured to provide a mirrored current proportional to the current signal when the connect switch is turned on, to charge the floating capacitor (a second current terminal of current mirror circuit 62 is coupled to the first bootstrap node BST1 through diode 63 and provides the first charging current signal i11 mirrored from the first difference signal) (see [0066] of Li “a first current terminal configured to receive the first difference signal IB-iBST1_F, and a second current terminal coupled to the first bootstrap node BST1 through the diode 63. The current mirror circuit 62 may be configured to mirror the first difference signal IB-iBST1_F to provide the first charging current signal i11 at its second current terminal”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the IC chip of EVL8017 wherein the current mirror circuit having an input terminal coupled to the current source, and an output terminal configured to provide a mirrored current proportional to the current signal when the connect switch is turned on, to charge the floating capacitor, as taught by Li, because it can set the magnitude of the charging current by a single reference current while isolating that reference current from the charging path.
Regarding claim 6, EVL8017 does not disclose wherein the IC chip further comprises: a voltage converter, coupled to the fourth pin, to provide the power supply voltage.
However, Li teaches (see Fig. 13) a voltage converter (power supply generator 600), coupled to the fourth pin, to provide the power supply voltage (transistor 121 receives the input voltage signal VIN and provides the power supply VCC at its second terminal) (see [0076] of Li “the power supply generator 600 is illustrated as a low dropout linear regulator (LDO) comprising a transistor 121 and an error amplifier 122”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the IC chip of EVL8017 to comprise a voltage converter, coupled to the fourth pin, to provide the power supply voltage, as taught by Li, because it can derive a regulated low-voltage supply for the IC chip from the input voltage already present at the converter, so that no separate supply source is required.
Regarding claim 7, EVL8017 discloses (see Fig. 3) an IC chip (U1, MP8017, in a QFN-19 package) used in an active clamp flyback converter (see p. 1 of EVL8017 “The MP8017 flyback converter is specifically designed for active-clamp, primary-side regulation (PSR) in a flyback topology”), comprising: a first pin (SW, pin 14), a) configured to receive an input voltage via a primary winding (SW pin 14 is coupled to the primary winding NP of T1, whose opposite end is connected to the VBUS rail); a second pin (SNBR, pin 17), a) configured to receive the input voltage via a buffer capacitor (C4, 4.7 µF, is coupled between the VBUS rail and SNBR pin 17); a third pin (BST, pin 13), coupled to the first pin via a floating capacitor (C6, 0.22 µF, is coupled between BST pin 13 and SW pin 14); and a fourth pin (VCC, pin 10), configured to provide a power supply voltage to the IC chip (VCC pin 10 is bypassed to PGND by C8, 2.2 µF).
EVL8017 does not disclose a first pin, b) coupled to a main power switch and an auxiliary switch, and a second pin, b) coupled to the first pin via the auxiliary switch.
However, Liu teaches (see Fig. 2 and Fig. 4) a first pin, b) coupled to a main power switch and an auxiliary switch (the node at the drain of power switch transistor S1 and the source of active clamp switch transistor S2) (see [0022] of Liu “A negative plate for bootstrap capacitor CB connects to the source of active clamp switch transistor S2 and to the drain of power switch transistor S1”), and a second pin, b) coupled to the first pin via the auxiliary switch (the positive plate of active clamp capacitor Ca is coupled to that node through active clamp transistor S2) (see [0022] of Liu “Active clamp transistor S2 couples between the drain of power switch transistor S1 and a positive plate for active clamp capacitor Ca”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the IC chip of EVL8017 to include a first pin, b) coupled to a main power switch and an auxiliary switch, and a second pin, b) coupled to the first pin via the auxiliary switch, as taught by Liu, because it can store and reclaim the leakage energy of the transformer in the buffer capacitor instead of dissipating it (see [0003] of Liu “In active clamp operation, the leakage energy in the transformer is stored and reclaimed in an active clamp capacitor that is coupled to a terminal for the power switch transistor through an active clamp switch transistor”).
EVL8017 does not disclose a first charge path from the power supply voltage to the floating capacitor is enabled, and a second charge path from the second pin to the floating capacitor is enabled.
However, Liu teaches (see Fig. 2 and Fig. 4) a first charge path from the power supply voltage to the floating capacitor is enabled (diode D1 is forward biased so that power supply capacitor VCC charges the positive plate of bootstrap capacitor CB) (see [0022] of Liu “As part of the first charging path, a diode D1 is forward biased by the power supply voltage VCC so as to charge a driver power supply voltage across a bootstrap capacitor CB”), and a second charge path from the second pin to the floating capacitor is enabled (transistor S3 is cycled on so that a charging path is activated from the positive plate of active clamp capacitor Ca to the positive plate of bootstrap capacitor CB) (see [0025] of Liu “Thus, when transistor S3 is cycled on, a charging path is activated from active clamp capacitor Ca through resistor R7, transistor S3, and resistor R7 to charge bootstrap capacitor CB”, Examiner’s Note: the second recitation of “resistor R7” appears to be a typographical error for “resistor R6”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the IC chip of EVL8017 wherein a first charge path from the power supply voltage to the floating capacitor is enabled, and a second charge path from the second pin to the floating capacitor is enabled, as taught by Liu, because it can recover the leakage inductance energy accumulated on the buffer capacitor and use that energy to sustain the voltage across the floating capacitor (see [0005] of Liu “The resulting voltage rise across active clamp capacitor Ca may damage it and cause safety issues”).
EVL8017 does not disclose when the main power switch is turned on, a first charge path from the power supply voltage to the floating capacitor is enabled, and the first charge path is disabled.
However, Li teaches (see Fig. 3) when the main power switch is turned on, a first charge path from the power supply voltage to the floating capacitor is enabled (when the third power switch 13 is turned on, the first switching node SW1 is pulled to the reference ground and power supply VCC charges the first bootstrap capacitor 23 through the first charging switch 21) (see [0034] of Li “The first switching node SW1 is connected to the reference ground, and the power supply VCC may be configured to charge the first bootstrap capacitor 23 via the first charging switch 21 to refresh the first bootstrap voltage signal VBST1”), and the first charge path is disabled (the first charging switch 21 opens whenever the third power switch 13 opens) (see [0031] of Li “on and off switching of the first charging switch 21 is simultaneous with on and off switching of the third power switch 13”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the IC chip of EVL8017 wherein when the main power switch is turned on, a first charge path from the power supply voltage to the floating capacitor is enabled, and the first charge path is disabled, as taught by Li, because it can confine charging of the floating capacitor to the interval during which the node shared by the floating capacitor and the main power switch is held at the reference ground.
EVL8017 does not disclose when a voltage at the second pin is higher than a reference voltage, the main power switch is turned off.
However, Koo teaches (see Fig. 1 and Fig. 3) when a voltage at the second pin is higher than a reference voltage (comparator 340 compares the voltage sensed at HV terminal 181, which is connected to the second terminal of clamp capacitor 153, with threshold voltage VTH) (see [0031] of Koo “In this manner, ACF controller 180 uses OVP circuit 188 to detect when the value of VCLAMP is too high”), the main power switch is turned off (low side switch 151 is deactivated) (see [0048] of Koo “In one example of the OVP operation, ACF controller 180 deactivates both switches 151 and 152 and otherwise shuts down power supply system 100 to protect the system and the load”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the IC chip of EVL8017 wherein when a voltage at the second pin is higher than a reference voltage, the main power switch is turned off, the first charge path is disabled, and a second charge path from the second pin to the floating capacitor is enabled, as taught by Koo, because it can hold the voltage at the second pin below the level at which the IC chip would be damaged (see [0003] of Koo “This buildup in voltage across the clamp capacitor will eventually cause the ACF converter to be damaged or otherwise to fail”), while recovering the charge accumulated at that pin into the floating capacitor instead of dissipating it, the transistor that establishes the second charge path in Liu already being switched by the output of a comparator that compares a sensed voltage with a reference voltage (see [0026] of Liu “To control whether transistor S4 is on or off, a comparator C1 compares a reference voltage Vref to a divided version of the driver power supply voltage stored across bootstrap capacitor CB”), and Koo already conducting the charge accumulated at the second pin away through a switch closed by the output of such a comparator (see [0043] of Koo “In response to the activation of the OVP signal, switch 310 closes and starts to discharge clamp capacitor 153”) (Examiner’s Note: turning off the main power switch necessarily disables the first charge path, which claim 7 recites as being enabled when the main power switch is turned on).
Regarding claim 8, EVL8017 does not disclose wherein the IC chip further comprises: a connecting switch, coupled between the second pin and the third pin.
However, Liu teaches (see Fig. 4) a connecting switch, coupled between the second pin and the third pin (NMOS transistor S3 is coupled between the positive plate of active clamp capacitor Ca and the positive plate of bootstrap capacitor CB) (see [0025] of Liu “A source of the transistor S3 couples through a resistor R6 to the positive plate of bootstrap capacitor CB. A drain of transistor S3 couples through a resistor R7 to the positive plate of active clamp capacitor Ca”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the IC chip of EVL8017 to comprise a connecting switch, coupled between the second pin and the third pin, as taught by Liu, because it can establish the second charge path through an active device that conducts only when required, thereby avoiding the continuous resistive loss of a permanently conducting path (see [0025] of Liu “An active circuit embodiment for charge path circuit 205 in which the charge path circuit 205 comprises an NMOS transistor S3 such as shown in FIG. 4 for a flyback converter 400 avoids such resistive losses”).
EVL8017 does not disclose wherein the connecting switch is configured to be turned on when the voltage at the second pin is higher than the reference voltage.
However, Koo teaches (see Fig. 3) wherein the connecting switch is configured to be turned on when the voltage at the second pin is higher than the reference voltage (switch 310 is closed by the output of comparator 340, which compares the voltage sensed at HV terminal 181 with threshold voltage VTH) (see [0043] of Koo “In response to the activation of the OVP signal, switch 310 closes and starts to discharge clamp capacitor 153”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the IC chip of EVL8017 wherein the connecting switch is configured to be turned on when the voltage at the second pin is higher than the reference voltage, as taught by Koo, because it can transfer the charge accumulated at the second pin only when that pin reaches the voltage at which the IC chip would otherwise be placed at risk.
Regarding claim 9, EVL8017 does not disclose wherein the IC chip further comprises: a current source, series coupled with the connecting switch between the second pin and the third pin.
However, Li teaches (see Fig. 5) a current source (first current regulating circuit 49, which generates the first charging current signal i11), series coupled with the connecting switch (switch 471) between the second pin and the third pin (switch 471 and the first current regulating circuit 49 are coupled in series between the input voltage signal VIN and the first bootstrap node BST1) (see [0050] of Li “The switch 471 may have a first terminal configured to receive the input voltage signal VIN, a second terminal coupled to the first current regulating circuit 49 via the diode 481, and a control terminal configured to receive the logic signal CP11”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the IC chip of EVL8017 to comprise a current source, series coupled with the connecting switch between the second pin and the third pin, as taught by Li, because it can hold the charging current delivered through the connecting switch to a controlled magnitude and thereby prevent an excessive inrush current from being drawn when the connecting switch is turned on.
Regarding claim 10, EVL8017 does not disclose wherein the IC chip further comprises: a current source, configured to provide a current signal; and a current mirror circuit, configured to deliver the current signal to the floating capacitor when the connecting switch is turned on.
However, Li teaches (see Fig. 5 and Fig. 7) a current source (the source of bias current signal IB within the first subtracting circuit 61), configured to provide a current signal (bias current signal IB) (see [0066] of Li “The first subtracting circuit 61 may be configured to receive the first feedback signal iBST1_F, and conduct a subtraction operation to the first feedback signal iBST1_F and a bias current signal IB to generate a first difference signal IB-iBST1_F”); and a current mirror circuit (current mirror circuit 62), configured to deliver the current signal to the floating capacitor when the connecting switch is turned on (current mirror circuit 62 delivers the first charging current signal i11 to the first bootstrap node BST1, and the first current regulating circuit 49 generates no such current while switch 471 is off) (see [0053] of Li “When the first feedback signal iBST1_F or the second feedback signal iBST2_F is larger than the first refresh threshold iTH1, both the switch 471 and the switch 472 are turned off. The first current regulating circuit 49 is unable to generate the first charging current signal i11 and the second charging current signal i12”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the IC chip of EVL8017 to comprise a current source, configured to provide a current signal; and a current mirror circuit, configured to deliver the current signal to the floating capacitor when the connecting switch is turned on, as taught by Li, because it can replicate a single reference current onto the charging path without placing the reference current source itself at the elevated potential of the second pin.
Regarding claim 11, EVL8017 does not disclose wherein the current mirror circuit having an input terminal coupled to the current source, and an output terminal configured to provide a mirrored current proportional to the current signal when the connect switch is turned on, to charge the floating capacitor.
However, Li teaches (see Fig. 7) the current mirror circuit having an input terminal coupled to the current source (a first current terminal of current mirror circuit 62 receives the first difference signal IB-iBST1_F generated from bias current signal IB), and an output terminal configured to provide a mirrored current proportional to the current signal when the connect switch is turned on, to charge the floating capacitor (a second current terminal of current mirror circuit 62 is coupled to the first bootstrap node BST1 through diode 63 and provides the first charging current signal i11 mirrored from the first difference signal) (see [0066] of Li “a first current terminal configured to receive the first difference signal IB-iBST1_F, and a second current terminal coupled to the first bootstrap node BST1 through the diode 63. The current mirror circuit 62 may be configured to mirror the first difference signal IB-iBST1_F to provide the first charging current signal i11 at its second current terminal”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the IC chip of EVL8017 wherein the current mirror circuit having an input terminal coupled to the current source, and an output terminal configured to provide a mirrored current proportional to the current signal when the connect switch is turned on, to charge the floating capacitor, as taught by Li, because it can set the magnitude of the charging current by a single reference current while isolating that reference current from the charging path.
Regarding claim 12, EVL8017 does not disclose wherein the IC chip further comprises: a voltage converter, coupled to the fourth pin, to provide the power supply voltage.
However, Li teaches (see Fig. 13) a voltage converter (power supply generator 600), coupled to the fourth pin, to provide the power supply voltage (transistor 121 receives the input voltage signal VIN and provides the power supply VCC at its second terminal) (see [0076] of Li “the power supply generator 600 is illustrated as a low dropout linear regulator (LDO) comprising a transistor 121 and an error amplifier 122”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the IC chip of EVL8017 to comprise a voltage converter, coupled to the fourth pin, to provide the power supply voltage, as taught by Li, because it can derive a regulated low-voltage supply for the IC chip from the input voltage already present at the converter, so that no separate supply source is required.
Regarding claim 13, EVL8017 discloses (see Fig. 3) an IC chip (U1, MP8017, in a QFN-19 package) used in an active clamp flyback converter (see p. 1 of EVL8017 “The MP8017 flyback converter is specifically designed for active-clamp, primary-side regulation (PSR) in a flyback topology”), comprising: a first pin (SW, pin 14); a second pin (SNBR, pin 17); a third pin (BST, pin 13); and a fourth pin (VCC, pin 10), configured to provide a power supply voltage to the IC chip (VCC pin 10 is bypassed to PGND by C8, 2.2 µF).
EVL8017 does not disclose a first pin, coupled to a main power switch and an auxiliary switch, and a second pin, coupled to the first pin via the auxiliary switch.
However, Liu teaches (see Fig. 2 and Fig. 4) a first pin, coupled to a main power switch and an auxiliary switch (the node at the drain of power switch transistor S1 and the source of active clamp switch transistor S2) (see [0022] of Liu “A negative plate for bootstrap capacitor CB connects to the source of active clamp switch transistor S2 and to the drain of power switch transistor S1”), and a second pin, coupled to the first pin via the auxiliary switch (the positive plate of active clamp capacitor Ca is coupled to that node through active clamp transistor S2) (see [0022] of Liu “Active clamp transistor S2 couples between the drain of power switch transistor S1 and a positive plate for active clamp capacitor Ca”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the IC chip of EVL8017 to include a first pin, coupled to a main power switch and an auxiliary switch, and a second pin, coupled to the first pin via the auxiliary switch, as taught by Liu, because it can store and reclaim the leakage energy of the transformer in the buffer capacitor instead of dissipating it (see [0003] of Liu “In active clamp operation, the leakage energy in the transformer is stored and reclaimed in an active clamp capacitor that is coupled to a terminal for the power switch transistor through an active clamp switch transistor”).
EVL8017 does not disclose a first charge path from the power supply voltage to the third pin is enabled, and a second charge path from the second pin to the third pin is enabled.
However, Liu teaches (see Fig. 2 and Fig. 4) a first charge path from the power supply voltage to the third pin is enabled (diode D1 is forward biased so that power supply capacitor VCC charges the positive plate of bootstrap capacitor CB) (see [0022] of Liu “As part of the first charging path, a diode D1 is forward biased by the power supply voltage VCC so as to charge a driver power supply voltage across a bootstrap capacitor CB”), and a second charge path from the second pin to the third pin is enabled (transistor S3 is cycled on so that a charging path is activated from the positive plate of active clamp capacitor Ca to the positive plate of bootstrap capacitor CB) (see [0025] of Liu “Thus, when transistor S3 is cycled on, a charging path is activated from active clamp capacitor Ca through resistor R7, transistor S3, and resistor R7 to charge bootstrap capacitor CB”, Examiner’s Note: the second recitation of “resistor R7” appears to be a typographical error for “resistor R6”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the IC chip of EVL8017 wherein a first charge path from the power supply voltage to the third pin is enabled, and a second charge path from the second pin to the third pin is enabled, as taught by Liu, because it can recover the leakage inductance energy accumulated at the second pin and use that energy to sustain the voltage at the third pin (see [0005] of Liu “The resulting voltage rise across active clamp capacitor Ca may damage it and cause safety issues”).
EVL8017 does not disclose when the main power switch is turned on, a first charge path from the power supply voltage to the third pin is enabled, and the first charge path is disabled.
However, Li teaches (see Fig. 3) when the main power switch is turned on, a first charge path from the power supply voltage to the third pin is enabled (when the third power switch 13 is turned on, the first switching node SW1 is pulled to the reference ground and power supply VCC charges the first bootstrap voltage supply node BST1 through the first charging switch 21) (see [0034] of Li “The first switching node SW1 is connected to the reference ground, and the power supply VCC may be configured to charge the first bootstrap capacitor 23 via the first charging switch 21 to refresh the first bootstrap voltage signal VBST1”), and the first charge path is disabled (the first charging switch 21 opens whenever the third power switch 13 opens) (see [0031] of Li “on and off switching of the first charging switch 21 is simultaneous with on and off switching of the third power switch 13”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the IC chip of EVL8017 wherein when the main power switch is turned on, a first charge path from the power supply voltage to the third pin is enabled, and the first charge path is disabled, as taught by Li, because it can confine charging to the interval during which the node shared with the main power switch is held at the reference ground.
EVL8017 does not disclose when a voltage at the second pin is higher than a reference voltage, the main power switch is turned off.
However, Koo teaches (see Fig. 1 and Fig. 3) when a voltage at the second pin is higher than a reference voltage (comparator 340 compares the voltage sensed at HV terminal 181, which is connected to the second terminal of clamp capacitor 153, with threshold voltage VTH) (see [0031] of Koo “In this manner, ACF controller 180 uses OVP circuit 188 to detect when the value of VCLAMP is too high”), the main power switch is turned off (low side switch 151 is deactivated) (see [0048] of Koo “In one example of the OVP operation, ACF controller 180 deactivates both switches 151 and 152 and otherwise shuts down power supply system 100 to protect the system and the load”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the IC chip of EVL8017 wherein when a voltage at the second pin is higher than a reference voltage, the main power switch is turned off, the first charge path is disabled, and a second charge path from the second pin to the third pin is enabled, as taught by Koo, because it can hold the voltage at the second pin below the level at which the IC chip would be damaged (see [0003] of Koo “This buildup in voltage across the clamp capacitor will eventually cause the ACF converter to be damaged or otherwise to fail”), while recovering the charge accumulated at that pin into the third pin instead of dissipating it, the transistor that establishes the second charge path in Liu already being switched by the output of a comparator that compares a sensed voltage with a reference voltage (see [0026] of Liu “To control whether transistor S4 is on or off, a comparator C1 compares a reference voltage Vref to a divided version of the driver power supply voltage stored across bootstrap capacitor CB”), and Koo already conducting the charge accumulated at the second pin away through a switch closed by the output of such a comparator (see [0043] of Koo “In response to the activation of the OVP signal, switch 310 closes and starts to discharge clamp capacitor 153”) (Examiner’s Note: turning off the main power switch necessarily disables the first charge path, which claim 13 recites as being enabled when the main power switch is turned on).
Regarding claim 14, EVL8017 does not disclose wherein the IC chip further comprises: a connecting switch, coupled between the second pin and the third pin.
However, Liu teaches (see Fig. 4) a connecting switch, coupled between the second pin and the third pin (NMOS transistor S3 is coupled between the positive plate of active clamp capacitor Ca and the positive plate of bootstrap capacitor CB) (see [0025] of Liu “A source of the transistor S3 couples through a resistor R6 to the positive plate of bootstrap capacitor CB. A drain of transistor S3 couples through a resistor R7 to the positive plate of active clamp capacitor Ca”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the IC chip of EVL8017 to comprise a connecting switch, coupled between the second pin and the third pin, as taught by Liu, because it can establish the second charge path through an active device that conducts only when required, thereby avoiding the continuous resistive loss of a permanently conducting path (see [0025] of Liu “An active circuit embodiment for charge path circuit 205 in which the charge path circuit 205 comprises an NMOS transistor S3 such as shown in FIG. 4 for a flyback converter 400 avoids such resistive losses”).
EVL8017 does not disclose wherein the connecting switch is configured to be turned on when the voltage at the second pin is higher than the reference voltage.
However, Koo teaches (see Fig. 3) wherein the connecting switch is configured to be turned on when the voltage at the second pin is higher than the reference voltage (switch 310 is closed by the output of comparator 340, which compares the voltage sensed at HV terminal 181 with threshold voltage VTH) (see [0043] of Koo “In response to the activation of the OVP signal, switch 310 closes and starts to discharge clamp capacitor 153”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the IC chip of EVL8017 wherein the connecting switch is configured to be turned on when the voltage at the second pin is higher than the reference voltage, as taught by Koo, because it can transfer the charge accumulated at the second pin only when that pin reaches the voltage at which the IC chip would otherwise be placed at risk.
Regarding claim 15, EVL8017 does not disclose wherein the IC chip further comprises: a current source, series coupled with the connecting switch between the second pin and the third pin.
However, Li teaches (see Fig. 5) a current source (first current regulating circuit 49, which generates the first charging current signal i11), series coupled with the connecting switch (switch 471) between the second pin and the third pin (switch 471 and the first current regulating circuit 49 are coupled in series between the input voltage signal VIN and the first bootstrap node BST1) (see [0050] of Li “The switch 471 may have a first terminal configured to receive the input voltage signal VIN, a second terminal coupled to the first current regulating circuit 49 via the diode 481, and a control terminal configured to receive the logic signal CP11”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the IC chip of EVL8017 to comprise a current source, series coupled with the connecting switch between the second pin and the third pin, as taught by Li, because it can hold the charging current delivered through the connecting switch to a controlled magnitude and thereby prevent an excessive inrush current from being drawn when the connecting switch is turned on.
Regarding claim 16, EVL8017 does not disclose wherein the IC chip further comprises: a current source, configured to provide a current signal; and a current mirror circuit, configured to deliver the current signal to the third pin when the connecting switch is turned on.
However, Li teaches (see Fig. 5 and Fig. 7) a current source (the source of bias current signal IB within the first subtracting circuit 61), configured to provide a current signal (bias current signal IB) (see [0066] of Li “The first subtracting circuit 61 may be configured to receive the first feedback signal iBST1_F, and conduct a subtraction operation to the first feedback signal iBST1_F and a bias current signal IB to generate a first difference signal IB-iBST1_F”); and a current mirror circuit (current mirror circuit 62), configured to deliver the current signal to the third pin when the connecting switch is turned on (current mirror circuit 62 delivers the first charging current signal i11 to the first bootstrap node BST1, and the first current regulating circuit 49 generates no such current while switch 471 is off) (see [0053] of Li “When the first feedback signal iBST1_F or the second feedback signal iBST2_F is larger than the first refresh threshold iTH1, both the switch 471 and the switch 472 are turned off. The first current regulating circuit 49 is unable to generate the first charging current signal i11 and the second charging current signal i12”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the IC chip of EVL8017 to comprise a current source, configured to provide a current signal; and a current mirror circuit, configured to deliver the current signal to the third pin when the connecting switch is turned on, as taught by Li, because it can replicate a single reference current onto the charging path without placing the reference current source itself at the elevated potential of the second pin.
Regarding claim 17, EVL8017 does not disclose wherein the current mirror circuit having an input terminal coupled to the current source, and an output terminal configured to provide a mirrored current proportional to the current signal when the connect switch is turned on.
However, Li teaches (see Fig. 7) the current mirror circuit having an input terminal coupled to the current source (a first current terminal of current mirror circuit 62 receives the first difference signal IB-iBST1_F generated from bias current signal IB), and an output terminal configured to provide a mirrored current proportional to the current signal when the connect switch is turned on (a second current terminal of current mirror circuit 62 is coupled to the first bootstrap node BST1 through diode 63 and provides the first charging current signal i11 mirrored from the first difference signal) (see [0066] of Li “a first current terminal configured to receive the first difference signal IB-iBST1_F, and a second current terminal coupled to the first bootstrap node BST1 through the diode 63. The current mirror circuit 62 may be configured to mirror the first difference signal IB-iBST1_F to provide the first charging current signal i11 at its second current terminal”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the IC chip of EVL8017 wherein the current mirror circuit having an input terminal coupled to the current source, and an output terminal configured to provide a mirrored current proportional to the current signal when the connect switch is turned on, as taught by Li, because it can set the magnitude of the charging current by a single reference current while isolating that reference current from the charging path.
Regarding claim 18, EVL8017 discloses (see Fig. 3) wherein a floating capacitor is coupled between the first pin and the third pin (C6, 0.22 µF, is coupled between BST pin 13 and SW pin 14).
Regarding claim 19, EVL8017 discloses (see Fig. 3) wherein the second pin is configured to receive an input voltage via a buffer capacitor (C4, 4.7 µF, is coupled between the VBUS rail and SNBR pin 17).
Regarding claim 20, EVL8017 does not disclose wherein the IC chip further comprises: a voltage converter, coupled to the fourth pin, to provide the power supply voltage.
However, Li teaches (see Fig. 13) a voltage converter (power supply generator 600), coupled to the fourth pin, to provide the power supply voltage (transistor 121 receives the input voltage signal VIN and provides the power supply VCC at its second terminal) (see [0076] of Li “the power supply generator 600 is illustrated as a low dropout linear regulator (LDO) comprising a transistor 121 and an error amplifier 122”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the IC chip of EVL8017 to comprise a voltage converter, coupled to the fourth pin, to provide the power supply voltage, as taught by Li, because it can derive a regulated low-voltage supply for the IC chip from the input voltage already present at the converter, so that no separate supply source is required.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Monolithic Power Systems, “Introducing the MP8017: An Ultra-Small IEEE 802.3af PoE PD Solution,” Article #W043 Rev. 1.0, May 19, 2022 discloses a fully integrated chip containing a PD interface, a DC/DC converter and a hot-swap power MOSFET, and adopting active-clamp control in which two integrated MOSFETs replace the RCD snubber of a conventional flyback converter.
Monolithic Power Systems, “MP8017 – IEEE 802.3af-Compliant PoE PD Solution with Primary- or Secondary-Side Regulation Active-Clamp Flyback Converter,” Rev. 1.1, October 28, 2024 (revision history identifies Rev. 1.0, February 21, 2023 as the initial release) discloses an integrated circuit for an active-clamp flyback converter having an SW pin at the drain of the main switching MOSFET, an SNBR pin connected to the drain of the internal SYNC FET, a BST pin for the high-side MOSFET driver, and a VCC pin powered through an internal LDO, wherein the BST capacitor is charged by VCC when the LS-FET turns on, and all switching is stopped when the SNBR voltage exceeds 105V.
US 2021/0119627 A1 discloses a gate driver bootstrap circuit that turns on a current mirror to charge a bootstrap capacitor.
US 2016/0065072 A1 discloses a power converter having a first charging circuit and a second charging circuit for a bootstrap capacitor selected by a comparing circuit.
US 2008/0218141 A1 discloses a circuit for charging a bootstrap capacitor in which a comparator controls a transistor coupled between a supply voltage and the bootstrap capacitor.
US 2020/0328669 A1 discloses an active clamp flyback circuit in which the main switch is controlled to be off and the auxiliary switch is operated to discharge the clamp capacitor in an over-voltage protection mode.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JYE-JUNE LEE whose telephone number is (571)270-7726. The examiner can normally be reached on M-F 9 AM - 5 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached on 5712721838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MONICA LEWIS/ Supervisory Patent Examiner, Art Unit 2838
/JYE-JUNE LEE/Examiner, Art Unit 2838
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