Accelerating Inductive Learning In Description Logic

DETAILED ACTION Claims 1-8 and 10-16 have been examined. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 U.S.C. § 101 35 U.S.C. § 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. The invention, as taught in Claims 1-8 and 10-16, is directed to “mental steps” and “mathematical steps” without significantly more. The claims recite: • instructions (i.e., mental steps) • a subset of said instructions expressed as logic-based rules or textual-like descriptions, in a form capable of interpretation by both humans and machines (i.e., mental steps) • selecting a knowledge base (i.e., mental steps) • selecting a set of concept axioms (i.e., mental steps) • applying the knowledge base and the set of concept axioms to perform the hypothesis evaluation task (i.e., mental steps) • performing a hypothesis search (i.e., mental steps) • scanning each assertion to find at least one assertion that matches specific conditions (i.e., mental steps) • selecting one or more hypotheses as DL hypotheses (i.e., mental steps) • evaluating at least one of the DL hypothesis (i.e., mental steps) • for each DL hypothesis, using the computed examples coverage to compute an evaluation score for the given hypothesis (i.e., mathematical steps) • determine the type of DL operation to be computed (i.e., mental steps) • “passing a retrieved memory address offset to a Binary Assertions Unit (BAU), the BAU further comprising a relationship operations sub-unit and a literal operations sub-unit” (i.e., mental steps) Applicant’s Specification, paragraph [0038] recites: [0038] As a logic-based representation, DL describes a knowledge base using instances (individuals), concepts and roles; where a DL knowledge base consists of an A-Box (assertions box) and a T-Box (terminological box). An A-Box contains the assertions (or ground facts), which in DL, can be unary and binary assertions. A unary (concept) assertion takes the form a:C where a is an individual and C is concept. A binary (role) assertion takes the form (a,b):r, by which r is the role, and both a and b are individuals; where a is the subject and b is the object of the role assertion. Examples for unary and binary assertions, can be seen in Table 1: Further, Applicant’s Specification, paragraph [0005] recites: [0005] Hardware-based acceleration of computer operations is performed using Description Logic (DL) language in inductive logic programming (ILP) instructions for performing a hypothesis evaluation task. At least a subset of the instructions are expressed as logic-based rules or textual-like descriptions, in a form capable of interpretation by both humans and machines. A knowledge base interpretable by Inductive Logic Programming (ILP) is selected. A set of concept axioms enforces a set of logic-based constraints on the knowledge base, in which the logic-based constraints establish reasoning tasks on the knowledge base using the ILP. A hardware configuration is used to implement the established reasoning tasks through a hardware implementation, and the knowledge base and the set of concept axioms are used to perform the hypothesis evaluation task, which is executed through the hardware implementation. • the relationship operations sub-unit and literal operations sub-unit capable of computing: - existential role restrictions, - universal role restrictions, - cardinality role restrictions - numeric role restriction. - string (EQUAL and NOT EQUAL) role restrictions: (i.e., mental steps) Applicant’s Specification, paragraph [0005] recites: [0005] Hardware-based acceleration of computer operations is performed using Description Logic (DL) language in inductive logic programming (ILP) instructions for performing a hypothesis evaluation task. At least a subset of the instructions are expressed as logic-based rules or textual-like descriptions, in a form capable of interpretation by both humans and machines. A knowledge base interpretable by Inductive Logic Programming (ILP) is selected. A set of concept axioms enforces a set of logic-based constraints on the knowledge base, in which the logic-based constraints establish reasoning tasks on the knowledge base using the ILP. A hardware configuration is used to implement the established reasoning tasks through a hardware implementation, and the knowledge base and the set of concept axioms are used to perform the hypothesis evaluation task, which is executed through the hardware implementation. • “a Unitary Assertions Unit (UAU) for computing conjunction and disjunction DL operations by receiving, processing and reporting the results of conjunction and disjunction operations” (i.e., mental steps) Applicant’s Specification, paragraph [0005] recites: [0005] Hardware-based acceleration of computer operations is performed using Description Logic (DL) language in inductive logic programming (ILP) instructions for performing a hypothesis evaluation task. At least a subset of the instructions are expressed as logic-based rules or textual-like descriptions, in a form capable of interpretation by both humans and machines. A knowledge base interpretable by Inductive Logic Programming (ILP) is selected. A set of concept axioms enforces a set of logic-based constraints on the knowledge base, in which the logic-based constraints establish reasoning tasks on the knowledge base using the ILP. A hardware configuration is used to implement the established reasoning tasks through a hardware implementation, and the knowledge base and the set of concept axioms are used to perform the hypothesis evaluation task, which is executed through the hardware implementation. • a result memory address offset lookup table and a concept memory address offset lookup table” (i.e., mental steps) Claim 1 Step 1 inquiry: Does this claim fall within a statutory category? The preamble of the claim recites “1. A method for provide hardware-based acceleration of computer operations, the method comprising…” Therefore, it is a “method” (or “process”), which is a statutory category of invention. Therefore, the answer to the inquiry is: “YES”. Step 2A (Prong One) inquiry: Are there limitations in Claim 1 that recite abstract ideas? YES. The following limitations in Claim 1 recite abstract ideas that fall within at least one of the groupings of abstract ideas enumerated in the 2019 PEG. Specifically, they are “mental steps” and “mathematical steps”: • instructions (i.e., mental steps) • a subset of said instructions expressed as logic-based rules or textual-like descriptions, in a form capable of interpretation by both humans and machines (i.e., mental steps) • selecting a knowledge base (i.e., mental steps) • selecting a set of concept axioms (i.e., mental steps) • applying the knowledge base and the set of concept axioms to perform the hypothesis evaluation task (i.e., mental steps) • performing a hypothesis search (i.e., mental steps) • scanning each assertion to find at least one assertion that matches specific conditions (i.e., mental steps) • selecting one or more hypotheses as DL hypotheses (i.e., mental steps) • evaluating at least one of the DL hypothesis (i.e., mental steps) • for each DL hypothesis, using the computed examples coverage to compute an evaluation score for the given hypothesis (i.e., mathematical steps) • determine the type of DL operation to be computed (i.e., mental steps) • “passing a retrieved memory address offset to a Binary Assertions Unit (BAU), the BAU further comprising a relationship operations sub-unit and a literal operations sub-unit” (i.e., mental steps) Applicant’s Specification, paragraph [0038] recites: [0038] As a logic-based representation, DL describes a knowledge base using instances (individuals), concepts and roles; where a DL knowledge base consists of an A-Box (assertions box) and a T-Box (terminological box). An A-Box contains the assertions (or ground facts), which in DL, can be unary and binary assertions. A unary (concept) assertion takes the form a:C where a is an individual and C is concept. A binary (role) assertion takes the form (a,b):r, by which r is the role, and both a and b are individuals; where a is the subject and b is the object of the role assertion. Examples for unary and binary assertions, can be seen in Table 1: Further, Applicant’s Specification, paragraph [0005] recites: [0005] Hardware-based acceleration of computer operations is performed using Description Logic (DL) language in inductive logic programming (ILP) instructions for performing a hypothesis evaluation task. At least a subset of the instructions are expressed as logic-based rules or textual-like descriptions, in a form capable of interpretation by both humans and machines. A knowledge base interpretable by Inductive Logic Programming (ILP) is selected. A set of concept axioms enforces a set of logic-based constraints on the knowledge base, in which the logic-based constraints establish reasoning tasks on the knowledge base using the ILP. A hardware configuration is used to implement the established reasoning tasks through a hardware implementation, and the knowledge base and the set of concept axioms are used to perform the hypothesis evaluation task, which is executed through the hardware implementation. • the relationship operations sub-unit and literal operations sub-unit capable of computing: - existential role restrictions, - universal role restrictions, - cardinality role restrictions - numeric role restriction. - string (EQUAL and NOT EQUAL) role restrictions: (i.e., mental steps) Applicant’s Specification, paragraph [0005] recites: [0005] Hardware-based acceleration of computer operations is performed using Description Logic (DL) language in inductive logic programming (ILP) instructions for performing a hypothesis evaluation task. At least a subset of the instructions are expressed as logic-based rules or textual-like descriptions, in a form capable of interpretation by both humans and machines. A knowledge base interpretable by Inductive Logic Programming (ILP) is selected. A set of concept axioms enforces a set of logic-based constraints on the knowledge base, in which the logic-based constraints establish reasoning tasks on the knowledge base using the ILP. A hardware configuration is used to implement the established reasoning tasks through a hardware implementation, and the knowledge base and the set of concept axioms are used to perform the hypothesis evaluation task, which is executed through the hardware implementation. • “a Unitary Assertions Unit (UAU) for computing conjunction and disjunction DL operations by receiving, processing and reporting the results of conjunction and disjunction operations” (i.e., mental steps) Applicant’s Specification, paragraph [0005] recites: [0005] Hardware-based acceleration of computer operations is performed using Description Logic (DL) language in inductive logic programming (ILP) instructions for performing a hypothesis evaluation task. At least a subset of the instructions are expressed as logic-based rules or textual-like descriptions, in a form capable of interpretation by both humans and machines. A knowledge base interpretable by Inductive Logic Programming (ILP) is selected. A set of concept axioms enforces a set of logic-based constraints on the knowledge base, in which the logic-based constraints establish reasoning tasks on the knowledge base using the ILP. A hardware configuration is used to implement the established reasoning tasks through a hardware implementation, and the knowledge base and the set of concept axioms are used to perform the hypothesis evaluation task, which is executed through the hardware implementation. • a result memory address offset lookup table and a concept memory address offset lookup table” (i.e., mental steps) Step 2A (Prong Two) inquiry: Are there additional elements or a combination of elements in the claim that apply, rely on, or use the judicial exception in a manner that imposes a meaningful limit on the judicial exception, such that it is more than a drafting effort designed to monopolize the exception? Applicant’s claims contain the following “additional elements”: (1) A “hardware configuration”/ “circuit” (2) An “execution” of the “hypothesis evaluation task through the hardware implementation” (3) A “using” of “a hardware accelerator” (4) A “main controller” (5) A “receiving” of “computation commands through communication with a host system and capable of decoding the received commands” (1) A “hardware configuration”/ “circuit” (e.g., a “processor” , or set of processors) is a broad term which is described at a high level and includes multiple general purpose computers. Applicant's Specification recites: [0005] Hardware-based acceleration of computer operations is performed using Description Logic (DL) language in inductive logic programming (ILP) instructions for performing a hypothesis evaluation task. At least a subset of the instructions are expressed as logic-based rules or textual-like descriptions, in a form capable of interpretation by both humans and machines. A knowledge base interpretable by Inductive Logic Programming (ILP) is selected. A set of concept axioms enforces a set of logic-based constraints on the knowledge base, in which the logic-based constraints establish reasoning tasks on the knowledge base using the ILP. A hardware configuration is used to implement the established reasoning tasks through a hardware implementation, and the knowledge base and the set of concept axioms are used to perform the hypothesis evaluation task, which is executed through the hardware implementation. Further, Applicant's Specification recites: [0031] ILP as one of the ML techniques struggle in the scalability aspect; especially since ILP algorithms (in many cases) are inherently sequential algorithms, which introduces major challenges for speeding up their computations. This ILP scalability challenge, has resulted in many approaches being developed to address these inherent deficiencies; however, many of these approaches (especially the ones based on parallel computing), rely on using software based solutions (e.g., CPUs and GPUs), and overlook the potential performance gains of hardware based solutions (e.g., FPGAs and ASICs). One key advantage of dedicated hardware designs (i.e., a hardware specifically designed for a particular purpose) is that they have much more parallel computing capabilities and consume much less power than software solutions. In other words, the number of parallel processing logic in CPUs and GPUs is fixed; while an FPGA (a common form of a hardware solution), has much more parallel processing capability that can be used (or configured) to improve performance. Even though FPGAs (as a hardware solution) consume much less power than software solutions (for the same computations), even more power efficiency can be obtained through an ASICs hardware solution. However, ASICs are more expensive to design and manufacture (as opposed to FPGAs). [0032] The disclosed concept implements description logic and inductive logic programming. In a non-limiting example, a hardware-based approach is implemented. Note that Applicant's claimed “hardware configuration” has support in the Specification, paragraph [0031], where it recites “hardware based solutions (e.g., FPGAs and ASICs)”. Note that the term does not specify how the solutions are “based” on hardware. It does not exclude programmable systems, since FPGAs (Field Programmable Gate Arrays) are programmable and reprogrammable (therefore, this makes them dependent on software). Further, the use of multiple FPGAs may include the use of software (e.g., for managing inter-FPGA communication.) The scope of the term includes programmable systems, including additional generic CPUs, which are “hardware based”. Further, Applicant's Specification recites: [0061] Fig. 4 is a schematic block diagram showing a comparison between software-based and hardware based approaches on accelerating ML computations, showing characteristics of ML acceleration. First, scalar CPU multi-threading ("CPU MT.(S)") is relatively the easiest acceleration method for accelerating computations; however, this method also provides the least performance speed increases. In many implementation cases(of this acceleration method), the vector/SIMD instruction set, available in modern CPUs, are typically ignored - this results in less efficient use of CPU's computing capabilities. On the other hand, in the second acceleration method which is vectorized CPU multithreading ("CPU MT.(V)"), will provide much higher performance gains than pure (scalar) multithreading; however, with two key disadvantages. First, the needed development skill is higher (than for scalar multithreading), because proper utilization of a CPU's vector instruction set, requires deep understanding of the CPU's architecture; moreover, some CPUs may have different vector instruction set, than other CPUs, e.g., SSE (Streaming SIMD Extensions) and AVX (Advanced Vector Extensions) for Intel and AMD CPUs, and Neon for ARM CPUs. The second disadvantage for vectorized CPU15 multithreading (especially with CPUs with large core counts) is that despite the much larger performance gains (than scalar multithreading); the CPU's cores together with each core's vector instructions will saturate the memory bandwidth, which will impose an upper limit on how much performance speed increases can be achieved. M.P.E.P. § 2016.05(f) recites: 2106.05(f) Mere Instructions To Apply An Exception [R-10.2019] Another consideration when determining whether a claim integrates a judicial exception into a practical application in Step 2A Prong Two or recites significantly more than a judicial exception in Step 2B is whether the additional elements amount to more than a recitation of the words “apply it” (or an equivalent) or are more than mere instructions to implement an abstract idea or other exception on a computer. As explained by the Supreme Court, in order to make a claim directed to a judicial exception patent-eligible, the additional element or combination of elements must do “‘more than simply stat[e] the [judicial exception] while adding the words ‘apply it’”. Alice Corp. v. CLS Bank, 573 U.S. 208, 221, 110 USPQ2d 1976, 1982-83 (2014) (quoting Mayo Collaborative Servs. V. Prometheus Labs., Inc., 566 U.S. 66, 72, 101 USPQ2d 1961, 1965). Thus, for example, claims that amount to nothing more than an instruction to apply the abstract idea using a generic computer do not render an abstract idea eligible. Alice Corp., 573 U.S. at 223, 110 USPQ2d at 1983. See also 573 U.S. at 224, 110 USPQ2d at 1984 (warning against a § 101 analysis that turns on “the draftsman’s art”). This “hardware configuration” (e.g., a “processor”, or set of processors) limitation does not integrate the additional element into a practical application and represents “insignificant extra-solution activity”. (See, M.P.E.P. § 2106.05(I)(A)). (2) An “execution” of the “hypothesis evaluation task through the hardware implementation” is a broad term which is described at a high level. M.P.E.P. § 2016.05(f) recites: 2106.05(f) Mere Instructions To Apply An Exception [R-10.2019] Another consideration when determining whether a claim integrates a judicial exception into a practical application in Step 2A Prong Two or recites significantly more than a judicial exception in Step 2B is whether the additional elements amount to more than a recitation of the words “apply it” (or an equivalent) or are more than mere instructions to implement an abstract idea or other exception on a computer. As explained by the Supreme Court, in order to make a claim directed to a judicial exception patent-eligible, the additional element or combination of elements must do “‘more than simply stat[e] the [judicial exception] while adding the words ‘apply it’”. Alice Corp. v. CLS Bank, 573 U.S. 208, 221, 110 USPQ2d 1976, 1982-83 (2014) (quoting Mayo Collaborative Servs. V. Prometheus Labs., Inc., 566 U.S. 66, 72, 101 USPQ2d 1961, 1965). Thus, for example, claims that amount to nothing more than an instruction to apply the abstract idea using a generic computer do not render an abstract idea eligible. Alice Corp., 573 U.S. at 223, 110 USPQ2d at 1983. See also 573 U.S. at 224, 110 USPQ2d at 1984 (warning against a § 101 analysis that turns on “the draftsman’s art”). This “execution” of the “hypothesis evaluation task through the hardware implementation” limitation does not integrate the additional element into a practical application and represents “insignificant extra-solution activity”. (See, M.P.E.P. § 2106.05(I)(A)). (3) A “using” of “a hardware accelerator” is a broad term which is described at a high level. M.P.E.P. § 2106.05 (f) recites in part: 2106.05(f) Mere Instructions To Apply An Exception [R-10.2019] Another consideration when determining whether a claim integrates a judicial exception into a practical application in Step 2A Prong Two or recites significantly more than a judicial exception in Step 2B is whether the additional elements amount to more than a recitation of the words "apply it" (or an equivalent) or are more than mere instructions to implement an abstract idea or other exception on a computer. This “using” of “a hardware accelerator” limitation does not integrate the additional element into a practical application and represents “insignificant extra-solution activity”. (See, M.P.E.P. § 2106.05(I)(A)). (4) A “main controller” (implemented in an FPGA or an ASIC) is a broad term which is described at a high level. M.P.E.P. § 2106.05 (f) recites in part: 2106.05(f) Mere Instructions To Apply An Exception [R-10.2019] Another consideration when determining whether a claim integrates a judicial exception into a practical application in Step 2A Prong Two or recites significantly more than a judicial exception in Step 2B is whether the additional elements amount to more than a recitation of the words "apply it" (or an equivalent) or are more than mere instructions to implement an abstract idea or other exception on a computer. This “main controller” limitation does not integrate the additional element into a practical application and represents “insignificant extra-solution activity”. (See, M.P.E.P. § 2106.05(I)(A)). (5) A “receiving” of “computation commands through communication with a host system and capable of decoding the received commands” is a broad term which is described at a high level. M.P.E.P. § 2106.05(g) recites: 2106.05(g) Insignificant Extra-Solution Activity [R-10.2019] Another consideration when determining whether a claim integrates the judicial exception into a practical application in Step 2A Prong Two or recites significantly more in Step 2B is whether the additional elements add more than insignificant extra-solution activity to the judicial exception. The term “extra-solution activity” can be understood as activities incidental to the primary process or product that are merely a nominal or tangential addition to the claim. Extra-solution activity includes both pre-solution and post-solution activity. This “receiving” of “computation commands through communication with a host system and capable of decoding the received commands” limitation does not integrate the additional element into a practical application and represents “insignificant extra-solution activity”. (See, M.P.E.P. § 2106.05(I)(A)). The answer to the inquiry is “NO”, no additional elements integrate the claimed abstract idea into a practical application. Step 2B inquiry: Does the claim provide an inventive concept, i.e., does the claim recite additional element(s) or a combination of elements that amount to significantly more than the judicial exception in the claim? Applicant’s claims contain the following “additional elements”: (1) A “hardware configuration”/ “circuit” (2) An “execution” of the “hypothesis evaluation task through the hardware implementation” (3) A “using” of “a hardware accelerator” (4) A “main controller” (5) A “receiving” of “computation commands through communication with a host system and capable of decoding the received commands” (1) A “hardware configuration”/ “circuit” (e.g., a “processor”, or set of processors) is a broad term which is described at a high level and includes multiple general purpose computers. Applicant's Specification recites: [0005] Hardware-based acceleration of computer operations is performed using Description Logic (DL) language in inductive logic programming (ILP) instructions for performing a hypothesis evaluation task. At least a subset of the instructions are expressed as logic-based rules or textual-like descriptions, in a form capable of interpretation by both humans and machines. A knowledge base interpretable by Inductive Logic Programming (ILP) is selected. A set of concept axioms enforces a set of logic-based constraints on the knowledge base, in which the logic-based constraints establish reasoning tasks on the knowledge base using the ILP. A hardware configuration is used to implement the established reasoning tasks through a hardware implementation, and the knowledge base and the set of concept axioms are used to perform the hypothesis evaluation task, which is executed through the hardware implementation. Further, Applicant's Specification recites: [0031] ILP as one of the ML techniques struggle in the scalability aspect; especially since ILP algorithms (in many cases) are inherently sequential algorithms, which introduces major challenges for speeding up their computations. This ILP scalability challenge, has resulted in many approaches being developed to address these inherent deficiencies; however, many of these approaches (especially the ones based on parallel computing), rely on using software based solutions (e.g., CPUs and GPUs), and overlook the potential performance gains of hardware based solutions (e.g., FPGAs and ASICs). One key advantage of dedicated hardware designs (i.e., a hardware specifically designed for a particular purpose) is that they have much more parallel computing capabilities and consume much less power than software solutions. In other words, the number of parallel processing logic in CPUs and GPUs is fixed; while an FPGA (a common form of a hardware solution), has much more parallel processing capability that can be used (or configured) to improve performance. Even though FPGAs (as a hardware solution) consume much less power than software solutions (for the same computations), even more power efficiency can be obtained through an ASICs hardware solution. However, ASICs are more expensive to design and manufacture (as opposed to FPGAs). [0032] The disclosed concept implements description logic and inductive logic programming. In a non-limiting example, a hardware-based approach is implemented. Note that Applicant's claimed “hardware configuration” has support in the Specification, paragraph [0031], where it recites “hardware based solutions (e.g., FPGAs and ASICs)”. Note that the term does not specify how the solutions are “based” on hardware. It does not exclude programmable systems, since FPGAs (Field Programmable Gate Arrays) are programmable and reprogrammable (therefore, this makes them dependent on software). Further, the use of multiple FPGAs may include the use of software (e.g., for managing inter-FPGA communication.) The scope of the term includes programmable systems, including additional generic CPUs, which are “hardware based”. Further, Applicant's Specification recites: [0061] Fig. 4 is a schematic block diagram showing a comparison between software-based and hardware based approaches on accelerating ML computations, showing characteristics of ML acceleration. First, scalar CPU multi-threading ("CPU MT.(S)") is relatively the easiest acceleration method for accelerating computations; however, this method also provides the least performance speed increases. In many implementation cases(of this acceleration method), the vector/SIMD instruction set, available in modern CPUs, are typically ignored - this results in less efficient use of CPU's computing capabilities. On the other hand, in the second acceleration method which is vectorized CPU multithreading ("CPU MT.(V)"), will provide much higher performance gains than pure (scalar) multithreading; however, with two key disadvantages. First, the needed development skill is higher (than for scalar multithreading), because proper utilization of a CPU's vector instruction set, requires deep understanding of the CPU's architecture; moreover, some CPUs may have different vector instruction set, than other CPUs, e.g., SSE (Streaming SIMD Extensions) and AVX (Advanced Vector Extensions) for Intel and AMD CPUs, and Neon for ARM CPUs. The second disadvantage for vectorized CPU15 multithreading (especially with CPUs with large core counts) is that despite the much larger performance gains (than scalar multithreading); the CPU's cores together with each core's vector instructions will saturate the memory bandwidth, which will impose an upper limit on how much performance speed increases can be achieved. M.P.E.P. § 2016.05(f) recites: 2106.05(f) Mere Instructions To Apply An Exception [R-10.2019] Another consideration when determining whether a claim integrates a judicial exception into a practical application in Step 2A Prong Two or recites significantly more than a judicial exception in Step 2B is whether the additional elements amount to more than a recitation of the words “apply it” (or an equivalent) or are more than mere instructions to implement an abstract idea or other exception on a computer. As explained by the Supreme Court, in order to make a claim directed to a judicial exception patent-eligible, the additional element or combination of elements must do “‘more than simply stat[e] the [judicial exception] while adding the words ‘apply it’”. Alice Corp. v. CLS Bank, 573 U.S. 208, 221, 110 USPQ2d 1976, 1982-83 (2014) (quoting Mayo Collaborative Servs. V. Prometheus Labs., Inc., 566 U.S. 66, 72, 101 USPQ2d 1961, 1965). Thus, for example, claims that amount to nothing more than an instruction to apply the abstract idea using a generic computer do not render an abstract idea eligible. Alice Corp., 573 U.S. at 223, 110 USPQ2d at 1983. See also 573 U.S. at 224, 110 USPQ2d at 1984 (warning against a § 101 analysis that turns on “the draftsman’s art”). Therefore, the claim as a whole does not amount to significantly more than the exception itself (i.e., there is no inventive concept in the claim). (See, M.P.E.P. § 2106.05(II)). (2) An “execution” of the “hypothesis evaluation task through the hardware implementation” is a broad term which is described at a high level. Applicant’s Specification recites: M.P.E.P. § 2016.05(f) recites: 2106.05(f) Mere Instructions To Apply An Exception [R-10.2019] Another consideration when determining whether a claim integrates a judicial exception into a practical application in Step 2A Prong Two or recites significantly more than a judicial exception in Step 2B is whether the additional elements amount to more than a recitation of the words “apply it” (or an equivalent) or are more than mere instructions to implement an abstract idea or other exception on a computer. As explained by the Supreme Court, in order to make a claim directed to a judicial exception patent-eligible, the additional element or combination of elements must do “‘more than simply stat[e] the [judicial exception] while adding the words ‘apply it’”. Alice Corp. v. CLS Bank, 573 U.S. 208, 221, 110 USPQ2d 1976, 1982-83 (2014) (quoting Mayo Collaborative Servs. V. Prometheus Labs., Inc., 566 U.S. 66, 72, 101 USPQ2d 1961, 1965). Thus, for example, claims that amount to nothing more than an instruction to apply the abstract idea using a generic computer do not render an abstract idea eligible. Alice Corp., 573 U.S. at 223, 110 USPQ2d at 1983. See also 573 U.S. at 224, 110 USPQ2d at 1984 (warning against a § 101 analysis that turns on “the draftsman’s art”). Therefore, the claim as a whole does not amount to significantly more than the exception itself (i.e., there is no inventive concept in the claim). (See, M.P.E.P. § 2106.05(II)). (3) An “using” of “a hardware accelerator” is a broad term which is described at a high level. M.P.E.P. § 2106.05 (f) recites in part: 2106.05(f) Mere Instructions To Apply An Exception [R-10.2019] Another consideration when determining whether a claim integrates a judicial exception into a practical application in Step 2A Prong Two or recites significantly more than a judicial exception in Step 2B is whether the additional elements amount to more than a recitation of the words "apply it" (or an equivalent) or are more than mere instructions to implement an abstract idea or other exception on a computer. Applicant’s Specification, paragraph [00139] recites: [00139] The current accelerator design is disclosed as a general hardware-based design that doesn't target (or is not optimized for) a particular hardware implementation (e.g., FPGA), as a potential future refinement. Since the disclosed current accelerator design is a general hardware-based design, an optimized version of the accelerator design could be implemented which is optimized for FPGA-based implementations. For other implementations, more DL operations could be supported to increase the expressivity of the used DL language. Therefore, the claim as a whole does not amount to significantly more than the exception itself (i.e., there is no inventive concept in the claim). (See, M.P.E.P. § 2106.05(II)). (4) An “main controller” is a broad term which is described at a high level. M.P.E.P. § 2106.05 (f) recites in part: 2106.05(f) Mere Instructions To Apply An Exception [R-10.2019] Another consideration when determining whether a claim integrates a judicial exception into a practical application in Step 2A Prong Two or recites significantly more than a judicial exception in Step 2B is whether the additional elements amount to more than a recitation of the words "apply it" (or an equivalent) or are more than mere instructions to implement an abstract idea or other exception on a computer. Applicant’s Specification, paragraph [0056] recites: [0056] The disclosed hardware design can either be implemented in an FPGA or an ASIC; however, an FPGA implementation is used to evaluate the performance of the disclosed design. In a comparison between the disclosed accelerator design and the accelerator developed by the researchers in the disclosed accelerator targets improving the performance of hypothesis evaluation for DL-based ILPs in embedded environments; whereas, the researchers' Prolog accelerator target accelerating hypothesis evaluation for the traditional (FOL-based) ILP learners. The disclosed accelerator (in its current state) targets speeding up computations for a single hypothesis, while the researchers' accelerator targets speeding up computations for a single hypothesis (through a single WAM), and multiple hypotheses (through multiple WAMs implemented on the same chip). Therefore, the claim as a whole does not amount to significantly more than the exception itself (i.e., there is no inventive concept in the claim). (See, M.P.E.P. § 2106.05(II)). (5) An “receiving” of “computation commands through communication with a host system and capable of decoding the received commands” is a broad term which is described at a high level. M.P.E.P. § 2106.05(d)(II) recites: The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network); … Further, M.P.E.P. § 2106.05(d)(I)(2) recites in part: 2. A factual determination is required to support a conclusion that an additional element (or combination of additional elements) is well-understood, routine, conventional activity. Berkheimer v. HP, Inc., 881 F.3d 1360, 1368, 125 USPQ2d 1649, 1654 (Fed. Cir. 2018). However, this does not mean that a prior art search is necessary to resolve this inquiry. Instead, examiners should rely on what the courts have recognized, or those in the art would recognize, as elements that are well-understood, routine, conventional activity in the relevant field when making the required determination. For example, in many instances, the specification of the application may indicate that additional elements are well-known or conventional. See, e.g., Intellectual Ventures v. Symantec, 838 F.3d at 1317; 120 USPQ2d at 1359 ("The written description is particularly useful in determining what is well-known or conventional"); Internet Patents Corp. v. Active Network, Inc., 790 F.3d 1343, 1348, 115 USPQ2d 1414, 1418 (Fed. Cir. 2015) (relying on specification’s description of additional elements as "well-known", "common" and "conventional"); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 614, 118 USPQ2d 1744, 1748 (Fed. Cir. 2016) (Specification described additional elements as "either performing basic computer functions such as sending and receiving data, or performing functions ‘known’ in the art."). Merely using the conventional computer to receive data is well known, understood, and conventional. Thus, it adds nothing significantly more to the judicial exception. The claim as a whole does not amount to significantly more than the exception itself (i.e., there is no inventive concept in the claim). (See, M.P.E.P. § 2106.05(II)). Therefore, the answer to the inquiry is “NO”, no additional elements provide an inventive concept that is significantly more than the claimed abstract ideas the claimed abstract idea into a practical application. Claim 1 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101. Claim 2 Claim 2 recites: 2. (original) The method as described in claim 1, wherein the execution of the hypothesis evaluation task provides hardware-based acceleration that accelerates hypothesis evaluation computations for the DL-based ILP learners used in the computer operations. Applicant’s Claim 2 merely teaches the mental steps of “hypothesis evaluation” practiced on a generic CPU. Applicant's Specification, paragraph [0061] recites the claimed hardware-based acceleration: [0061] Fig. 4 is a schematic block diagram showing a comparison between software-based and hardware based approaches on accelerating ML computations, showing characteristics of ML acceleration. First, scalar CPU multi-threading ("CPU MT.(S)") is relatively the easiest acceleration method for accelerating computations; however, this method also provides the least performance speed increases. In many implementation cases(of this acceleration method), the vector/SIMD instruction set, available in modern CPUs, are typically ignored - this results in less efficient use of CPU's computing capabilities. On the other hand, in the second acceleration method which is vectorized CPU multithreading ("CPU MT.(V)"), will provide much higher performance gains than pure (scalar) multithreading; however, with two key disadvantages. First, the needed development skill is higher (than for scalar multithreading), because proper utilization of a CPU's vector instruction set, requires deep understanding of the CPU's architecture; moreover, some CPUs may have different vector instruction set, than other CPUs, e.g., SSE (Streaming SIMD Extensions) and AVX (Advanced Vector Extensions) for Intel and AMD CPUs, and Neon for ARM CPUs. The second disadvantage for vectorized CPU15 multithreading (especially with CPUs with large core counts) is that despite the much larger performance gains (than scalar multithreading); the CPU's cores together with each core's vector instructions will saturate the memory bandwidth, which will impose an upper limit on how much performance speed increases can be achieved. It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).) Claim 2 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101. Claim 3 Claim 3 recites: 3. The method as described in claim 1, further comprising: representing outputs of DL operations as the reasoning tasks for a given DL hypothesis as a logical matrix. Applicant’s Claim 3 merely teaches a “representation” (i.e., mental step) of outputs. It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).) Claim 3 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101. Claim 4 Claim 4 recites: 4. The method as described in claim 1, further comprising: representing outputs of DL operations as the reasoning tasks for a given DL hypothesis as a logical matrix, so that each matrix represents an aspect of the DL knowledge base, wherein a results matrix represents the outputs of DL operations for a given DL hypothesis, wherein the DL accesses a concepts matrix, and wherein a results matrix provides an output storage configuration. Applicant’s Claim 4 merely teaches data matrices (i.e., mental steps). It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).) Claim 4 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101. Claim 5 Claim 5 recites: 5. The method as described in claim 1, further comprising: representing the DL operations as the reasoning tasks for a given DL hypothesis as a logical matrix, wherein each matrix represents an aspect of the DL knowledge base, with a results matrix representing the outputs of DL operations for a given DL hypothesis; and providing a results matrix as an output. Applicant’s Claim 5 merely teaches representations of operations and data (i.e., mental steps). It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).) Claim 5 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101. Claim 6 Claim 6 recites: 6. The method as described in claim 1, further comprising: performing the DL operations while retrieving input data; and initiating processing of the retrieved data as the retrieve data becomes available without waiting until completion of a burst read operation. Applicant’s Claim 6 merely teaches data processing (i.e., mental step). It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).) Claim 6 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101. Claim 7 Claim 7 recites: 7. The method as described in claim 1, wherein using the hardware configuration to implement the established reasoning tasks provides an acceleration function to accelerate performance for ILP-related computations. Applicant’s Claim 7 merely teaches executed reasoning tasks (i.e., mental steps). It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).) Claim 7 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101. Claim 8 Claim 8 recites: 8. The method as described in claim 1, wherein using the hardware configuration to implement the established reasoning tasks provides an acceleration function to accelerate performance for ILP-related computations comprising hypothesis evaluation computations. Applicant’s Claim 8 merely teaches reasoning tasks (i.e., mental steps). It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).) Claim 8 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101. Claim 10 Step 1 inquiry: Does this claim fall within a statutory category? The preamble of the claim recites “10. A hardware-based accelerator comprising…” An “accelerator” is not a “process,” “product of manufacture,” “composition of matter,” or “apparatus.” Therefore, it is NOT a statutory category of invention. Therefore, the answer to the inquiry is: “NO”. Step 2A (Prong One) inquiry: Are there limitations in Claim 10 that recite abstract ideas? YES. The following limitations in Claim 10 recite abstract ideas that fall within at least one of the groupings of abstract ideas enumerated in the 2019 PEG. Specifically, they are “mental steps” and “mathematical steps”: • instructions (i.e., mental steps) • a subset of said instructions expressed as logic-based rules or textual-like descriptions, in a form capable of interpretation by both humans and machines (i.e., mental steps) • selecting a knowledge base (i.e., mental steps) • selecting a set of concept axioms (i.e., mental steps) • applying the knowledge base and the set of concept axioms to perform the hypothesis evaluation task (i.e., mental steps) • performing a hypothesis search (i.e., mental steps) • scanning each assertion to find at least one assertion that matches specific conditions (i.e., mental steps) • selecting one or more hypotheses as DL hypotheses (i.e., mental steps) • evaluating at least one of the DL hypothesis (i.e., mental steps) • for each DL hypothesis, using the computed examples coverage to compute an evaluation score for the given hypothesis (i.e., mathematical steps) • determine the type of DL operation to be computed (i.e., mental steps) • “passing a retrieved memory address offset to a Binary Assertions Unit (BAU), the BAU further comprising a relationship operations sub-unit and a literal operations sub-unit” (i.e., mental steps) Applicant’s Specification, paragraph [0038] recites: [0038] As a logic-based representation, DL describes a knowledge base using instances (individuals), concepts and roles; where a DL knowledge base consists of an A-Box (assertions box) and a T-Box (terminological box). An A-Box contains the assertions (or ground facts), which in DL, can be unary and binary assertions. A unary (concept) assertion takes the form a:C where a is an individual and C is concept. A binary (role) assertion takes the form (a,b):r, by which r is the role, and both a and b are individuals; where a is the subject and b is the object of the role assertion. Examples for unary and binary assertions, can be seen in Table 1: Further, Applicant’s Specification, paragraph [0005] recites: [0005] Hardware-based acceleration of computer operations is performed using Description Logic (DL) language in inductive logic programming (ILP) instructions for performing a hypothesis evaluation task. At least a subset of the instructions are expressed as logic-based rules or textual-like descriptions, in a form capable of interpretation by both humans and machines. A knowledge base interpretable by Inductive Logic Programming (ILP) is selected. A set of concept axioms enforces a set of logic-based constraints on the knowledge base, in which the logic-based constraints establish reasoning tasks on the knowledge base using the ILP. A hardware configuration is used to implement the established reasoning tasks through a hardware implementation, and the knowledge base and the set of concept axioms are used to perform the hypothesis evaluation task, which is executed through the hardware implementation. • the relationship operations sub-unit and literal operations sub-unit capable of computing: - existential role restrictions, - universal role restrictions, - cardinality role restrictions - numeric role restriction. - string (EQUAL and NOT EQUAL) role restrictions: (i.e., mental steps) Applicant’s Specification, paragraph [0005] recites: [0005] Hardware-based acceleration of computer operations is performed using Description Logic (DL) language in inductive logic programming (ILP) instructions for performing a hypothesis evaluation task. At least a subset of the instructions are expressed as logic-based rules or textual-like descriptions, in a form capable of interpretation by both humans and machines. A knowledge base interpretable by Inductive Logic Programming (ILP) is selected. A set of concept axioms enforces a set of logic-based constraints on the knowledge base, in which the logic-based constraints establish reasoning tasks on the knowledge base using the ILP. A hardware configuration is used to implement the established reasoning tasks through a hardware implementation, and the knowledge base and the set of concept axioms are used to perform the hypothesis evaluation task, which is executed through the hardware implementation. • “a Unitary Assertions Unit (UAU) for computing conjunction and disjunction DL operations by receiving, processing and reporting the results of conjunction and disjunction operations” (i.e., mental steps) Applicant’s Specification, paragraph [0005] recites: [0005] Hardware-based acceleration of computer operations is performed using Description Logic (DL) language in inductive logic programming (ILP) instructions for performing a hypothesis evaluation task. At least a subset of the instructions are expressed as logic-based rules or textual-like descriptions, in a form capable of interpretation by both humans and machines. A knowledge base interpretable by Inductive Logic Programming (ILP) is selected. A set of concept axioms enforces a set of logic-based constraints on the knowledge base, in which the logic-based constraints establish reasoning tasks on the knowledge base using the ILP. A hardware configuration is used to implement the established reasoning tasks through a hardware implementation, and the knowledge base and the set of concept axioms are used to perform the hypothesis evaluation task, which is executed through the hardware implementation. • a result memory address offset lookup table and a concept memory address offset lookup table” (i.e., mental steps) Step 2A (Prong Two) inquiry: Are there additional elements or a combination of elements in the claim that apply, rely on, or use the judicial exception in a manner that imposes a meaningful limit on the judicial exception, such that it is more than a drafting effort designed to monopolize the exception? Applicant’s claims contain the following “additional elements”: A “circuit” (2) A “using” of “a hardware accelerator” (3) A “main controller” (4) A “receiving” of “computation commands through communication with a host system and capable of decoding the received commands” (1) A “circuit” (e.g., a “processor” , or set of processors) is a broad term which is described at a high level and includes multiple general purpose computers. Note that there is no teaching of a “circuit” in the Specification. There are, however, teachings of well-understood, routine, and conventional computers. Applicant's Specification recites: [0005] Hardware-based acceleration of computer operations is performed using Description Logic (DL) language in inductive logic programming (ILP) instructions for performing a hypothesis evaluation task. At least a subset of the instructions are expressed as logic-based rules or textual-like descriptions, in a form capable of interpretation by both humans and machines. A knowledge base interpretable by Inductive Logic Programming (ILP) is selected. A set of concept axioms enforces a set of logic-based constraints on the knowledge base, in which the logic-based constraints establish reasoning tasks on the knowledge base using the ILP. A hardware configuration is used to implement the established reasoning tasks through a hardware implementation, and the knowledge base and the set of concept axioms are used to perform the hypothesis evaluation task, which is executed through the hardware implementation. Further, Applicant's Specification recites: [0031] ILP as one of the ML techniques struggle in the scalability aspect; especially since ILP algorithms (in many cases) are inherently sequential algorithms, which introduces major challenges for speeding up their computations. This ILP scalability challenge, has resulted in many approaches being developed to address these inherent deficiencies; however, many of these approaches (especially the ones based on parallel computing), rely on using software based solutions (e.g., CPUs and GPUs), and overlook the potential performance gains of hardware based solutions (e.g., FPGAs and ASICs). One key advantage of dedicated hardware designs (i.e., a hardware specifically designed for a particular purpose) is that they have much more parallel computing capabilities and consume much less power than software solutions. In other words, the number of parallel processing logic in CPUs and GPUs is fixed; while an FPGA (a common form of a hardware solution), has much more parallel processing capability that can be used (or configured) to improve performance. Even though FPGAs (as a hardware solution) consume much less power than software solutions (for the same computations), even more power efficiency can be obtained through an ASICs hardware solution. However, ASICs are more expensive to design and manufacture (as opposed to FPGAs). [0032] The disclosed concept implements description logic and inductive logic programming. In a non-limiting example, a hardware-based approach is implemented. Note that Applicant's claimed “hardware configuration” has support in the Specification, paragraph [0031], where it recites “hardware based solutions (e.g., FPGAs and ASICs)”. Note that the term does not specify how the solutions are “based” on hardware. It does not exclude programmable systems, since FPGAs (Field Programmable Gate Arrays) are programmable and reprogrammable (therefore, this makes them dependent on software). Further, the use of multiple FPGAs may include the use of software (e.g., for managing inter-FPGA communication.) The scope of the term includes programmable systems, including additional generic CPUs, which are “hardware based”. Further, Applicant's Specification recites: [0061] Fig. 4 is a schematic block diagram showing a comparison between software-based and hardware based approaches on accelerating ML computations, showing characteristics of ML acceleration. First, scalar CPU multi-threading ("CPU MT.(S)") is relatively the easiest acceleration method for accelerating computations; however, this method also provides the least performance speed increases. In many implementation cases(of this acceleration method), the vector/SIMD instruction set, available in modern CPUs, are typically ignored - this results in less efficient use of CPU's computing capabilities. On the other hand, in the second acceleration method which is vectorized CPU multithreading ("CPU MT.(V)"), will provide much higher performance gains than pure (scalar) multithreading; however, with two key disadvantages. First, the needed development skill is higher (than for scalar multithreading), because proper utilization of a CPU's vector instruction set, requires deep understanding of the CPU's architecture; moreover, some CPUs may have different vector instruction set, than other CPUs, e.g., SSE (Streaming SIMD Extensions) and AVX (Advanced Vector Extensions) for Intel and AMD CPUs, and Neon for ARM CPUs. The second disadvantage for vectorized CPU15 multithreading (especially with CPUs with large core counts) is that despite the much larger performance gains (than scalar multithreading); the CPU's cores together with each core's vector instructions will saturate the memory bandwidth, which will impose an upper limit on how much performance speed increases can be achieved. M.P.E.P. § 2016.05(f) recites: 2106.05(f) Mere Instructions To Apply An Exception [R-10.2019] Another consideration when determining whether a claim integrates a judicial exception into a practical application in Step 2A Prong Two or recites significantly more than a judicial exception in Step 2B is whether the additional elements amount to more than a recitation of the words “apply it” (or an equivalent) or are more than mere instructions to implement an abstract idea or other exception on a computer. As explained by the Supreme Court, in order to make a claim directed to a judicial exception patent-eligible, the additional element or combination of elements must do “‘more than simply stat[e] the [judicial exception] while adding the words ‘apply it’”. Alice Corp. v. CLS Bank, 573 U.S. 208, 221, 110 USPQ2d 1976, 1982-83 (2014) (quoting Mayo Collaborative Servs. V. Prometheus Labs., Inc., 566 U.S. 66, 72, 101 USPQ2d 1961, 1965). Thus, for example, claims that amount to nothing more than an instruction to apply the abstract idea using a generic computer do not render an abstract idea eligible. Alice Corp., 573 U.S. at 223, 110 USPQ2d at 1983. See also 573 U.S. at 224, 110 USPQ2d at 1984 (warning against a § 101 analysis that turns on “the draftsman’s art”). This “circuit” (e.g., a “processor”, or set of processors) limitation does not integrate the additional element into a practical application and represents “insignificant extra-solution activity”. (See, M.P.E.P. § 2106.05(I)(A)). (2) A “using” of “a hardware accelerator” is a broad term which is described at a high level. M.P.E.P. § 2106.05 (f) recites in part: 2106.05(f) Mere Instructions To Apply An Exception [R-10.2019] Another consideration when determining whether a claim integrates a judicial exception into a practical application in Step 2A Prong Two or recites significantly more than a judicial exception in Step 2B is whether the additional elements amount to more than a recitation of the words "apply it" (or an equivalent) or are more than mere instructions to implement an abstract idea or other exception on a computer. This “using” of “a hardware accelerator” limitation does not integrate the additional element into a practical application and represents “insignificant extra-solution activity”. (See, M.P.E.P. § 2106.05(I)(A)). (3) A “main controller” (implemented in an FPGA or an ASIC) is a broad term which is described at a high level. M.P.E.P. § 2106.05 (f) recites in part: 2106.05(f) Mere Instructions To Apply An Exception [R-10.2019] Another consideration when determining whether a claim integrates a judicial exception into a practical application in Step 2A Prong Two or recites significantly more than a judicial exception in Step 2B is whether the additional elements amount to more than a recitation of the words "apply it" (or an equivalent) or are more than mere instructions to implement an abstract idea or other exception on a computer. This “main controller” limitation does not integrate the additional element into a practical application and represents “insignificant extra-solution activity”. (See, M.P.E.P. § 2106.05(I)(A)). (4) A “receiving” of “computation commands through communication with a host system and capable of decoding the received commands” is a broad term which is described at a high level. M.P.E.P. § 2106.05(g) recites: 2106.05(g) Insignificant Extra-Solution Activity [R-10.2019] Another consideration when determining whether a claim integrates the judicial exception into a practical application in Step 2A Prong Two or recites significantly more in Step 2B is whether the additional elements add more than insignificant extra-solution activity to the judicial exception. The term “extra-solution activity” can be understood as activities incidental to the primary process or product that are merely a nominal or tangential addition to the claim. Extra-solution activity includes both pre-solution and post-solution activity. This “receiving” of “computation commands through communication with a host system and capable of decoding the received commands” limitation does not integrate the additional element into a practical application and represents “insignificant extra-solution activity”. (See, M.P.E.P. § 2106.05(I)(A)). The answer to the inquiry is “NO”, no additional elements integrate the claimed abstract idea into a practical application. Step 2B inquiry: Does the claim provide an inventive concept, i.e., does the claim recite additional element(s) or a combination of elements that amount to significantly more than the judicial exception in the claim? Applicant’s claims contain the following “additional elements”: (1) A “circuit” (2) A “using” of “a hardware accelerator” (3) A “main controller” (4) A “receiving” of “computation commands through communication with a host system and capable of decoding the received commands” (1) A “circuit” (e.g., a “processor” , or set of processors) is a broad term which is described at a high level and includes multiple general purpose computers. Note that there is no teaching of a “circuit” in the Specification. There are, however, teachings of well-understood, routine, and conventional computers. Applicant's Specification recites: [0005] Hardware-based acceleration of computer operations is performed using Description Logic (DL) language in inductive logic programming (ILP) instructions for performing a hypothesis evaluation task. At least a subset of the instructions are expressed as logic-based rules or textual-like descriptions, in a form capable of interpretation by both humans and machines. A knowledge base interpretable by Inductive Logic Programming (ILP) is selected. A set of concept axioms enforces a set of logic-based constraints on the knowledge base, in which the logic-based constraints establish reasoning tasks on the knowledge base using the ILP. A hardware configuration is used to implement the established reasoning tasks through a hardware implementation, and the knowledge base and the set of concept axioms are used to perform the hypothesis evaluation task, which is executed through the hardware implementation. Further, Applicant's Specification recites: [0031] ILP as one of the ML techniques struggle in the scalability aspect; especially since ILP algorithms (in many cases) are inherently sequential algorithms, which introduces major challenges for speeding up their computations. This ILP scalability challenge, has resulted in many approaches being developed to address these inherent deficiencies; however, many of these approaches (especially the ones based on parallel computing), rely on using software based solutions (e.g., CPUs and GPUs), and overlook the potential performance gains of hardware based solutions (e.g., FPGAs and ASICs). One key advantage of dedicated hardware designs (i.e., a hardware specifically designed for a particular purpose) is that they have much more parallel computing capabilities and consume much less power than software solutions. In other words, the number of parallel processing logic in CPUs and GPUs is fixed; while an FPGA (a common form of a hardware solution), has much more parallel processing capability that can be used (or configured) to improve performance. Even though FPGAs (as a hardware solution) consume much less power than software solutions (for the same computations), even more power efficiency can be obtained through an ASICs hardware solution. However, ASICs are more expensive to design and manufacture (as opposed to FPGAs). [0032] The disclosed concept implements description logic and inductive logic programming. In a non-limiting example, a hardware-based approach is implemented. Note that Applicant's claimed “hardware configuration” has support in the Specification, paragraph [0031], where it recites “hardware based solutions (e.g., FPGAs and ASICs)”. Note that the term does not specify how the solutions are “based” on hardware. It does not exclude programmable systems, since FPGAs (Field Programmable Gate Arrays) are programmable and reprogrammable (therefore, this makes them dependent on software). Further, the use of multiple FPGAs may include the use of software (e.g., for managing inter-FPGA communication.) The scope of the term includes programmable systems, including additional generic CPUs, which are “hardware based”. Further, Applicant's Specification recites: [0061] Fig. 4 is a schematic block diagram showing a comparison between software-based and hardware based approaches on accelerating ML computations, showing characteristics of ML acceleration. First, scalar CPU multi-threading ("CPU MT.(S)") is relatively the easiest acceleration method for accelerating computations; however, this method also provides the least performance speed increases. In many implementation cases(of this acceleration method), the vector/SIMD instruction set, available in modern CPUs, are typically ignored - this results in less efficient use of CPU's computing capabilities. On the other hand, in the second acceleration method which is vectorized CPU multithreading ("CPU MT.(V)"), will provide much higher performance gains than pure (scalar) multithreading; however, with two key disadvantages. First, the needed development skill is higher (than for scalar multithreading), because proper utilization of a CPU's vector instruction set, requires deep understanding of the CPU's architecture; moreover, some CPUs may have different vector instruction set, than other CPUs, e.g., SSE (Streaming SIMD Extensions) and AVX (Advanced Vector Extensions) for Intel and AMD CPUs, and Neon for ARM CPUs. The second disadvantage for vectorized CPU15 multithreading (especially with CPUs with large core counts) is that despite the much larger performance gains (than scalar multithreading); the CPU's cores together with each core's vector instructions will saturate the memory bandwidth, which will impose an upper limit on how much performance speed increases can be achieved. M.P.E.P. § 2016.05(f) recites: 2106.05(f) Mere Instructions To Apply An Exception [R-10.2019] Another consideration when determining whether a claim integrates a judicial exception into a practical application in Step 2A Prong Two or recites significantly more than a judicial exception in Step 2B is whether the additional elements amount to more than a recitation of the words “apply it” (or an equivalent) or are more than mere instructions to implement an abstract idea or other exception on a computer. As explained by the Supreme Court, in order to make a claim directed to a judicial exception patent-eligible, the additional element or combination of elements must do “‘more than simply stat[e] the [judicial exception] while adding the words ‘apply it’”. Alice Corp. v. CLS Bank, 573 U.S. 208, 221, 110 USPQ2d 1976, 1982-83 (2014) (quoting Mayo Collaborative Servs. V. Prometheus Labs., Inc., 566 U.S. 66, 72, 101 USPQ2d 1961, 1965). Thus, for example, claims that amount to nothing more than an instruction to apply the abstract idea using a generic computer do not render an abstract idea eligible. Alice Corp., 573 U.S. at 223, 110 USPQ2d at 1983. See also 573 U.S. at 224, 110 USPQ2d at 1984 (warning against a § 101 analysis that turns on “the draftsman’s art”). The claim as a whole does not amount to significantly more than the exception itself (i.e., there is no inventive concept in the claim). (See, M.P.E.P. § 2106.05(II)). (2) An “using” of “a hardware accelerator” is a broad term which is described at a high level. M.P.E.P. § 2106.05 (f) recites in part: 2106.05(f) Mere Instructions To Apply An Exception [R-10.2019] Another consideration when determining whether a claim integrates a judicial exception into a practical application in Step 2A Prong Two or recites significantly more than a judicial exception in Step 2B is whether the additional elements amount to more than a recitation of the words "apply it" (or an equivalent) or are more than mere instructions to implement an abstract idea or other exception on a computer. Applicant’s Specification, paragraph [00139] recites: [00139] The current accelerator design is disclosed as a general hardware-based design that doesn't target (or is not optimized for) a particular hardware implementation (e.g., FPGA), as a potential future refinement. Since the disclosed current accelerator design is a general hardware-based design, an optimized version of the accelerator design could be implemented which is optimized for FPGA-based implementations. For other implementations, more DL operations could be supported to increase the expressivity of the used DL language. Therefore, the claim as a whole does not amount to significantly more than the exception itself (i.e., there is no inventive concept in the claim). (See, M.P.E.P. § 2106.05(II)). (3) An “main controller” is a broad term which is described at a high level. M.P.E.P. § 2106.05 (f) recites in part: 2106.05(f) Mere Instructions To Apply An Exception [R-10.2019] Another consideration when determining whether a claim integrates a judicial exception into a practical application in Step 2A Prong Two or recites significantly more than a judicial exception in Step 2B is whether the additional elements amount to more than a recitation of the words "apply it" (or an equivalent) or are more than mere instructions to implement an abstract idea or other exception on a computer. Applicant’s Specification, paragraph [0056] recites: [0056] The disclosed hardware design can either be implemented in an FPGA or an ASIC; however, an FPGA implementation is used to evaluate the performance of the disclosed design. In a comparison between the disclosed accelerator design and the accelerator developed by the researchers in the disclosed accelerator targets improving the performance of hypothesis evaluation for DL-based ILPs in embedded environments; whereas, the researchers' Prolog accelerator target accelerating hypothesis evaluation for the traditional (FOL-based) ILP learners. The disclosed accelerator (in its current state) targets speeding up computations for a single hypothesis, while the researchers' accelerator targets speeding up computations for a single hypothesis (through a single WAM), and multiple hypotheses (through multiple WAMs implemented on the same chip). Therefore, the claim as a whole does not amount to significantly more than the exception itself (i.e., there is no inventive concept in the claim). (See, M.P.E.P. § 2106.05(II)). (4) An “receiving” of “computation commands through communication with a host system and capable of decoding the received commands” is a broad term which is described at a high level. M.P.E.P. § 2106.05(d)(II) recites: The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network); … Further, M.P.E.P. § 2106.05(d)(I)(2) recites in part: 2. A factual determination is required to support a conclusion that an additional element (or combination of additional elements) is well-understood, routine, conventional activity. Berkheimer v. HP, Inc., 881 F.3d 1360, 1368, 125 USPQ2d 1649, 1654 (Fed. Cir. 2018). However, this does not mean that a prior art search is necessary to resolve this inquiry. Instead, examiners should rely on what the courts have recognized, or those in the art would recognize, as elements that are well-understood, routine, conventional activity in the relevant field when making the required determination. For example, in many instances, the specification of the application may indicate that additional elements are well-known or conventional. See, e.g., Intellectual Ventures v. Symantec, 838 F.3d at 1317; 120 USPQ2d at 1359 ("The written description is particularly useful in determining what is well-known or conventional"); Internet Patents Corp. v. Active Network, Inc., 790 F.3d 1343, 1348, 115 USPQ2d 1414, 1418 (Fed. Cir. 2015) (relying on specification’s description of additional elements as "well-known", "common" and "conventional"); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 614, 118 USPQ2d 1744, 1748 (Fed. Cir. 2016) (Specification described additional elements as "either performing basic computer functions such as sending and receiving data, or performing functions ‘known’ in the art."). Merely using the conventional computer to receive data is well known, understood, and conventional. Thus, it adds nothing significantly more to the judicial exception. The claim as a whole does not amount to significantly more than the exception itself (i.e., there is no inventive concept in the claim). (See, M.P.E.P. § 2106.05(II)). Therefore, the answer to the inquiry is “NO”, no additional elements provide an inventive concept that is significantly more than the claimed abstract ideas the claimed abstract idea into a practical application. Claim 10 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101. Claim 11 Claim 11 recites: 11. (original) The hardware-based accelerator as described in claim 10, wherein the circuit for execution of the hypothesis evaluation task provides hardware-based acceleration that accelerates hypothesis evaluation computations for the DL-based ILP learners used in the computer operations. Applicant’s Claim 11 merely teaches the mental steps of “hypothesis evaluation” practiced on a generic CPU. Applicant's Specification, paragraph [0061] recites the claimed hardware-based acceleration: [0061] Fig. 4 is a schematic block diagram showing a comparison between software-based and hardware based approaches on accelerating ML computations, showing characteristics of ML acceleration. First, scalar CPU multi-threading ("CPU MT.(S)") is relatively the easiest acceleration method for accelerating computations; however, this method also provides the least performance speed increases. In many implementation cases(of this acceleration method), the vector/SIMD instruction set, available in modern CPUs, are typically ignored - this results in less efficient use of CPU's computing capabilities. On the other hand, in the second acceleration method which is vectorized CPU multithreading ("CPU MT.(V)"), will provide much higher performance gains than pure (scalar) multithreading; however, with two key disadvantages. First, the needed development skill is higher (than for scalar multithreading), because proper utilization of a CPU's vector instruction set, requires deep understanding of the CPU's architecture; moreover, some CPUs may have different vector instruction set, than other CPUs, e.g., SSE (Streaming SIMD Extensions) and AVX (Advanced Vector Extensions) for Intel and AMD CPUs, and Neon for ARM CPUs. The second disadvantage for vectorized CPU15 multithreading (especially with CPUs with large core counts) is that despite the much larger performance gains (than scalar multithreading); the CPU's cores together with each core's vector instructions will saturate the memory bandwidth, which will impose an upper limit on how much performance speed increases can be achieved. It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).) Claim 11 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101. Claim 12 Claim 12 recites: 12. The hardware-based accelerator as described in claim 10, further comprising: a circuit for representing outputs of DL operations as the reasoning tasks for a given DL hypothesis as a logical matrix. Applicant’s Claim 12 merely teaches a generic “circuit” (or, CPU). It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).) Claim 12 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101. Claim 13 Claim 13 recites: 13. The hardware-based accelerator as described in claim 10, further comprising: a circuit for representing outputs of DL operations as the reasoning tasks for a given DL hypothesis as a logical matrix, so that each matrix represents an aspect of the DL knowledge base, wherein a results matrix represents the outputs of DL operations for a given DL hypothesis, wherein the DL accesses a concepts matrix, and wherein a results matrix provides an output storage configuration. Applicant’s Claim 13 merely teaches a generic “circuit” (or, CPU). It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).) Claim 13 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101. Claim 14 Claim 14 recites: 14. The hardware-based accelerator as described in claim 10, further comprising: a circuit for representing the DL operations as the reasoning tasks for a given DL hypothesis as a logical matrix, wherein each matrix represents an aspect of the DL knowledge base, with a results matrix representing the outputs of DL operations for a given DL hypothesis; and a circuit for providing a results matrix as an output. Applicant’s Claim 14 merely teaches a generic “circuit” (or, CPU). It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).) Claim 14 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101. Claim 15 Claim 15 recites: 15. The hardware-based accelerator as described in claim 10, wherein the circuit for performing the DL operations performs said DL operations while retrieving input data, and initiates processing of the retrieved data as the retrieve data becomes available without waiting until completion of a burst read operation. Applicant’s Claim 15 merely teaches a generic “circuit” (or, CPU). It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).) Claim 15 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101. Claim 16 Claim 16 recites: 16. The hardware-based accelerator as described in claim 10, wherein using the accelerator provides a hardware configuration to implement the established reasoning tasks provides an acceleration function to accelerate performance for ILP-related computations comprising hypothesis evaluation computations. Applicant’s Claim 16 merely teaches a generic “hardware configuration” (or, CPU). It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).) Claim 16 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101. Response to Arguments Applicant's arguments filed 02 JUN 2026 have been fully considered but they are not persuasive. Specifically, Applicant argues: Argument 1 The Examiner rejected claim 9 under 35 U.S.C. §112(b), as being indefinite, in that the description of, "A hardware-based accelerator" did not further limit the "circuit" claimed in claim 1. Response Applicant cancels claim 9, which obviates this rejection. Withdrawal of the rejection under 35 U.S.C. §112 is therefore respectfully requested. The 35 U.S.C. §112(b) is WITHDRAWN. Argument 2 Independent claims 1 and 10 now describe specific features of Applicant's hardware accelerator, in which a main controller receives and decodes commands to determine the type of Description Logic (DL) operations, and passes memory address offsets to a Binary Assertions Unit (BAU) having a relationship operations sub-unit and a literal operations sub-unit, with the relationship operations sub-unit and literal operations sub-unit capable of computing specified restrictions, a Unitary Assertions Unit (UAU) conjunction and disjunction DL operations, and memory address offset lookup tables. It is submitted that these hardware components present a physical circuit architecture that provides digital logic that accelerates a particular set of computations for the hypothesis evaluation task; the hypothesis evaluation task is a key computational step in inductive logic programming (ILP). ILP is a machine learning (ML) technique, which is typically implemented as a sub-field of artificial intelligence. The ML models constructed by ILP algorithms are textual rules that describe complex and multi-relational concepts. These textual rules are expressed using a logic formalism such as first order logic and description logic. Accordingly, Applicant's claimed technology is a dedicated processor architecture for accelerating ILP computations. Each component in this dedicated processor design employs a set of sub-computations to complete its specialized computations. As such, the learned textual rules do not per se require computer implementation of human activity. The learned textual rules can be interpreted and understood by both humans and machines (computers). The claims present technology that is neither based on "mental steps"; but rather a tangible physical architecture that meets the subject matter eligibility under 35 U.S.C. §101 as presented under Alice. The mere use of computerized methods, algorithms and the like are not automatically excluded categories of subject matter; i.e., they are not, in and of themselves, necessarily abstract ideas. While such claims may include an abstract idea, further analysis of the claim as a whole is required to determine eligibility under Alice. Rather, the claims present, "an improvement in the functioning of a computer or other technology or technological field, which is patent eligible at step one of the Alice/Mayo test even if it recites an abstract idea, law of nature, or natural phenomenon." See the USPTO 2019 Revised Patent Subject Matter Eligibility Guidance, as well as McRO, Inc. V. Bandai Namco Games Am. Inc., 837 F.3d 1299, 1316 (Fed. Cir. 2016); Enfish, LLC v. Microsoft Corp., 822 F. 3d 1327 (Fed. Cir. 2016); and Core Wireless Licensing S.A.R.L. V. LG Electronics, Inc. 880 F.3d 1356 (Fed. Cir. 2018). The present claims are directed towards a method of providing hardware acceleration which, when viewed as a whole, clearly provides an improved operational method, representative of an improvement in the technological field of hardware accelerators. Each of these new amendments is addressed in the rejection, above. In short, Applicant does not claim a specially designed computer. Applicant claims the logic that may be embodied into an FPGA. That is, Applicant makes standard use of an FPGA to embody unspecified logic. Applicant's argument is unpersuasive. The rejections stand. Argument 3 Applicant further references the patent eligibility as a "real world" implementation under the two-prong test of patent eligibility under Alice as detailed in Applicant's August 13, 2025, Response, which Applicant incorporates by reference. Accordingly, it is submitted that claims 1-8 and 10-16 are in a condition for allowance. Applicant does not claim anything significantly more than the abstract ideas, themselves. Applicant's argument is unpersuasive. The rejections stand. Argument 4 Allowed Claims Applicant notes that claims 1-8 and 10-16 (now presented as claims were not subject to prior art rejections. Applicant appreciates this indication of allowability over the art. Not rejected under art does not mean “allowed.” Applicant’s claims remain rejected under 35 U.S.C § 101. Applicant's argument is unpersuasive. The rejections stand. Claims Not Rejected Under Art Claims 1, 3-10, and 12-16 are not rejected under art because when reading the claims in light of the specification, as per MPEP § 2111.01, none of the references of record, whether taken alone or in combination, discloses or suggests the combination of limitations specified in independent Claim 1. Specifically, the closest prior art of Algahtani, A Hardware Approach For Accelerating Inductive Learning In Description Logic, ACM Transactions on Embedded Computing Systems, Volume 23, Issue 4, Article No.: 62, 29 JUN 2024, pp. 1 – 37 fails to expressly teach: Claim 1's "...DL hypotheses..." Claim 1's "...Description Logic hypotheses..." Claim 1's "...select a knowledge base interpretable by Inductive Logic Programming..." Claim 1's "...scanning each assertion..." Further, none of the references of record, whether taken alone or in combination, discloses or suggests the combination of limitations specified in independent Claim 10. Specifically, the closest prior art of Algahtani fails to expressly teach: Claim 10's "...DL hypotheses..." Claim 10's "...Description Logic hypotheses..." Claim 10's "...select a knowledge base interpretable by Inductive Logic Programming..." Claim 10's "...scanning each assertion..." Only to the extent that these limitations (specifically as defined above) are not found in the prior art of record is the present case not rejected under the prior art. Conclusion Any inquiries concerning this communication or earlier communications from the examiner should be directed to Wilbert L. Starks, Jr., who may be reached Monday through Friday, between 8:00 a.m. and 5:00 p.m. EST. or via telephone at (571) 272-3691 or email: Wilbert.Starks@uspto.gov. If you need to send an Official facsimile transmission, please send it to (571) 273-8300. If attempts to reach the examiner are unsuccessful the Examiner’s Supervisor (SPE), Kakali Chaki, may be reached at (571) 272-3719. Hand-delivered responses should be delivered to the Receptionist @ (Customer Service Window Randolph Building 401 Dulany Street, Alexandria, VA 22313), located on the first floor of the south side of the Randolph Building. Finally, information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Moreover, status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have any questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) toll-free @ 1-866-217-9197. /WILBERT L STARKS/ Primary Examiner, Art Unit 2122 WLS 18 AUG 2026