Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 1/30/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “obtaining a first correlation between a characteristic, and a withstand voltage, each of a plurality of second MOS transistors, the characteristic being measured under a condition that a contact resistance between the stage, at which said each second MOS transistor is placed, and an electrode of said each second MOS transistor, is equal to or lower than a predetermined rate of an on-resistance of said each second MOS transistor; measuring a withstand voltage of the first MOS transistor when the first MOS transistor is off; and outputting the characteristic of the first MOS transistor, using the first correlation and the measured withstand voltage of the first MOS transistor.” The meaning of the language “obtaining a first correlation between a characteristic, and a withstand voltage, each of a plurality of second MOS transistors” is not clear. It is not clear what is correlation. What type of relation is considered as correlation. It is not clear what is the correlation between characteristics and withstand voltage. It is not clear what is the characteristics and how the withstand voltage is calculated. Claim only recites, characteristics is measured under a condition that a contact resistance between the stage, at which said each second MOS transistor is placed, and an electrode of said each second MOS transistor, is equal to or lower than a predetermined rate of an on-resistance of said each second MOS transistor. It is not clear what is the contact resistance and how the contact resistance is calculated and what is the meaning of “equal to or lower than a predetermined rate of an on-resistance”. It is not clear what is “predetermined rate” means and what is the condition and how the condition is determined. Therefore, claim language is not clear. Claim does not recite any structure to determine those values. Claim only recites MOS transistor. Therefore, it is not clear how the correlation is obtained.
Again, claim recites “outputting the characteristic of the first MOS transistor, using the first correlation and the measured withstand voltage of the first MOS transistor”. However, it is not clear what is the first correlation and how the correlation is calculated and what structure is used to calculate the correlation. Therefore, the limitation is not clear.
For purposes of the present examination any relation between more than one MOS transistor is construed to mean the first correlation and any characteristics is construed to mean the characteristics being measured. Clarification is required so that the scope of the claim is clear.
Independent claim 8 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention, because of the same reason as stated above for independent claim 1.
Claims 2-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite by virtue of their dependence from claims 1.
Claim 2 recites, “wherein the plurality of second MOS transistors includes at least 30 second MOS transistors”. The limitation is not clear. It is not clear what, “30 second MOS transistors” means. Is it 30 MOS transistor or “30 second” any parameter of MOS transistor? Therefore, the claim language is not clear.
For purposes of the present examination 30 second MOS transistors is construed to mean 30 MOS transistors. Clarification is required so that the scope of the claim is clear.
Referring to claim 1, it appears that the claim has recited insufficient structure for performing the recited method of having "two states," namely, “obtaining a first correlation between a characteristic, and a withstand voltage, ….” and “measuring a withstand voltage of the first MOS transistor when the first MOS transistor is off; and outputting the characteristic of the first MOS transistor….”. Paragraphs 25 of the specification (PG PUB) and Figure 1 teaches the structure which is used to calculate all the obtaining and measuring steps, however, claim 1 only includes MOS Transistor. Consequently, the claim does not appear to recite the requisite structure for performing the claimed method. As such, the boundaries of the language are unclear because the claim does not provide a discernable boundary on what performs the method. The recited method does not follow from the structure recited in the claim, i.e., “obtaining a first correlation between a characteristic, and a withstand voltage, ….” and “measuring a withstand voltage of the first MOS transistor when the first MOS transistor is off; and outputting the characteristic of the first MOS transistor….”. therefore, it is unclear whether the method steps require some other structure or is simply a result of operating the MOS Transistor. Thus, one of ordinary skill would not be able to draw a clear boundary between what is and is not covered by the claim. See MPEP 2173.05(g).
Independent claim 8 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention, because of the same reason as stated above for independent claim 1.
Claims 2-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite by virtue of its dependence from claim 1.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-8 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Claim 1
Step
Analysis
1: Statutory Category?
Yes. The claim recites a method of measuring a characteristic of a semiconductor device and, therefore, is a method.
2A - Prong 1: Judicial Exception Recited?
Yes. The claim recites the limitations of obtaining a first correlation between a characteristic, and a withstand voltage; ….measuring a withstand voltage of the first MOS transistor when the first MOS transistor is off; and outputting the characteristic of the first MOS transistor….. The claim 1 as a whole are directed to a methods comprising abstract ideas involving mathematical algorithms/procedures/relationships/correlations which have been determined by the courts as being directed to abstract ideas. obtaining a first correlation between a characteristic, and a withstand voltage; ….measuring a withstand voltage of the first MOS transistor when the first MOS transistor is off; and outputting the characteristic of the first MOS transistor by using mathematical formula and by using an algorithm. obtaining a first correlation between a characteristic, and a withstand voltage, each of a plurality of second MOS transistors, the characteristic being measured under a condition that a contact resistance between the stage, at which said each second MOS transistor is placed, and an electrode of said each second MOS transistor, is equal to or lower than a predetermined rate of an on-resistance of said each second MOS transistor which are directed to of data gathering and measuring from the data gathering using formula or algorithm. Collecting, displaying, and manipulating data; collecting information, analyzing it; obtaining and comparing intangible data; organizing and manipulating information through mathematical correlations; comparing new and stored information using rules to identify options, organizing and storing information which have been identified by the courts as extra-solution activity or using the generic functions of a computer and/or software to perform well known functions of a circuit design all of which have been identified by the courts as abstract ideas and are modeled in some forms of mathematical algorithms/procedures/relationships/correlations as is well known in the art of computer-aided analysis.
The limitations of outputting the characteristics is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind or by looking at the screen of an oscilloscope or a spectrum analyzer. For example, language, “obtaining” some date and then input in the system in the context of this claim encompasses the user manually inputting the values in the model the values by a piece of pen and paper and then measuring (data gathering) and outputting.
Accordingly, the claim recites an abstract idea.
2A - Prong 2: Integrated into a Practical Application?
No. The claim does not include any additional element, individually or in view of the claim as a whole, that are sufficient to amount to significantly more than the judicial exception because the computer, memory and/or one or more processors are generic computer components known in the industry and the steps implemented by the method, computer-readable storage medium, and apparatus are directed to simply appending well- understood, routine and conventional activities previously known to the industry to the judicial exception (i.e., requiring no more than generic computer to perform generic functions including data gathering, collecting and comparing known information; collecting, displaying, and manipulating data; collecting information, analyzing it, and displaying certain results of the collection and analysis; obtaining and comparing intangible data; organizing and manipulating information through mathematical correlations; comparing new and stored information using rules to identify options, organizing and storing information; retrieving data from the data storage or outputting data to the storage or to the screen for user interactive input/output). Therefore, the claim is directed to the abstract idea.
2B: Claim provides an Inventive Concept?
No. As discussed with respect to Step 2A Prong Two, the additional elements in the claim amounts to no more than mere instructions to apply the exception using a mathematical formula.
The same analysis applies here in 2B, i.e., mere instructions to apply an exception using a generic computer component or pencil and paper cannot integrate a judicial exception into a practical application at Step 2A or provide an inventive concept in Step 2B. The claim is ineligible.
Claim 8
Step
Analysis
1: Statutory Category?
Yes. The claim recites a method of measuring a characteristic of a semiconductor device and, therefore, is a method.
2A - Prong 1: Judicial Exception Recited?
Yes. The claim recites the limitations of obtaining a first correlation between a characteristic, and a threshold voltage; ….measuring a threshold voltage of the first MOS transistor when the first MOS transistor is off; and outputting the characteristic of the first MOS transistor….. The claim 1 as a whole are directed to a methods comprising abstract ideas involving mathematical algorithms/procedures/relationships/correlations which have been determined by the courts as being directed to abstract ideas. obtaining a first correlation between a characteristic, and a threshold voltage; ….measuring a threshold voltage of the first MOS transistor when the first MOS transistor is off; and outputting the characteristic of the first MOS transistor by using mathematical formula and by using an algorithm. obtaining a first correlation between a characteristic, and a threshold voltage, each of a plurality of second MOS transistors, the characteristic being measured under a condition that a contact resistance between the stage, at which said each second MOS transistor is placed, and an electrode of said each second MOS transistor, is equal to or lower than a predetermined rate of an on-resistance of said each second MOS transistor which are directed to of data gathering and measuring from the data gathering using formula or algorithm. Collecting, displaying, and manipulating data; collecting information, analyzing it; obtaining and comparing intangible data; organizing and manipulating information through mathematical correlations; comparing new and stored information using rules to identify options, organizing and storing information which have been identified by the courts as extra-solution activity or using the generic functions of a computer and/or software to perform well known functions of a circuit design all of which have been identified by the courts as abstract ideas and are modeled in some forms of mathematical algorithms/procedures/relationships/correlations as is well known in the art of computer-aided analysis.
The limitations of outputting the characteristics is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind or by looking at the screen of an oscilloscope or a spectrum analyzer. For example, language, “obtaining” some date and then input in the system in the context of this claim encompasses the user manually inputting the values in the model the values by a piece of pen and paper and then measuring (data gathering) and outputting.
Accordingly, the claim recites an abstract idea.
2A - Prong 2: Integrated into a Practical Application?
No. The claim does not include any additional element, individually or in view of the claim as a whole, that are sufficient to amount to significantly more than the judicial exception because the computer, memory and/or one or more processors are generic computer components known in the industry and the steps implemented by the method, computer-readable storage medium, and apparatus are directed to simply appending well- understood, routine and conventional activities previously known to the industry to the judicial exception (i.e., requiring no more than generic computer to perform generic functions including data gathering, collecting and comparing known information; collecting, displaying, and manipulating data; collecting information, analyzing it, and displaying certain results of the collection and analysis; obtaining and comparing intangible data; organizing and manipulating information through mathematical correlations; comparing new and stored information using rules to identify options, organizing and storing information; retrieving data from the data storage or outputting data to the storage or to the screen for user interactive input/output). Therefore, the claim is directed to the abstract idea.
2B: Claim provides an Inventive Concept?
No. As discussed with respect to Step 2A Prong Two, the additional elements in the claim amounts to no more than mere instructions to apply the exception using a mathematical formula.
The same analysis applies here in 2B, i.e., mere instructions to apply an exception using a generic computer component or pencil and paper cannot integrate a judicial exception into a practical application at Step 2A or provide an inventive concept in Step 2B. The claim is ineligible.
Dependent claims 2-7 when analyzed as a whole are held to be patent ineligible under 35 U.S.C. 101 because the recited limitations, considered both individually and as an ordered combination with the claim as a whole, fail to establish to integrate the abstract idea into a practical application:
For example, claim 2 recites, “wherein the plurality of second MOS transistors includes at least 30 second MOS transistors” which is as insignificant data gathering information and therefore is an abstract idea. The claim, as a whole, does not integrate the abstract idea to be a practical application. The claim is not specific to any practical application. The claim is ineligible.
For example, claim 3 recites, “wherein the contact resistance is 1% or less of the on-resistance of said each second MOS transistor” which is as insignificant data gathering information and therefore is an abstract idea. The claim, as a whole, does not integrate the abstract idea to be a practical application. The claim is not specific to any practical application. The claim is ineligible.
For example, claim 4 recites, “wherein the characteristic of the first MOS transistor and the characteristic of each of the plurality of second MOS transistors are each a drain-source voltage when a predetermined current flows, while a predetermined voltage is being applied between a gate and a source of the first MOS transistor or said each second MOS transistor” which is the data gathering information and therefore is an abstract idea. The claim, as a whole, does not integrate the abstract idea to be a practical application. The claim is not specific to any practical application. The claim is ineligible.
For example, claim 5 recites, “classifying the first MOS transistor into one of a plurality of groups that are obtained by dividing a predetermined range of the characteristic thereof, based on the outputted characteristic of the first MOS transistor.” which is as insignificant data gathering information and therefore is an abstract idea. The claim, as a whole, does not integrate the abstract idea to be a practical application. The claim is not specific to any practical application. The claim is ineligible.
For example, claim 6 recites, “comprising the method of measuring the semiconductor device according to claim 5.” which is as insignificant data gathering information and therefore is an abstract idea. The claim, as a whole, does not integrate the abstract idea to be a practical application. The claim is not specific to any practical application. The claim is ineligible.
For example, claim 7 recites, “obtaining two first MOS transistors included in a predetermined group of a plurality of groups, each of the two first MOS transistors being classified into the predetermined group using the method of measuring the semiconductor device according to claim 5; and connecting the obtained two first MOS transistors in parallel with each other.” which is the calculating the values as the mathematical concept and can be done mentally or in a generic computer component and therefore is an abstract idea. The claim, as a whole, does not integrate the abstract idea to be a practical application. The claim is not specific to any practical application. Mere instructions to apply an exception using a generic computer component cannot integrate a judicial exception into a practical application at Step 2A or provide an inventive concept in Step 2B. The claim is ineligible.
As a reminder, the 2019 PEG defines the phrase “integration into a practical application” to require an additional element or a combination of additional elements in the claim to apply, rely on, or use the judicial exception in a manner that imposes a meaningful limit on the judicial exception, such that it is more than a drafting effort designed to monopolize the exception.
Below are some examples of limitations that are indicative of integration into a practical application: Limitations that are indicative of integration into a practical application:
Improvements to the functioning of a computer, or to any other technology or technical field - see MPEP 2106.05(a)
Applying or using a judicial exception to effect a particular treatment or prophylaxis for a disease or medical condition — see Vanda Memo
Applying the judicial exception with, or by use of, a particular machine - see MPEP 2106.05(b)
Effecting a transformation or reduction of a particular article to a different state or thing - see MPEP 2106.05(c)
Applying or using the judicial exception in some other meaningful way beyond generally linking the use of the judicial exception to a particular technological environment, such that the claim as a whole is more than a drafting effort designed to monopolize the exception - see MPEP 2106.05(e) and Vanda Memo.
Claims 2-7 depend either directly or indirectly from claim 1 and thus are also rejected under 101 for the same reasons.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 4-8 are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by OKAGAKI TAKESHI in the Patent Application Publication Number JP2008010466A (Publication date 2008-01-17).
Regarding claim 1, Takeshi teaches a method of measuring a characteristic of a semiconductor device that is a first metal-oxide-semiconductor (MOS) transistor using a stage (a semiconductor integrated circuit in which variation in MOS transistor characteristics can be evaluated quantitatively with high precision.; Abstract Line 1; The present invention relates to a semiconductor integrated circuit having a TEG (Test Element Group) capable of evaluating the characteristics of a MOS transistor; Paragraph [0001] Line 1-2), the method comprising:
obtaining a first correlation between a characteristic, and a withstand voltage, each of a plurality of second MOS transistors (there is provided a semiconductor integrated circuit comprising a plurality of MOS units each having a first conductivity type first MOS transistor and a second conductivity type second MOS transistor as measurement transistors; Paragraph [0010] Line 1-3),
the characteristic being measured under a condition that a contact resistance between the stage, at which said each second MOS transistor is placed (As described above, for the PMOS transistor PT in which the on-state drain current Idpon of the selection MOS unit UT1s flows, four-terminal measurement using the PMOS drain voltage monitor terminal DPM, the PMOS source voltage monitor terminal SPM, the PMOS drain terminal DP, and the PMOS source terminal SP. That is, the drain and source voltage measurement using the PMOS drain voltage monitor terminal DPM and the PMOS source voltage monitor terminal SPM and the measurement of the on-state drain current Idpon using the PMOS drain terminal DP and the NMOS drain terminal DN are performed. As a result of being completely independent, accurate measurement excluding the influence of wiring resistance and probe contact resistance is realized; Paragraph [0053] Line 1-8), and an electrode of said each second MOS transistor, is equal to or lower than a predetermined rate of an on-resistance of said each second MOS transistor (With the above setting, in the selection MOS unit UT1s shown in FIG. 9, a predetermined potential difference is set between the PMOS drain terminal DP and the PMOS source terminal SP, and the PMOS transistor PT is turned on, so that the PMOS transistor PT of the selection MOS unit UT1s. The on-state drain current Idpon flowing through can be measured from the PMOS drain terminal DP; Paragraph [0049] Line 1-4);
measuring a withstand voltage of the first MOS transistor when the first MOS transistor is off (In the semiconductor integrated circuit according to claim 1, when the characteristic of the first MOS transistor of the selection MOS unit is measured, the one MOS transistor is selected as the first MOS transistor, and the first and second MOS transistors are selected. The potential difference between the current measuring terminals is set to a potential difference such that a measurable current flows through the first MOS transistor, and the potential difference between the third and fourth current measuring terminals is set to substantially zero; Paragraph [0011] Line 1-5; On the other hand, the NMOS transistor Q5 receiving the output of the NAND gate G1 at the gate electrode is turned off. Further, the NMOS transistors Q1 to Q4 receiving the “H” signal at the gate electrode are turned on, and the PMOS source voltage monitor terminal SPM and the PMOS drain voltage monitor terminal DPM are electrically connected to the source and drain of the PMOS transistor PT, The NMOS drain voltage monitor terminal DNM and the NMOS source voltage monitor terminal SNM are electrically connected to the drain and source of the NMOS transistor NT. As a result, voltage measurement by these monitor terminals (SPM, DPM, SNM, DNM) becomes possible; Paragraph [0034] Line 1-11); and
outputting the characteristic of the first MOS transistor, using the first correlation and the measured withstand voltage of the first MOS transistor (FIG. 14 is an explanatory diagram showing N / PMOS correlation variation based on a comparison between an on (state drain) current (Ion−Nch) of an NMOS transistor and an on current (Ion−Pch) of a PMOS transistor. As shown in FIG. 13, the gate electrode discrete N / PMOS layout configuration as shown in FIG. 13 predicts the N / PMOS correlation variation 41, and the gate electrode shared N / PMOS as shown in FIG. In the PMOS layout configuration, the N / PMOS correlation variation 42 is predicted; Paragraph [0018] Line 1-5).
Regarding claim 4, Takeshi teaches a method of measuring the semiconductor device,
wherein the characteristic of the first MOS transistor and the characteristic of each of the plurality of second MOS transistors are each a drain-source voltage when a predetermined current flows, while a predetermined voltage is being applied between a gate and a source of the first MOS transistor or said each second MOS transistor (With the above setting, in the selection MOS unit UT1s shown in FIG. 9, a predetermined potential difference is set between the PMOS drain terminal DP and the PMOS source terminal SP, and the PMOS transistor PT is turned on, so that the PMOS transistor PT of the selection MOS unit UT1s. The on-state drain current Idpon flowing through can be measured from the PMOS drain terminal DP; Paragraph [0049] Line 1-4; On the other hand, in the non-selection MOS unit UT1d shown in FIG. 8, a predetermined potential difference is set between the NMOS drain terminal DN and the NMOS source terminal SN, but the potential applied to the gate application voltage terminal GOFF is the NMOS source. Since the gate-source voltage Vgs is “0” and falls below the threshold voltage and the NMOS transistor NT is turned off, the off-state drain current Idnoff is generated from the NMOS transistor NT of the unselected MOS unit UT1d. Will flow; Paragraph [0043] Line 1-5).
Regarding claim 5, Takeshi teaches a method of measuring the semiconductor device,
the method further comprising:
classifying the first MOS transistor into one of a plurality of groups that are obtained by dividing a predetermined range (first conductive type and second conductive type as the predetermined range) of the characteristic thereof, based on the outputted characteristic of the first MOS transistor (According to a first aspect of the present invention, there is provided a semiconductor integrated circuit comprising a plurality of MOS units each having a first conductivity type first MOS transistor and a second conductivity type second MOS transistor as measurement transistors. And first and second current measurement terminals electrically connected in common to one electrode and the other electrode of the first MOS transistor of the plurality of MOS units, and the second of the plurality of MOS units. Corresponding to the third and fourth current measuring terminals electrically connected in common to one electrode and the other electrode of the MOS transistor, and one electrode and the other electrode of the first MOS transistor of the plurality of MOS units First and second voltage measuring terminals provided in common, and one electrode and the other electrode of the second MOS transistor of the plurality of MOS units Correspondingly provided third and fourth voltage measurement terminals and MOS unit selection means for selecting one of the plurality of MOS units as a selection MOS unit, the plurality of MOS units, Each of the first and second MOS transistors is configured to share a gate electrode, and when corresponding to the selection MOS unit, one of the first and second MOS transistors is turned on and the other MOS transistor is turned on. A MOS transistor conduction controller that turns off one of the MOS transistors when the MOS transistor is turned off and corresponds to a non-selected MOS unit other than the selected MOS unit, and the first and The second voltage measuring terminal is connected to one electrode of the first MOS transistor and the other. Electrically connected to the electrode, and a third and a first electrode and a voltage measuring terminal connection control unit electrically connected to the other electrode of the fourth voltage measuring terminal and the second MOS transistor; Paragraph [0010] Line 1-18).
Regarding claim 6, Takeshi teaches a method of manufacturing a semiconductor device,
comprising the method of measuring the semiconductor device according to claim 5 ((Operation (PMOS)) FIGS. 9 and 10 are explanatory diagrams for explaining a measurement method for the PMOS transistor PT; Paragraph [0046] Line 1-2; The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a semiconductor integrated circuit having a TEG capable of accurately and quantitatively evaluating variations in MOS transistor characteristics; Paragraph [0009] Line 1-2; See the rejection of claim 5).
Regarding claim 7, Takeshi teaches a method of manufacturing a semiconductor module, comprising:
obtaining two first MOS transistors included in a predetermined group of a plurality of groups, each of the two first MOS transistors being classified into the predetermined group using the method of measuring the semiconductor device according to claim 5 (According to a first aspect of the present invention, there is provided a semiconductor integrated circuit comprising a plurality of MOS units each having a first conductivity type first MOS transistor and a second conductivity type second MOS transistor as measurement transistors. And first and second current measurement terminals electrically connected in common to one electrode and the other electrode of the first MOS transistor of the plurality of MOS units, and the second of the plurality of MOS units. Corresponding to the third and fourth current measuring terminals electrically connected in common to one electrode and the other electrode of the MOS transistor, and one electrode and the other electrode of the first MOS transistor of the plurality of MOS units First and second voltage measuring terminals provided in common, and one electrode and the other electrode of the second MOS transistor of the plurality of MOS units Correspondingly provided third and fourth voltage measurement terminals and MOS unit selection means for selecting one of the plurality of MOS units as a selection MOS unit, the plurality of MOS units, Each of the first and second MOS transistors is configured to share a gate electrode, and when corresponding to the selection MOS unit, one of the first and second MOS transistors is turned on and the other MOS transistor is turned on. A MOS transistor conduction controller that turns off one of the MOS transistors when the MOS transistor is turned off and corresponds to a non-selected MOS unit other than the selected MOS unit, and the first and The second voltage measuring terminal is connected to one electrode of the first MOS transistor and the other. Electrically connected to the electrode, and a third and a first electrode and a voltage measuring terminal connection control unit electrically connected to the other electrode of the fourth voltage measuring terminal and the second MOS transistor; Paragraph [0010] Line 1-18); and
connecting the obtained two first MOS transistors in parallel with each other (Figures 8-10 show the MOS transistors are connected in parallel).
Regarding claim 8, Takeshi teaches a method of measuring a characteristic of a semiconductor device that is a first metal-oxide-semiconductor (MOS) transistor using a stage (a semiconductor integrated circuit in which variation in MOS transistor characteristics can be evaluated quantitatively with high precision.; Abstract Line 1; The present invention relates to a semiconductor integrated circuit having a TEG (Test Element Group) capable of evaluating the characteristics of a MOS transistor; Paragraph [0001] Line 1-2), the method comprising:
obtaining a first correlation between a characteristic, and a threshold voltage, each of a plurality of second MOS transistors (there is provided a semiconductor integrated circuit comprising a plurality of MOS units each having a first conductivity type first MOS transistor and a second conductivity type second MOS transistor as measurement transistors; Paragraph [0010] Line 1-3 On the other hand, with the above setting, in the unselected MOS unit UT1d shown in FIG. 10, a predetermined potential difference is set between the PMOS drain terminal DP and the PMOS source terminal SP, and the gate-source voltage Vgs is “0” and the threshold voltage is set. Since the PMOS transistor PT is turned off, the off-state drain current Idpoff flows from the PMOS transistor PT of the unselected MOS unit UT1d; Paragraph [0051] Line 1-4),
the characteristic being measured under a condition that a contact resistance between the stage, at which said each second MOS transistor is placed (As described above, for the PMOS transistor PT in which the on-state drain current Idpon of the selection MOS unit UT1s flows, four-terminal measurement using the PMOS drain voltage monitor terminal DPM, the PMOS source voltage monitor terminal SPM, the PMOS drain terminal DP, and the PMOS source terminal SP. That is, the drain and source voltage measurement using the PMOS drain voltage monitor terminal DPM and the PMOS source voltage monitor terminal SPM and the measurement of the on-state drain current Idpon using the PMOS drain terminal DP and the NMOS drain terminal DN are performed. As a result of being completely independent, accurate measurement excluding the influence of wiring resistance and probe contact resistance is realized; Paragraph [0053] Line 1-8), and an electrode of said each second MOS transistor, is equal to or lower than a predetermined rate of an on-resistance of said each second MOS transistor (With the above setting, in the selection MOS unit UT1s shown in FIG. 9, a predetermined potential difference is set between the PMOS drain terminal DP and the PMOS source terminal SP, and the PMOS transistor PT is turned on, so that the PMOS transistor PT of the selection MOS unit UT1s. The on-state drain current Idpon flowing through can be measured from the PMOS drain terminal DP; Paragraph [0049] Line 1-4);
measuring a threshold voltage of the first MOS transistor (In the semiconductor integrated circuit according to claim 1, when the characteristic of the first MOS transistor of the selection MOS unit is measured, the one MOS transistor is selected as the first MOS transistor, and the first and second MOS transistors are selected. The potential difference between the current measuring terminals is set to a potential difference such that a measurable current flows through the first MOS transistor, and the potential difference between the third and fourth current measuring terminals is set to substantially zero; Paragraph [0011] Line 1-5; On the other hand, the NMOS transistor Q5 receiving the output of the NAND gate G1 at the gate electrode is turned off. Further, the NMOS transistors Q1 to Q4 receiving the “H” signal at the gate electrode are turned on, and the PMOS source voltage monitor terminal SPM and the PMOS drain voltage monitor terminal DPM are electrically connected to the source and drain of the PMOS transistor PT, The NMOS drain voltage monitor terminal DNM and the NMOS source voltage monitor terminal SNM are electrically connected to the drain and source of the NMOS transistor NT. As a result, voltage measurement by these monitor terminals (SPM, DPM, SNM, DNM) becomes possible; Paragraph [0034] Line 1-11 As described above, the MOS unit UT2 of the second embodiment includes the switching gates for connecting the voltage monitor terminals (SPM, DPM, SNM, DNM) and the gate applied voltage terminal (GOFF) with the transmission gates TG1 to TG5. Thus, by minimizing the influence by increasing the threshold voltage of each N / PMOS transistor, more accurate measurement can be realized; Paragraph [0063] Line 1-4); and
outputting the characteristic of the first MOS transistor, using the first correlation and the measured threshold voltage of the first MOS transistor (FIG. 14 is an explanatory diagram showing N / PMOS correlation variation based on a comparison between an on (state drain) current (Ion−Nch) of an NMOS transistor and an on current (Ion−Pch) of a PMOS transistor. As shown in FIG. 13, the gate electrode discrete N / PMOS layout configuration as shown in FIG. 13 predicts the N / PMOS correlation variation 41, and the gate electrode shared N / PMOS as shown in FIG. In the PMOS layout configuration, the N / PMOS correlation variation 42 is predicted; Paragraph [0018] Line 1-5).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over OKAGAKI TAKESHI in the Patent Application Publication Number JP2008010466A (Publication date 2008-01-17).
Regarding claim 2, Takeshi teaches a method of measuring the semiconductor device,
wherein the plurality of second MOS transistors includes at least 30 second MOS transistors (According to a first aspect of the present invention, there is provided a semiconductor integrated circuit comprising a plurality of MOS units; Paragraph [0010] Line 1-2; plurality of MOS can be 30 MOS transistors).
Takeshi discloses the claimed invention (plurality of MOS transistor) except for 30 second MOS transistors. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have 30 MOS transistors, since it has been held that discovering an optimum value of a result effective variable involves only routine Skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 3, Takeshi teaches a method of measuring the semiconductor device,
wherein the contact resistance is 1% or less of the on-resistance of said each second MOS transistor (For example, when a voltage of half the power supply voltage (Vcc / 2) is input to one electrode of the transmission gates TG1 to TG5, the NMOS gate increases as the potential of the other electrode approaches (Vcc / 2) from “0”. The threshold voltage increases. However, at the same time, the PMOS gate also has a slightly increased threshold voltage, but it is desired to be in an on state. Therefore, the resistance is lowered compared to the configuration in which the NMOS transistor is switched alone, and the influence of the increased threshold voltage can be sufficiently reduced; Paragraph [0062] Line 5-10).
Takeshi discloses the claimed invention (less contact resistance) except for the contact resistance is 1% or less of the on-resistance. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have the contact resistance is 1% or less of the on-resistance, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Kim (US 20090140763 A1) discloses, “METHOD OF MEASURING ON-RESISTANCE IN BACKSIDE DRAIN WAFER-[0007] Embodiments relate to a method of measuring on-resistance in a backside drain wafer by which a precise on-resistance can be measured without using a chuck. [0015] Example FIG. 4 is a cross-sectional diagram of a first MOS transistor (Die 1) for explaining a method of measuring an on-resistance in a backside drain wafer and example FIG. 5 is a diagram of an equivalent circuit shown in example FIG. 4. Referring to example FIGS. 4 and 5, in a structure including a first MOS transistor having lightly doped n-type epitaxial layer 2 formed on and/or over heavily doped n-type substrate 1. P-type channel layer 3 is formed on and/or over epitaxial layer 2 and gate 4 embedded in channel layer 3 and partially in epitaxial layer 2. Source 5 is formed on and/or over gate 4 and drain 6 formed at a bottom region or backside of substrate 1. Second MOS transistor (Die 2) is provided adjacent to first MOS transistor (Die 1). Second MOS transistor (Die 2) has lightly doped n-type epitaxial layer 2' formed on and/or over a heavily doped n-type substrate 1'. P-type channel layer 3' is formed on and/or over epitaxial layer 2' and gate 4' embedded in channel layer 3' and partially in epitaxial layer 2'. Source 5' is formed on and/or over gate 4' and drain 6 formed at a bottom region or backside of substrate 1'. [0016] On-resistance is measured by altering a current path using the fact that drain 6 is shared by first MOS transistor (Die 1) and second MOS transistor (Die 2) on backsides thereof. In particular, when the first MOS transistor (Die 1) and second MOS transistor (Die 2) are turned on by applying power to gates 4 and 4' thereof, respectively, a current path is formed that flows to drain 6 via source 5, channel layer 3, epitaxial layer 2 and substrate 1 of first MOS transistor (Die 1) and then flows to substrate 1', epitaxial layer 2', channel layer 3' and source 5' of second MOS transistor (Die 2). By applying a test voltage to gate 4 of first MOS transistor (Die 1) and applying a voltage over a full turn-on voltage to gate 4' of second MOS transistor (Die 2), gate 4' is forced into a floating mode-However Kim does not disclose obtaining a first correlation between a characteristic, and a withstand voltage, each of a plurality of second MOS transistors, the characteristic being measured under a condition that a contact resistance between the stage, at which said each second MOS transistor is placed, and an electrode of said each second MOS transistor, is equal to or lower than a predetermined rate of an on-resistance of said each second MOS transistor; measuring a withstand voltage of the first MOS transistor when the first MOS transistor is off.”
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/NASIMA MONSUR/Primary Examiner, Art Unit 2858
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