DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 10-11, 14-16 and 18-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang et al. (USPN 11,133,039).
With respect to claim 1, Yang et al. discloses, in Fig. 2 and 4, Power multiplexer circuitry (Fig. 1 further details disclosed in Fig. 4) comprising:
interface control logic (118 with 312) comprising:
first SR latch circuitry (118 is a latch having set and reset terminals, see Col. 4 lines 35-39. Thus 118 is an SR latch) to generate first (one of 130 and 128) and second (other one of 130 and 128) interface control signals responsive to first (one of SEL_VMAX2 and the output of 136) and second (other one of SEL_VMAX2 and the output of 136) latch control signals;
a PMUX control circuit (112 with 114, 138, 140, 142, 144, 1446, 152, 154, 156, 158 and 160) to provide a first selection control signal responsive to the first interface control signal (one of 162 and 148) and to provide a second selection control signal responsive to the second interface control signal (other one of 162 and 148);
a power output circuit (164 and 150) to output a selected voltage (VDD_SRAM) at a PMUX output (189), the power output circuit comprising:
first switch circuitry (one of 164 and 150) arranged between a first voltage rail (one of VDD and VDDM) and the PMUX output to provide an electrical path therebetween (189) responsive to the first selection control signal (one of 162 and 148);
second switch circuitry (other one of 164 and 150) arranged between a second voltage rail (other one of VDD and VDDM) and the PMUX output to provide an electrical path therebetween (189) responsive to the second selection control signal (other one of 162 and 148).
With respect to claim 10, the circuitry of claim 1, where the PMUX control circuit comprises:
a first logic gate (one of 152 and 158) to provide the first selection control signal (via one of 156, 158 with 160 and 140, 142, 144 with 146) responsive to the first latch control signal (one of 130 and 128) and an enable signal (SD_VMAX2, note SDB_VMAX is generated according to SD_VMAX); and
a second logic gate (other one of 152 and 158) to provide the second selection control signal (via the other one of 156, 158 with 160 and 140, 142, 144 with 146) responsive to the second latch control signal (other one of 130 and 128) and the enable signal (SD_VMAX2, note SDB_VMAX is generated according to SD_VMAX).
With respect to claim 11, the circuitry of claim 10, where the PMUX control circuit comprises a level shifter (112) to level shift an external signal (SD) to provide the enable signal (SDB_VMAX2) at a voltage level of the selected voltage (when VMAX2 is equal to VDDM and VDDM is the selected voltage, the circuit operates as claimed, see Col. 3 lines 57-59).
With respect to claim 14, the circuitry of claim 1, where the circuitry is integrated in the storage System (SRAM storage/memory system, see Col. 2 lines 40-52).
With respect to claim 15, the circuitry of claim 1, where the first voltage rail is electrically isolated from the second voltage rail (VDD and VDDM are electrically isolated due to the physical distance/separation between the rails as well as to avoid VDDM being shorted to VDD and vice versa, note physical separation constitutes “electrical isolation” according to Applicant, e.g., see claim 9 of the instant application).
With respect to claim 16, the circuitry of claim 1, where first switch circuitry comprises a first select transistor arranged between the first voltage rail and the PMUX output to provide the electrical path therebetween and where the second switch circuitry comprises a second select transistor arranged between the second voltage rail and the PMUX output to provide the electrical path therebetween (both 164 and 150 are PMOS transistors, thus the circuit is connected and operative as claimed).
With respect to claim 18, Yang et al. discloses, a system (Fig. 1 further details disclosed in Figs. 2 and 4) comprising power multiplexer circuitry (186 with 100/185 of Fig. 1, details disclosed in Figs. 2 and 4) comprising:
interface control logic (118 with 312) comprising:
SR latch circuitry (118 is a latch having set and reset terminals, see Col. 4 lines 35-39. Thus 118 is an SR latch) to generate first (one of 130 and 128) and second (other one of 130 and 128) interface control signals responsive to first (one of SEL_VMAX2 and the output of 136) and second (other one of SEL_VMAX2 and the output of 136) latch control signals;
a PMUX control circuit (138, 140, 142, 144, 1446, 152, 154, 156, 158 and 160) to provide a first selection control signal responsive to the first interface control signal (one of 162 and 148) and to provide a second selection control signal responsive to the second interface control signal (other one of 162 and 148);
a power output circuit (164 and 150) to output a selected voltage (VDD_SRAM) at a PMUX output (189), the power output circuit comprising:
first switch circuitry (one of 164 and 150) arranged between a first voltage rail (one of VDD and VDDM) and the PMUX output to provide an electrical path therebetween (189) responsive to the first selection control signal (one of 162 and 148);
second switch circuitry (other one of 164 and 150) arranged between a second voltage rail (other one of VDD and VDDM) and the PMUX output to provide an electrical path therebetween (189) responsive to the second selection control signal (other one of 162 and 148).
With respect to claim 19, the system of claim 18 comprising a storage system, the storage system comprising cell circuitry arranged in electrical communication with the PMUX output (SRAM storage cell of 183/182 and 181 in communication with 185 of Fig. 1).
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Englekirk et al. (USPAPN 2023/0318598)
With respect to claim 1, Englekirk et al. discloses, in Figs. 2 and 4-5, Power multiplexer circuitry (Fig. 2 further details disclosed in Figs. 4-5) comprising:
interface control logic (208, 210 and 206) comprising:
first SR latch circuitry (206) to generate first (one of BFIRST and AFIRST) and second (other one of BFIRST and AFIRST) interface control signals responsive to first (one of the outputs of 208 and 210) and second (other one of the outputs of 208 and 210) latch control signals;
a PMUX control circuit (212 and 216) to provide a first selection control signal responsive to the first interface control signal (one of ACAP and ACAP bar) and to provide a second selection control signal responsive to the second interface control signal (other one of ACAP and ACAP bar);
a power output circuit (214) to output a selected voltage (VDD_INT voltage) at a PMUX output (VDD_INT output node), the power output circuit comprising:
first switch circuitry (one of MP3 and MP4) arranged between a first voltage rail and the PMUX output to provide an electrical path therebetween responsive (one of BFILTERED and AFILTERED) to the first selection control signal (one of ACAP and ACAP bar);
second switch circuitry (other one of MP3 and MP4) arranged between a second voltage rail and the PMUX output to provide an electrical path therebetween (other one of BFILTERED and AFILTERED) responsive to the second selection control signal (other one of ACAP and ACAP bar).
With respect to claim 10, the circuitry of claim 1, where the PMUX control circuit (details of 212 disclosed in Fig. 5, see also Fig. 4) comprises:
a first logic gate (one of the inverters, i.e., not gates, of M17 with M18 and M15 with M16) to provide the first selection control signal (one of ACAP and ACAP bar) responsive to the first latch control signal (one of AFIRST and BFIRST) and an enable signal (PORB, note PORB controls the output of 206 via 208 and 210, see also Fig. 4, and the output of 206 controls 212 via the control of AFIRST and BFIRST. Thus, since AFIRST and BFIRST are responsive to the PORB signal and the output 212 is responsive to AFIRST and BFIRST. Then the output, i.e., the above inverters, are responsive to PORB); and
a second logic gate (other one of the inverters of M17 with M18 and M15 with M16) to provide the second selection control signal (other one of ACAP and ACAP bar) responsive to the second latch control signal (other one of AFIRST and BFIRST) and the enable signal (PORB for the reasons discussed above).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (USPN 11,133,039) in view of Chan et al. (USPN 12,562,741)
Yang et al. discloses that the level shifter 112 generates the enable signal. Yang et al. fails to disclose the details of the level shifter of 112. Thus, Yang et al. fails to explicitly disclose, “where the PMUX control circuit comprises second SR latch circuitry to provide the enable signal”
However, Chan et al. discloses, in Fig. 2, a specific level shifter circuit (Fig. 2) that comprises an SR latch (230) to provide the enable signal (i.e., by controlling 240 such that the level shifter input of one of OUT and OUT bar, e.g., signal equivalent to the output of 112 of Yang et al.).
The level shifter of Chan et al. is a high speed level shifter that has low distortion (see Col. 3 lines 19-20).
It would have been obvious to replace the generic level shifter of 112 of Yang et al. with the level shifter of Fig. 2 of Chan et al. for the purpose of having a level shifter that operates at high speeds with low distortion.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Englekirk et al. (USPAPN 2023/0318598) in view of Kou et al. (USPN 10,281,502).
With respect to claim 13, Englekirk et al. discloses, that 212 and 216 receive/powered by the selected voltage at the VDD_INT output terminal. Englekirk et al. fails to disclose a clamp circuit connected to the VDD_INT output terminal. Thus, Englekirk et al. fails to disclose “where the PMUX control circuit comprises clamp circuitry, where the output of the clamp circuitry is to supply the PMUX control circuit and power output circuit with the selected voltage”.
However, it is old and well-known to connect a clamp circuit to the output of a power mux/selector. Thus, is further evidenced in Fig. 2 of Kuo et al. which discloses a power MUX/selector (M1 with M2) that selects one of VDD and VDDM similar to that of the power MUX/selector of Englekirk et al. The circuit Kuo et al. further includes clamp circuitry (214 with 216), where the output of the clamp circuitry is to supply the selective voltage output terminal (VOUT) and power output circuit (M1 with M2) with the selected voltage (one of VDD and VDDM via 214 and 216). The clamp circuit of 214 and 216 ensures that the output terminal of the selector never falls below the selected one of VDD and VDDM minus the forward voltages of the diodes 214 and 216 (see Col. 4 line 64 to Col. 5 line 5).
It would have been obvious to add the clamp circuit of 214 with 216 of Kou et al. between AFILTERED and BFILTED and the output node VDD_INT of Englekirk et al. for the purpose of ensuring the output of the voltage selector never falls below the one of the selected voltage levels minus the respective forward voltages of 214 and 216.
As combined above the clamp circuit of Kou et al. will be connected to the PMUX control circuit of Englekirk et al.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (USPN 11,133,039) in view of Umeyama (USPN 9,252,750).
With respect to claim 17, the circuitry of claim 16, that both the first and second switch circuitries (one of 164 and 150 and the other one of 164 and 150) are controlled responsive to the first latch control signal (SEL_VMAX when SEL_VMAX is interested as the first latch control signal), since SEL_VMAX directly controls node 120 of 1180 and SEL_VMAX controls the node of 122 of 118 via 136. Thus, SEL_VMAX controls both the first and second switch circuitry of Yang et al. However, Yang et al. fails to disclose two serially connected/stacked transistors in the second branch of the other one of 164 and 150.
Thus, Yang et al. fails to disclose “where the second switch circuitry comprises a third select transistor arranged in series with the second select transistor between the second voltage rail and the PMUX output to provide the electrical path therebetween, where the third select transistor is controllable responsive to the first latch control signal”.
However, it is old and well-known to add an additional serially connected/stacked transistor to both the first and second switch circuitries of a voltage selector/power MUX. This is further evidenced in Figs. 2 and 3 of Umeyama which discloses, in Fig. 3, adding additional transistors (i.e., M3b2 and M3m2) in each branch (VB to VOUT branch and VM to VOUT branch) of a voltage selector (130) that are serially connected/stacked to/with a single transistor (M3b1 and M3m1, see Fig. 2 which only includes one transistor) of the voltage selector for the purpose of preventing reverse current flow (i.e., back flow) within the voltage selector branches (see Col. 13 line 43 to Col. 14 line 3).
It would have been obvious to add the additional transistors M3b2 and M3m2 of Umeyama to the voltage selection transistors of one of 164 and 150 of Yang et al. for the purpose of preventing reverse current flow in the voltage switch of Yang et al.
As combined the second switch circuitry comprises a third select transistor arranged in series with the second select transistor between the second voltage rail and the PMUX output to provide the electrical path therebetween (the added one of M3b2 and M3m2 of Umeyama to Yang et al.), where the third select transistor is controllable responsive to the first latch control signal (as discussed above both branches of Yang et al. are, at least in part, controlled by the first control signal SEL_VMAX and thus the circuit is controlled as claimed).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (USPN 11,133,039) in view of So (USPN 6,025,746)
With respect to claim 20, Yang et al. merely discloses a generic internal power supply terminal VDD_SRAM for a SRAM device. Yang et al. fails to explicitly disclose “an electrical discharge clamp on an electrical path between the PMUX output and the cell circuitry”. However, it is old and well-known to connect ESD clamps to on the electrical paths of the external and internal power supply nodes of an SRAM device for the purpose of clamping/preventing ESD damage to the internal devices (i.e., SRAM). This is further evidenced in Fig. 6 and the ABSTRACT (see SRAM) and Col. 6 lines 18-41 (see ESD clamping/protection of the internal/external power supplies of Fig. 6) of So.
It would have been obvious to add the ESD clamping/protection circuitry of Fig. 6 of So to the external and internal power supply terminals of Yang et al. for the purpose of preventing damage caused by ESD to the SRAM circuitry of Yang et al.
Allowable Subject Matter
Claims 2-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/THOMAS J. HILTUNEN/Primary Examiner, Art Unit 2836
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