DETAILED ACTION
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 10 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 10,693,490). Chen (Fig. 1) discloses an apparatus (100) comprising:
an analog to digital converter (ADC) (120) having an output;
decimation filter circuitry (130) having an input and an output, the input of the decimation filter circuitry (130) coupled to the output (DOUT) of the ADC (120);
multiplexer circuitry (MUX/DEMUX 140) having an input, a first output, and a second output, the input of the multiplexer circuitry coupled to the output of the decimation filter circuitry (130);
first filter (1st sub-HPF) circuitry having an input coupled to the first output of the multiplexer circuitry; and
second filter circuitry (2nd sub-HPF) having an input coupled to the second output of the multiplexer circuitry (col. 1, lines 54-67).
Allowable Subject Matter
Claims 1-9 and 17-20 are allowed.
Claim 11-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claims 1-9, the prior art of record, when taken alone or in combination, cannot be construed as reasonably teaching or suggesting all of the elements of the claimed invention as arranged or provided in the manner as claimed by the applicant. Added for emphasis, the claim recitation “first delay circuitry [240] having an input and an output, the input of the first delay circuitry coupled to the first output of the multiplexer circuitry [230]; first filter circuitry [255] having an input coupled to the output of the first delay circuitry; second delay circuitry [245] having an input and an output, the input of the second delay circuitry coupled to the second output of the multiplexer circuitry [230]; and second filter circuitry [260] having an input coupled to the output of the second delay circuitry” is not found in the prior art of record. Therefore, the claims are allowed.
Regarding claims 17-20, the prior art of record, when taken alone or in combination, cannot be construed as reasonably teaching or suggesting all of the elements of the claimed invention as arranged or provided in the manner as claimed by the applicant. Added for emphasis, the claim recitation “first delay circuitry having an input and an output, the input of the first delay circuitry coupled to the first output of the multiplexer circuitry, the first delay circuitry configured to delay signals by a filter delay, the filter delay based on a number of filter circuitry, a notch frequency, and an oversampling rate; second delay circuitry having an input and an output, the input of the second delay circuitry coupled to the second output of the multiplexer circuitry, the second delay circuitry configured to delay signals by the filter delay; first filter circuitry having an input coupled to the output of the first delay circuitry; and second filter circuitry having an input coupled to the output of the second delay circuitry” is not found in the prior art of record. Therefore, the claims are allowed.
Regarding claim 11, the prior art of record, when taken alone or in combination, cannot be construed as reasonably teaching or suggesting all of the elements of the claimed invention as arranged or provided in the manner as claimed by the applicant. Added for emphasis, the claim recitation “first delay circuitry having an input and an output, the input of the first delay circuitry coupled to the first output of the multiplexer circuitry, the output of the first delay circuitry coupled to the input of the first filter circuitry; and second delay circuitry having an input and an output, the input of the second delay circuitry coupled to the second output of the multiplexer circuitry, the output of the second delay circuitry coupled to the input of the second filter circuitry” is not found in the prior art of record.
Regarding claims 12-13, the prior art of record, when taken alone or in combination, cannot be construed as reasonably teaching or suggesting all of the elements of the claimed invention as arranged or provided in the manner as claimed by the applicant. Added for emphasis, the claim recitation “the first filter circuitry includes: settling circuitry having an input and an output, the input of the settling circuitry coupled to the first output of the multiplexer circuitry; and averaging circuitry having an input coupled to the output of the settling circuitry” is not found in the prior art of record.
Regarding claim 14, the prior art of record, when taken alone or in combination, cannot be construed as reasonably teaching or suggesting all of the elements of the claimed invention as arranged or provided in the manner as claimed by the applicant. Added for emphasis, the claim recitation “offset calibration circuitry having an input and an output, the input of the offset calibration circuitry coupled to the output of the decimation filter circuitry; gain calibration circuitry having an input and an output, the input of the gain calibration circuitry coupled to the output of the offset calibration circuitry; and clipping circuitry having an input and an output, the input of the clipping circuitry coupled to the output of the gain calibration circuitry, the output of the clipping circuitry coupled to the input of the multiplexer circuitry” is not found in the prior art of record.
Regarding claim 15, the prior art of record, when taken alone or in combination, cannot be construed as reasonably teaching or suggesting all of the elements of the claimed invention as arranged or provided in the manner as claimed by the applicant. Added for emphasis, the claim recitation “wherein the decimation filter circuitry further has a control input, the multiplexer circuitry further has a control input, and the apparatus further comprising: oversampling ratio (OSR) circuitry having an output coupled to the control input of the decimation filter circuitry; and channel control circuitry having an output coupled to the control input of the multiplexer circuitry” is not found in the prior art of record.
Regarding claim 16, the prior art of record, when taken alone or in combination, cannot be construed as reasonably teaching or suggesting all of the elements of the claimed invention as arranged or provided in the manner as claimed by the applicant. Added for emphasis, the claim recitation “the ADC further has an input, the multiplexer circuitry is first multiplexer circuitry, the first filter circuitry further has an output, the second filter circuitry further has an output, and the apparatus further comprising: second multiplexer circuitry having a control input and an output, the output of the second multiplexer circuitry coupled to the input of the ADC; and buffer circuitry having a first input, a second input, and an output, the first input of the buffer circuitry coupled to the output of the first filter circuitry, the second input of the buffer circuitry coupled to the output of the second filter circuitry, the output of the buffer circuitry coupled to the control input of the second multiplexer circuitry” is not found in the prior art of record.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAI M NGUYEN whose telephone number is (571)272-1809. The examiner can normally be reached Mon-Fri: 8:00 am - 4:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dameon E. Levi can be reached at 571-272-2105. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAI M NGUYEN/Primary Examiner, Art Unit 2845
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