Ation DETAILED ACTION
Claims 1-20 are present for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/05/2025 is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 5, 7-9, 12, 14-16 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Roberts et al. (US2016/0378668) in view of Lee et al. (US2023/0359379).
With respect claim 1, Roberts et al. teaches a plurality of memory devices (see Fig. 1 and paragraphs 17 and 19; memory modules); and
a processing device, operatively coupled with the plurality of memory devices (see Fig. 1 and paragraph 16; processor core 102 coupled to memory devices through controller), to perform operations comprising:
receiving a request to perform a memory access operation at a first memory region of a first memory device of the plurality of memory devices (see paragraph 36; memory module 110 receives a memory access request targeting the memory location);
identifying, based on an operation type of the memory access operation, one or more corresponding actions associated with the metadata region (see paragraph 35; an access metadata rule for a memory location (e.g., a row of the storage array 116), indicating how the access metadata for the memory location is to be modified in response to a memory access request. Also in claim 1; in response to the first memory access request, adjusting, at the memory module, first access metadata indicating a pattern of accesses to the first location of the memory module);
causing the memory access operation to be performed on a first plurality of memory cells at the first memory device (see paragraphs 35-36; memory module 110 receives a memory access request targeting the memory location. In response, at block 408 the memory module 110 executes the memory access request by, for example, writing data to or reading data from the data payload fields of the memory location); and
responsive to causing the memory access operation to be performed, causing at least one of the one or more corresponding actions to be performed on a second plurality of memory cells corresponding to the metadata region (see paragraph 33; in response to receiving the memory access request 350, the ADM 115 modifies the access metadata at the memory location indicated by the metadata pointer field 352. Also in paragraphs 35-37; ADM 115 initiates modification of the access metadata at the memory location by executing a low priority read of the access metadata fields at the memory location).
Roberts et al. does not teach determining, based on a data structure referencing a namespace accessible to a host system and to the plurality of memory devices, a mapping between an identifier of the first memory region and an identifier of a metadata region associated with the first memory region.
However, Lee et al. teaches CXL memory controller 621 may include a storage manager, a mapping table manager, an address mapper, and a metadata buffer (see paragraph 183)… wherein mapping table manager may generate the map data by allocating the map data to the buffer memory BFM. The mapping table manager may modify the map data by changing the map data allocated to the buffer memory BFM. The mapping table manager may delete the map data by deallocating the map data allocated to the buffer memory BFM (see paragraph 185-187).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Roberts et al. to include the above mentioned to efficiently use the memory (see Lee, paragraph 194).
With respect claim 2, Roberts et al. does not teach wherein each of the plurality of memory devices is a dynamic capacity device connected to the host system via a respective plurality of Compute Express Link (CXL) links.
However, Lee et al. teaches wherein each of the plurality of memory devices is a dynamic capacity device connected to the host system via a respective plurality of Compute Express Link (CXL) links (see paragraph 143; host 201 may be directly connected with the plurality of memory devices 202a and 202b. The host 201, the CXL storage 210, and the plurality of CXL memories 220_1 to 220_n may be connected with the CXL switch SW_CXL and may communicate with each other through the CXL switch).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Roberts et al. to include the above mentioned to efficiently use the memory (see Lee, paragraph 194).
With respect claim 5, Roberts et al. teaches wherein the one or more actions associated with the metadata region comprise at least one of: (i) a move operation to move metadata of the metadata region from a first physical location to a second physical location, (ii) a copy operation to copy at least a portion of the metadata of the metadata region, (iii) a reset operation to reset at least the portion of the metadata of the metadata region, (iv) a clone operation to duplicate at least the portion of the metadata of the metadata region, or (v) a computation operation to perform a computation operation to at least the portion of the metadata of the metadata region (see paragraph 28 and 32; the FN field 242 can indicate a given metadata value is to be incremented on read and write accesses, and is to be decremented on reset operations).
With respect claim 7, Roberts et al. does not teach wherein the system further comprises a fabric management component, wherein the fabric management component comprises firmware embedded within a baseboard management controller, and wherein the fabric management component associated with the one or more of the plurality of memory devices creates, via an application programming interface, an entry of the data structure, wherein the entry comprises the mapping between the identifier of the first memory region and the identifier of the metadata region associated with the first memory region.
However, Lee et al. teaches the CXL switch SW_CXL may be connected with an external network or Fabric and may be configured to communicate with an external server through the external network or Fabric (see paragraph 161). Lee et al. also teaches wherein CXL memory controller 621 may include a storage manager, a mapping table manager, an address mapper, and a metadata buffer (see paragraph 183)… wherein mapping table manager may generate the map data by allocating the map data to the buffer memory BFM. The mapping table manager may modify the map data by changing the map data allocated to the buffer memory BFM. The mapping table manager may delete the map data by deallocating the map data allocated to the buffer memory BFM (see paragraph 185-187).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Roberts et al. to include the above mentioned to efficiently use the memory (see Lee, paragraph 194).
With respect claim 8, Roberts et al. teaches a non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device (see paragraph 48; computer readable medium), cause the processing device to perform operations comprising:
receiving a request to perform a memory access operation at a first memory region of a first memory device of a plurality of memory devices (see paragraph 36; memory module 110 receives a memory access request targeting the memory location);
identifying, based on an operation type of the memory access operation, one or more corresponding actions associated with the metadata region (see paragraph 35; an access metadata rule for a memory location (e.g., a row of the storage array 116), indicating how the access metadata for the memory location is to be modified in response to a memory access request. Also in claim 1; in response to the first memory access request, adjusting, at the memory module, first access metadata indicating a pattern of accesses to the first location of the memory module);
causing the memory access operation to be performed on a first plurality of memory cells at the first memory device (see paragraphs 35-36; memory module 110 receives a memory access request targeting the memory location. In response, at block 408 the memory module 110 executes the memory access request by, for example, writing data to or reading data from the data payload fields of the memory location); and
responsive to causing the memory access operation to be performed, causing at least one of the one or more corresponding actions to be performed on a second plurality of memory cells corresponding to the metadata region (see paragraph 33; in response to receiving the memory access request 350, the ADM 115 modifies the access metadata at the memory location indicated by the metadata pointer field 352. Also in paragraphs 35-37; ADM 115 initiates modification of the access metadata at the memory location by executing a low priority read of the access metadata fields at the memory location).
Roberts et al. does not teach determining, based on a data structure referencing a namespace accessible to a host system and to the plurality of memory devices, a mapping between an identifier of the first memory region and an identifier of a metadata region associated with the first memory region.
However, Lee et al. teaches CXL memory controller 621 may include a storage manager, a mapping table manager, an address mapper, and a metadata buffer (see paragraph 183)… wherein mapping table manager may generate the map data by allocating the map data to the buffer memory BFM. The mapping table manager may modify the map data by changing the map data allocated to the buffer memory BFM. The mapping table manager may delete the map data by deallocating the map data allocated to the buffer memory BFM (see paragraph 185-187).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the medium taught by Roberts et al. to include the above mentioned to efficiently use the memory (see Lee, paragraph 194).
With respect claim 9, Roberts et al. does not teach wherein each of the plurality of memory devices is a dynamic capacity device connected to the host system via a respective plurality of Compute Express Link (CXL) links.
However, Lee et al. teaches wherein each of the plurality of memory devices is a dynamic capacity device connected to the host system via a respective plurality of Compute Express Link (CXL) links (see paragraph 143; host 201 may be directly connected with the plurality of memory devices 202a and 202b. The host 201, the CXL storage 210, and the plurality of CXL memories 220_1 to 220_n may be connected with the CXL switch SW_CXL and may communicate with each other through the CXL switch).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the medium taught by Roberts et al. to include the above mentioned to efficiently use the memory (see Lee, paragraph 194).
With respect claim 12, Roberts et al. teaches wherein the one or more actions associated with the metadata region comprise at least one of: (i) a move operation to move metadata of the metadata region from a first physical location to a second physical location, (ii) a copy operation to copy at least a portion of the metadata of the metadata region, (iii) a reset operation to reset at least the portion of the metadata of the metadata region, (iv) a clone operation to duplicate at least the portion of the metadata of the metadata region, or (v) a computation operation to perform a computation operation to at least the portion of the metadata of the metadata region (see paragraph 28 and 32; the FN field 242 can indicate a given metadata value is to be incremented on read and write accesses, and is to be decremented on reset operations).
With respect claim 14, Roberts et al. does not teach wherein a fabric management component associated with the one or more of the pluralities of memory devices creates, via an application programming interface, an entry of the data structure, wherein the entry comprises the mapping between the identifier of the first memory region and the identifier of the metadata region associated with the first memory region.
However, Lee et al. teaches the CXL switch SW_CXL may be connected with an external network or Fabric and may be configured to communicate with an external server through the external network or Fabric (see paragraph 161). Lee et al. also teaches wherein CXL memory controller 621 may include a storage manager, a mapping table manager, an address mapper, and a metadata buffer (see paragraph 183)… wherein mapping table manager may generate the map data by allocating the map data to the buffer memory BFM. The mapping table manager may modify the map data by changing the map data allocated to the buffer memory BFM. The mapping table manager may delete the map data by deallocating the map data allocated to the buffer memory BFM (see paragraph 185-187).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the medium taught by Roberts et al. to include the above mentioned to efficiently use the memory (see Lee, paragraph 194).
With respect claim 15, Roberts et al. teaches receiving, by a processing device, a request to perform a memory access operation at a first memory region of a first memory device of a plurality of memory devices (see paragraph 36; memory module 110 receives a memory access request targeting the memory location);
identifying, based on an operation type of the memory access operation, one or more corresponding actions associated with the metadata region (see paragraph 35; an access metadata rule for a memory location (e.g., a row of the storage array 116), indicating how the access metadata for the memory location is to be modified in response to a memory access request. Also in claim 1; in response to the first memory access request, adjusting, at the memory module, first access metadata indicating a pattern of accesses to the first location of the memory module);
causing the memory access operation to be performed on a first plurality of memory cells at the first memory device (see paragraphs 35-36; memory module 110 receives a memory access request targeting the memory location. In response, at block 408 the memory module 110 executes the memory access request by, for example, writing data to or reading data from the data payload fields of the memory location); and
responsive to causing the memory access operation to be performed, causing at least one of the one or more corresponding actions to be performed on a second plurality of memory cells corresponding to the metadata region (see paragraph 33; in response to receiving the memory access request 350, the ADM 115 modifies the access metadata at the memory location indicated by the metadata pointer field 352. Also, in paragraphs 35-37; ADM 115 initiates modification of the access metadata at the memory location by executing a low priority read of the access metadata fields at the memory location).
Roberts et al. does not teach determining, based on a data structure referencing a namespace accessible to a host system and to the plurality of memory devices, a mapping between an identifier of the first memory region and an identifier of a metadata region associated with the first memory region.
However, Lee et al. teaches CXL memory controller 621 may include a storage manager, a mapping table manager, an address mapper, and a metadata buffer (see paragraph 183)… wherein mapping table manager may generate the map data by allocating the map data to the buffer memory BFM. The mapping table manager may modify the map data by changing the map data allocated to the buffer memory BFM. The mapping table manager may delete the map data by deallocating the map data allocated to the buffer memory BFM (see paragraph 185-187).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Roberts et al. to include the above mentioned to efficiently use the memory (see Lee, paragraph 194).
With respect claim 16, Roberts et al. does not teach wherein each of the plurality of memory devices is a dynamic capacity device connected to the host system via a respective plurality of Compute Express Link (CXL) links.
However, Lee et al. teaches wherein each of the plurality of memory devices is a dynamic capacity device connected to the host system via a respective plurality of Compute Express Link (CXL) links (see paragraph 143; host 201 may be directly connected with the plurality of memory devices 202a and 202b. The host 201, the CXL storage 210, and the plurality of CXL memories 220_1 to 220_n may be connected with the CXL switch SW_CXL and may communicate with each other through the CXL switch).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Roberts et al. to include the above mentioned to efficiently use the memory (see Lee, paragraph 194).
With respect claim 19, Roberts et al. teaches wherein the one or more actions associated with the metadata region comprise at least one of: (i) a move operation to move metadata of the metadata region from a first physical location to a second physical location, (ii) a copy operation to copy at least a portion of the metadata of the metadata region, (iii) a reset operation to reset at least the portion of the metadata of the metadata region, (iv) a clone operation to duplicate at least the portion of the metadata of the metadata region, or (v) a computation operation to perform a computation operation to at least the portion of the metadata of the metadata region (see paragraph 28 and 32; the FN field 242 can indicate a given metadata value is to be incremented on read and write accesses, and is to be decremented on reset operations).
Claim(s) 3, 10 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Roberts et al. (US2016/0378668) and Lee et al. (US2023/0359379) as applied to claims 1, 8 and 15 above, and further in view of Durham et al (US2021/0405896) and Clark et al. (US2022/0114086).
With respect claim 3, Robert et al. and Lee et al. do not teach wherein the data structure comprises a plurality of entries, wherein each entry comprises an identifier of a memory region, a pointer referencing a physical location of a metadata region associated with the memory region, an identifier of a corresponding range of physical addresses of sets of memory cells residing on the plurality of memory devices.
However, Durham et al. teaches wherein for any given memory allocation slot 140 to which a memory allocation is assigned, unique metadata that is associated with the memory allocation is stored in a metadata region 150 defined in the given memory allocation slot 140… encoding of a virtual/linear address (pointer) for a memory allocation identifies a memory allocation slot to which the memory allocation is assigned and may include unique tag data that is associated with the memory allocation and with embedded metadata in the metadata region of the slot (see paragraph 42). Durham et al. also teaches encoded pointer 310 is created for one of the memory allocations 360 (e.g., 32B allocation, 56B allocation, 48B allocation, 24B allocation, or 64B allocation) and includes memory address 304 for an address within the memory range of that memory allocation (see paragraph 76).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Roberts et al. and Lee et al. to include the above mentioned to reduce memory overhead for storing metadata/tags, while providing performance optimizations (see Durham, paragraph 29).
Roberts et al., Lee et al. and Durham et al. does not teach an identifier of one or more host systems of a plurality of host systems, wherein the memory region is accessible by the one or more host systems.
However, Clark et al. teaches host-managed device memory (HDM) decoders 126 that may be programmed to facilitate a mapping of host to device physical addresses for use in system memory (e.g., pooled system memory) (see paragraph 21).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Roberts et al., Lee et al. and Durham et al. to include the above mentioned to improve the system (see Clark, paragraph 16).
With respect claim 10, Robert et al. and Lee et al. do not teach wherein the data structure comprises a plurality of entries, wherein each entry comprises an identifier of a memory region, a pointer referencing a physical location of a metadata region associated with the memory region, an identifier of a corresponding range of physical addresses of sets of memory cells residing on the plurality of memory devices, and an identifier of one or more host systems of a plurality of host systems, wherein the memory region is accessible by the one or more host systems.
However, Durham et al. teaches wherein for any given memory allocation slot 140 to which a memory allocation is assigned, unique metadata that is associated with the memory allocation is stored in a metadata region 150 defined in the given memory allocation slot 140… encoding of a virtual/linear address (pointer) for a memory allocation identifies a memory allocation slot to which the memory allocation is assigned and may include unique tag data that is associated with the memory allocation and with embedded metadata in the metadata region of the slot (see paragraph 42). Durham et al. also teaches encoded pointer 310 is created for one of the memory allocations 360 (e.g., 32B allocation, 56B allocation, 48B allocation, 24B allocation, or 64B allocation) and includes memory address 304 for an address within the memory range of that memory allocation (see paragraph 76).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Roberts et al. and Lee et al. to include the above mentioned to reduce memory overhead for storing metadata/tags, while providing performance optimizations (see Durham, paragraph 29).
Roberts et al., Lee et al. and Durham et al. does not teach an identifier of one or more host systems of a plurality of host systems, wherein the memory region is accessible by the one or more host systems.
However, Clark et al. teaches host-managed device memory (HDM) decoders 126 that may be programmed to facilitate a mapping of host to device physical addresses for use in system memory (e.g., pooled system memory) (see paragraph 21).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Roberts et al., Lee et al. and Durham et al. to include the above mentioned to improve the system (see Clark, paragraph 16).
With respect claim 17, Robert et al. and Lee et al. do not teach wherein the data structure comprises a plurality of entries, wherein each entry comprises an identifier of a memory region, a pointer referencing a physical location of a metadata region associated with the memory region, an identifier of a corresponding range of physical addresses of sets of memory cells residing on the plurality of memory devices, and
However, Durham et al. teaches wherein for any given memory allocation slot 140 to which a memory allocation is assigned, unique metadata that is associated with the memory allocation is stored in a metadata region 150 defined in the given memory allocation slot 140… encoding of a virtual/linear address (pointer) for a memory allocation identifies a memory allocation slot to which the memory allocation is assigned and may include unique tag data that is associated with the memory allocation and with embedded metadata in the metadata region of the slot (see paragraph 42). Durham et al. also teaches encoded pointer 310 is created for one of the memory allocations 360 (e.g., 32B allocation, 56B allocation, 48B allocation, 24B allocation, or 64B allocation) and includes memory address 304 for an address within the memory range of that memory allocation (see paragraph 76).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Roberts et al. and Lee et al. to include the above mentioned to reduce memory overhead for storing metadata/tags, while providing performance optimizations (see Durham, paragraph 29).
Roberts et al., Lee et al. and Durham et al. does not teach an identifier of one or more host systems of a plurality of host systems, wherein the memory region is accessible by the one or more host systems.
However, Clark et al. teaches host-managed device memory (HDM) decoders 126 that may be programmed to facilitate a mapping of host to device physical addresses for use in system memory (e.g., pooled system memory) (see paragraph 21).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Roberts et al., Lee et al. and Durham et al. to include the above mentioned to improve the system (see Clark, paragraph 16).
Claim(s) 4, 11 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Roberts et al. (US2016/0378668) and Lee et al. (US2023/0359379) as applied to claims 1, 8 and 15 above, and further in view of Durham et al (US2021/0405896).
With respect claim 4, Roberts et al. and Lee et al. do not teach wherein the operations further comprise: identifying, based on the data structure referencing the namespace, a first pointer referencing a first physical location of the metadata region associated with the first memory region.
However, Durham et al. teaches wherein for any given memory allocation slot 140 to which a memory allocation is assigned, unique metadata that is associated with the memory allocation is stored in a metadata region 150 defined in the given memory allocation slot 140… encoding of a virtual/linear address (pointer) for a memory allocation identifies a memory allocation slot to which the memory allocation is assigned and may include unique tag data that is associated with the memory allocation and with embedded metadata in the metadata region of the slot (see paragraph 42).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Roberts et al. and Lee et al. to include the above mentioned to reduce memory overhead for storing metadata/tags, while providing performance optimizations (see Durham, paragraph 29).
With respect claim 11, Roberts et al. and Lee et al. do not teach identifying, based on the data structure referencing the namespace, a first pointer referencing a first physical location of the metadata region associated with the first memory region.
However, Durham et al. teaches wherein for any given memory allocation slot 140 to which a memory allocation is assigned, unique metadata that is associated with the memory allocation is stored in a metadata region 150 defined in the given memory allocation slot 140… encoding of a virtual/linear address (pointer) for a memory allocation identifies a memory allocation slot to which the memory allocation is assigned and may include unique tag data that is associated with the memory allocation and with embedded metadata in the metadata region of the slot (see paragraph 42).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the medium taught by Roberts et al. and Lee et al. to include the above mentioned to reduce memory overhead for storing metadata/tags, while providing performance optimizations (see Durham, paragraph 29).
With respect claim 18, Roberts et al. and Lee et al. do not teach identifying, based on the data structure referencing the namespace, a first pointer referencing a first physical location of the metadata region associated with the first memory region.
However, Durham et al. teaches wherein for any given memory allocation slot 140 to which a memory allocation is assigned, unique metadata that is associated with the memory allocation is stored in a metadata region 150 defined in the given memory allocation slot 140… encoding of a virtual/linear address (pointer) for a memory allocation identifies a memory allocation slot to which the memory allocation is assigned and may include unique tag data that is associated with the memory allocation and with embedded metadata in the metadata region of the slot (see paragraph 42).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Roberts et al. and Lee et al. to include the above mentioned to reduce memory overhead for storing metadata/tags, while providing performance optimizations (see Durham, paragraph 29).
Claim(s) 6, 13 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Roberts et al. (US2016/0378668) and Lee et al. (US2023/0359379) as applied to claims 1, 8 and 15 above, and further in view of Okada et al (US2017/0075816).
With respect claim 6, Roberts et al. and Lee et al. do not teach wherein the metadata region associated with the first memory region is associated with a read-only access privilege to the host system.
However, Okada et al. teaches wherein IO translation table is a page table and includes an entry for each page (see paragraph 91). The entry of a page includes fields for a page number (#), a translation active flag, a target device, a physical address, a page size, a virtual address, and access rights… The access rights include a Read access right and a Write access right. The Read access right indicates whether Read access to the page can be executed. The Write access right indicates whether Write access to the page can be executed (see paragraph 92).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Roberts et al. and Lee et al. to include the above mentioned to provide memory access protection (see Okada, paragraph 75).
With respect claim 13, Roberts et al. and Lee et al. do not teach wherein the metadata region associated with the first memory region is associated with a read-only access privilege to the host system.
However, Okada et al. teaches wherein IO translation table is a page table and includes an entry for each page (see paragraph 91). The entry of a page includes fields for a page number (#), a translation active flag, a target device, a physical address, a page size, a virtual address, and access rights… The access rights include a Read access right and a Write access right. The Read access right indicates whether Read access to the page can be executed. The Write access right indicates whether Write access to the page can be executed (see paragraph 92).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the medium taught by Roberts et al. and Lee et al. to include the above mentioned to provide memory access protection (see Okada, paragraph 75).
With respect claim 20, Roberts et al. and Lee et al. do not teach wherein the metadata region associated with the first memory region is associated with a read-only access privilege to the host system.
However, Okada et al. teaches wherein IO translation table is a page table and includes an entry for each page (see paragraph 91). The entry of a page includes fields for a page number (#), a translation active flag, a target device, a physical address, a page size, a virtual address, and access rights… The access rights include a Read access right and a Write access right. The Read access right indicates whether Read access to the page can be executed. The Write access right indicates whether Write access to the page can be executed (see paragraph 92).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Roberts et al. and Lee et al. to include the above mentioned to provide memory access protection (see Okada, paragraph 75).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Goldberg et al. (US 2016/0011801) teaches storage region metadata management.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARACELIS RUIZ whose telephone number is (571)270-1038. The examiner can normally be reached Monday-Friday 11:00am-7:30pm.
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/ARACELIS RUIZ/Primary Examiner, Art Unit 2139