DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims:
Claims 1-20 are pending in Instant Application.
Priority
Priority is not claimed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 16-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 16 recites the limitation “the apparatus” in the last limitation of the claim. There is insufficient antecedent basis for this limitation in the claim.
The above cited rejections are merely exemplary.
The Applicant(s) are respectfully requested to correct all similar errors.
Claims not specifically mentioned are rejected by virtue of their dependency.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-6, 8-13, and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Tatar et al. (U.S. Publication No. 2007/0195777) in view Matthews et al. (U.S. Patent No. 11,943,128).
As per claim 1, Tatar teaches an apparatus in a network switch (Tatar: fig. 2; line card 200 of a network routing device coupled to switch fabric 270), comprising:
processing pipelines including outputs coupled to a switch circuit of the network switch (Tatar: paragraph 0046; Ingress Packet Processor 230 is a pipelined switch comprised of four parallel pipelines (or tiny pipes), wherein each pipe can perform the same series of operations on packet heads…paragraph 0047; Ingress Packet Processor 230 provides Ingress Traffic Management module 240 with the heads and tails…The Ingress Traffic Management module can then place the merged packet into a queue in preparation for transmission to the switch fabric);
a first circuit coupled between port groups of the network switch and inputs of the processing pipelines, the first circuit configured to distribute packets output from the port groups among the processing pipelines (Tatar: paragraph 0045; A plurality of shared port adapters (SPA) 210 are coupled to line card 200 via bridge 220…paragraph 0057; Bridge module 220 is the interface between shared port adapters 210 (SPA) and Ingress Packet Processor 230…paragraph 0074; Incoming heads and tails enter Pre-Fetch module 405 from bridge 220. State machine 406 forwards packet tails to tail buffer 436 in buffer manager interface module 430 and headers to one of four internal head buffers 408 via a head distribution mechanism 407…paragraph 0075; head distribution mechanism 407 can distribute headers to head buffers 408 in a cyclic manner…paragraph 0076; Each head buffer 408 can provide packet headers to any HPU tiny pipe. Packet header distribution from the head buffers to the tiny pipes is performed by buffer distributor 409); and
a memory coupled to the processing pipelines (Tatar: paragraph 0072; The HPU is coupled to a forwarding database 420, Netflow database 422, and classification database 424…paragraph 0158; Classification Database 424 is physically implemented with two separate memories: a CBSRAM for token buckets and a CSSRAM for statistics (e.g., head counters), in addition to TCAMs and other memories);
wherein the processing pipelines are configured to process streams of the packets through digital logic (Tatar: paragraph 0079; Each incoming packet head is associated with a PHB that contains the packet head as well as other switching information. That information is written into the PHB by the different stages of the tiny pipe…paragraph 0107; Execution unit 730 performs arithmetic and logic operations based on instructions from instruction Fetch stage 710 and data (operands) from operand Fetch stage 720…paragraph 0163; The PoP stage is responsible for the preparation of the buffer header (BHDR) and any necessary further classification processing) to generate results (Tatar: paragraph 0164; PoP stage 574 also performs buffer header (BHDR) tasks including: writing a free queue number and return queue number field in BHDR, writing local output queue field in BHDR, writing output queue field in BHDR, and calculating fabric length field in BHDR), supply the results to the switch circuit to switch the packets (Tatar: paragraph 0179; The primary function of Gather stage 576 is to collect together various pieces of data contained in a PHB and other registers (e.g., PAIR) in preparation for departure of the packet header from the HPU tiny pipe and transferring data into buffer manager interface module (BMI) 430…paragraph 0041; packets can be processed and routed in a multi-stage, parallel pipeline that can operate on several packets at the same time to determine each packet's routing destination. Once that determination is made, each received packet can be modified to contain new routing information as well as additional header data to facilitate the packet's transmission through the switching fabric…each packet is then buffered and enqueued for transmission through the switching fabric to the corresponding destination port), and write and read the state to and from the memory (Tatar: paragraph 0158; The entries of Match FIFO 1150 can be read sequentially by Read Match module 1210, which then determines whether to write the entry as a read request to Classification Database 424 through Classification SRAM Controller (CSC) Interface 1250…Classification Database 424 is physically implemented with two separate memories: a CBSRAM for token buckets and a CSSRAM for statistics…paragraph 0160; Data read from Classification Database 424 can be split between CAR Logic module 1240 and an appropriate PHB…CAR Logic module 1240 can write an updated CAR bucket back to a FIFO that is part of the Classification Database 424).
Tatar teaches port adapters (SPA) 210, see at least paragraph 0045. However Tatar does not explicitly mention port groups; and processing pipelines are based on state for the port groups.
However Matthews teaches:
port groups (Matthews: col. 33, lines 24-28; The ingress ports 610 are divided into port groups 610a-n, and each group of ports 610 feeds data units to a different pipeline 602 of processing components. There may be any number of groups of ports 610, and hence any number of corresponding pipelines 602); and
processing pipelines are based on state for the port groups (Matthews: col. 32, lines 59-67; Port state data may include, for instance, flow control state information describing various traffic flows and associated traffic flow control rules or policies, link status information indicating links that are up or down, port utilization information indicating how ports are being utilized (e.g. utilization percentages, utilization states, etc.). Forwarding logic may be configured to implement the associated rules or policies associated with the flow(s) to which a given packet belongs).
Therefore it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings as in Matthews with the teachings as in Tatar. The motivation for doing so would have been in order to quickly determine where to send and/or store data for processing, and to expediently send and/or store that data to the appropriate destination once determined and to handle network traffic in a manner that will optimally utilize available network resources throughout the network in which the device is situated (Matthews: col. 2, lines 46-54).
As per claim 2, the modified Tatar teaches the apparatus of claim 1, wherein the memory comprises: memory circuits configured to store the state for the port groups (Tatar: paragraph 0158; Classification Database 424 is physically implemented with two separate memories: a CBSRAM for token buckets and a CSSRAM for statistics (e.g., head counters), in addition to TCAMs and other memories. See also Matthews: col. 33, lines 24-28; The ingress ports 610 are divided into port groups 610a-n), each of the memory circuits configured to store a respective portion of the state for at least one of the port groups (Tatar: paragraph 0158; Classification Database 424 is physically implemented with two separate memories: a CBSRAM for token buckets and a CSSRAM for statistics (e.g., head counters), in addition to TCAMs and other memories. See also Matthews: col. 32, lines 11-30; a device 500 will typically store in its memories one or more forwarding tables (or equivalent structures) that map certain data unit attributes or characteristics to actions to be taken with respect to data units 505 having those attributes or characteristics, such as sending a data unit 505 to a selected path, or processing the data unit 505 using a specified internal component. For instance, such attributes or characteristics may include a Quality-of-Service level specified by the data unit 505 or associated with another characteristic of the data unit 505, a flow control group, an ingress port 510 through which the data unit 505 was received, a tag or label in a packet's header, a source address, a destination address, a packet type, or any other suitable distinguishing property. The forwarding logic may, for example, read such a table, determine one or more ports 590 to send a data unit 505 to based on the table, and add or associate the data unit 505 with information that indicates to downstream logic to send the data unit 505 along a path that includes a specific traffic manager 540 and/or egress processor 550 that is coupled to the one or more ports 590…col. 32, lines 59-67; Port state data may include, for instance, flow control state information describing various traffic flows and associated traffic flow control rules or policies, link status information indicating links that are up or down, port utilization information indicating how ports are being utilized (e.g. utilization percentages, utilization states, etc.). Forwarding logic may be configured to implement the associated rules or policies associated with the flow(s) to which a given packet belongs); wherein the apparatus comprises a second circuit configured to arbitrate access to the memory circuits among the processing pipelines (Tatar: paragraph 0148; Classification Database 424 is associated with the CAMP stages and accessible via Classification TCAM Controller 1130…paragraph 0154; CAM-Match Control Logic module 1120…the CAM-Match Control Logic module transmits a request to Classification Database 424. That request can remain asserted until the Classification Database acknowledges Lookup result determination).
The same motivation to combine as the independent claim applies here.
As per claim 3, the modified Tatar teaches the apparatus of claim 1, wherein the memory is configured to store respective portions of the state for respective ones of the port groups, wherein the memory includes multiple ports (Tatar: paragraph 0060; buffer memory 330 can be configured into 64 separate buffers. Each buffer can be assigned to a port of an SPA. See also Matthews: col. 33, lines 24-28; The ingress ports 610 are divided into port groups 610a-n...col. 32, lines 58-59; forwarding logic may read port state data for ports 510/590), and wherein the processing pipelines are configured to access the memory via the ports (Tatar: paragraph 0148; Classification Database 424 is associated with the CAMP stages and accessible via Classification TCAM Controller 1130…The result bus can be connected directly to a CSRAM as the address bus; thus, content of the address in the CSRAM can be read by the CAMP stages. See also Matthews: col. 32, lines 58-59; forwarding logic may read port state data for ports 510/590).
The same motivation to combine as the independent claim applies here.
As per claim 4, the modified Tatar teaches the apparatus of claim 1, wherein a first bandwidth for each of the processing pipelines is the same or less than a second bandwidth of the processing pipelines in aggregate (Tatar: paragraph 0046; ingress Packet Processor 230 is a pipelined switch comprised of four parallel pipelines (or tiny pipes), wherein each pipe can perform the same series of operations on packet heads …paragraph 0075; head distribution mechanism 407 can distribute headers to head buffers 408 in a cyclic manner…paragraph 0211; The function of the algorithm is to round robin among the queues based on allocated bandwidth, rather than a number of packets sent. MDRR is based upon DRR but with the addition of one high-priority queue per slot).
The same motivation to combine as the independent claim applies here.
As per claim 5, the modified Tatar teaches the apparatus of claim 1, further comprising: a second circuit configured to couple outputs of the processing pipelines to inputs of the switch circuit (Tatar: paragraph 0073; Once HPU 410 has completed analysis of the packet heads, the packet heads are forwarded in parallel to buffer manager interface module 430. Buffer manager interface module 430 is responsible for forwarding packet heads and tails to Ingress Traffic Management module 240…paragraph 0048; Ingress Traffic Management module 240 passes packets to appropriate FIFOs in switch fabric interface 250. In this aspect, the switch fabric interface can fragment the unicast and multicast packets received from the Ingress Traffic Management module into uniformly sized and appropriately identified cells to be transmitted through switch fabric 270).
As per claim 6, the modified Tatar teaches the apparatus of claim 5, comprising M port groups and K processing pipelines, where M and K are integers (Matthews: col. 33, lines 24-28; The ingress ports 610 are divided into port groups 610a-n, and each group of ports 610 feeds data units to a different pipeline 602 of processing components. There may be any number of groups of ports 610, and hence any number of corresponding pipelines 602), and where the second circuit is configured to couple K of the streams of packets to M of the inputs of the switch circuit (Tatar: paragraph 0185; BMI 430 is responsible for collecting headers and associated data from the four tiny pipes of HPU 410 and transferring that information to the Ingress or Egress Traffic Management modules…paragraph 0048; Ingress Traffic Management module 240 passes packets to appropriate FIFOs in switch fabric interface 250…paragraph 0225; SLI interface module 1750 receives cell data from cell FIFO module 1740 and provides that information to SLI module 1755…SLI interface module 1750 can divide each cell across four SLI data paths (and subsequently to four corresponding switch fabric cards), and redundant data can be sent along a fifth SLI data path).
The same motivation to combine as the independent claim applies here.
Regarding claims 8-13, they are substantially similar to claims 2-6, respectively, and are rejected in the same manner, the same arts and reasoning applying.
With respect to Claim 15, it is substantially similar to Claim 1 and is rejected in the same manner, the same art and reasoning applying. Further, the modified Tatar also teaches a network switch, comprising: port groups; a switch circuit coupled to the port groups; a hardware platform coupled to the port groups and the switch circuit, the hardware platform comprising: (Tatar: fig. 2, paragraph 0045; plurality of shared port adapters (SPA) 210 are coupled to line card 200 via bridge 220…Bridge 220 then sends interleaved heads and tails from each incoming FIFO memory to Ingress Packet Processor 230…paragraph 0046; Ingress Packet Processor 230 is a pipelined switch comprised of four parallel pipelines (or tiny pipes)…paragraph 0048; Ingress Traffic Management module 240 passes packets to appropriate FIFOs in switch fabric interface 250…paragraph 0218; Switch Fabric Interface 250 is responsible for communicating packet information with Switch Fabric 270. See also Matthews: col. 33, lines 24-28; The ingress ports 610 are divided into port groups 610a-n, and each group of ports 610 feeds data units to a different pipeline 602 of processing components. There may be any number of groups of ports 610, and hence any number of corresponding pipelines 602).
Regarding claims 16-20, they are substantially similar to claims 2-6, respectively, and are rejected in the same manner, the same arts and reasoning applying.
Claims 7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Tatar et al. (U.S. Publication No. 2007/0195777), in view Matthews et al. (U.S. Patent No. 11,943,128), and further in view of Scheurich et al. (U.S. Publication No. 2015/0341253).
As per claim 7, the modified Tatar teaches the apparatus of claim 6.
However the modified Tatar does not explicitly mention wherein K is less than M.
However Scheurich teaches:
wherein K is less than M (Scheurich: fig. 3 and paragraph 0047; the switch comprises an OpenFlow pipeline 342 to store and execute forwarding rules that implements packet forwarding. Furthermore, ports 344 are provided which are used to receive or send traffic. These ports are connected to the OpenFlow pipeline 342…see also fig. 5 and paragraph 0056; The split horizon means that the switches comprise two different port groups and switching is only forwarded from ports of one group to ports of the other group).
Therefore it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings as in Scheurich with the teachings as in Tatar. The motivation for doing so would have been in order to avoid accidental switching loops if the booting switch is connected to several other switches (Scheurich: paragraph 0053).
Regarding claim 14, it is substantially similar to claim 7, and is rejected in the same manner, the same arts and reasoning applying.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KARINA J. GARCIA-CHING whose telephone number is (571)270-7159. The examiner can normally be reached Monday - Wednesday (9:00 AM - 5:00 PM).
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/KARINA J GARCIA-CHING/Examiner, Art Unit 2449
/VIVEK SRIVASTAVA/Supervisory Patent Examiner, Art Unit 2449
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