Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the application filed on 01/30/2025.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/30/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference characters not mentioned in the description: 118 (Fig. 19), 119 (Fig. 21), and 302 (Fig. 19). Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference characters in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to because of the following informalities.In Fig. 3, “LAPLSE” appears that it should read as “LAPSE”;
in Fig. 3, “IMMEDEATELY” appears that it should read as “IMMEDIATELY”.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed, i.e. including an adjustable threshold voltage for gradually increasing and gradually reducing an ON period in a burst mode.
The disclosure is objected to because of the following informalities:
In [0007], “control IC 42a” appears that it should read as “control IC 40a”, according to Fig. 2;
in [0035], “first resistor” appears that it should read as “first terminal”, because the terminal STB corresponds to the first terminal to which the resistor 58 is connected;
in [0051], “heavy load state load” appears that it should read as “heavy load state”;
in [0082], “are operated” appears that it should read as “is operated;
in [0137], “setting circuit 201” appears that it should read as “setting circuit 203”, because the data indicating the level of the reference voltage Vref1 is received by the setting circuit 203 of the control IC 40d (see [0124] and Fig. 19);
in [0140], “easily change” appears that it should read as “easily changing”.
Appropriate correction is required.
Claim Objections
Claims 6, 8, and 14 are objected to because of the following informalities:
Regarding claim 6, in lines 7-8, “stopping the switching the first transistor” appears that it should read as “stopping the switching of the first transistor”.
Regarding claim 8, in line 7, “a voltage of the auxiliary coil” appears that it should read as “the voltage of the auxiliary coil”, because of antecedent basis.
Regarding claim 14, in line 3, “a voltage of the resistor” appears that it should read as “the voltage of the resistor”, because of antecedent basis.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 4-8, 12, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US Patent Application Publication US 2017/0373604 A1, hereinafter “Chen ’604”) in view of Chen et al. (US Patent Application Publication US 2021/0305888 A1, hereinafter “Chen ’888”).
Regarding claim 1, Chen ’604 discloses (see Fig. 12, Fig. 2, Fig. 3, Fig. 4, and Fig. 10) a switching control circuit (control IC 12) for controlling a power supply circuit (switching power supply apparatus of Fig. 12) that generates an output voltage (output DC voltage Vo) at a target level on a secondary side (see [0035] of Chen ’604 “The secondary windings S1 and S2, the diodes D3 and D4, and the output capacitor C10 make up a circuit which rectifies and smooths an AC voltage generated in the secondary windings S1 and S2 and which converts it to an output DC voltage Vo.”; see [0036] of Chen ’604 “The shunt regulator SR1 causes a current corresponding to the difference between a voltage obtained by dividing an output voltage Vo (voltage across the output capacitor C10) and an internal reference voltage to flow to the light-emitting diode of the photocoupler PC1.”) from an input voltage (input DC voltage Vi) thereof (see [0033] of Chen ’604 “An input DC voltage Vi is applied to the input capacitor C1.”), the power supply circuit including a transformer (T1) including a primary coil (primary winding P1), a secondary coil (secondary windings S1 and S2), and an auxiliary coil (auxiliary winding P2) (see [0079] of Chen ’604 “With the switching power supply apparatus according to the third embodiment the transformer T1 includes the auxiliary winding P2.”), a first transistor (switching element Qa) and a second transistor (switching element Qb) that are configured to control a current of the primary coil (see [0053] of Chen ’604 “By on-off controlling the switching elements Qa and Qb, a resonance current of the resonance circuit is controlled.”), and a first capacitor (resonance capacitor C6) that forms a resonant circuit with the primary coil (see [0034] of Chen ’604 “A leakage inductance component between the primary winding P1 and secondary windings S1 and S2 of the transformer T1 and the resonance capacitor C6 make up a resonance circuit.”), the switching control circuit being configured to control switching of the first transistor and the second transistor (control IC 12, which on-off controls the switching elements Qa and Qb through the high-side drive circuit 24 and the low-side drive circuit 25; see [0053] of Chen ’604 “As a result, the high-side drive circuit outputs a signal VHO illustrated in FIG. 7 to the HO terminal to on-off control the switching element Qa. The low-side drive circuit 25 outputs a signal VLO illustrated in FIG. 7 to the LO terminal to on-off control the switching element Qb.”), the switching control circuit comprising: a comparator circuit (hysteresis comparator COMP3) configured to compare each of a first voltage (threshold voltage Vfbss) and a second voltage (threshold voltage Vfbse, which is shown in Fig. 10 below the threshold voltage Vfbss) lower than the first voltage, with a feedback voltage (voltage VFB at the FB terminal) corresponding to the output voltage (see [0046] of Chen ’604 “An inverting input terminal of the hysteresis comparator COMP3 is connected to the FB terminal of the control IC 12 and a non-inverting input terminal of the hysteresis comparator COMP3 is connected to a terminal which receives a threshold voltage Vfbss or Vfbse generated inside the control IC 12.”; see [0036] of Chen ’604 “A collector terminal of a phototransistor of the photocoupler PC1 is connected to an FB terminal of a control integrated circuit (IC) 12.”); and a drive signal output circuit (oscillation circuit 22, control circuit 23, high-side drive circuit 24, low-side drive circuit 25, and constant-current sources Ichg and Idchg of charge and discharge circuit 26) configured to output a drive signal (signals VHO and VLO) to operate the power supply circuit in a normal mode (see [0051] of Chen ’604 “First when the switching power supply apparatus operates in a normal mode, the control circuit 23 outputs a low(L)-level burst operation signal bur_en.”), and output the drive signal to operate the power supply circuit in a burst mode (burst operation in the standby mode, in which the load is light; see [0056] of Chen ’604 “With burst operation in the standby mode the control circuit 23 outputs a high(H)-level burst operation signal bur_en.”; see [0068] of Chen ’604 “A load is light in the standby mode.”), wherein the drive signal output circuit enters a first state (soft start) of outputting the drive signal to gradually increase an ON period of each of the first transistor and the second transistor (see [0067] of Chen ’604 “With a soft start control is exercised so that as the voltage VCS rises, a switching frequency of the oscillation circuit 22 will become lower.”), in response to the feedback voltage exceeding the first voltage (see [0068] of Chen ’604 “When the voltage VFB at the FB terminal exceeds the threshold voltage Vfbss, an output of the hysteresis comparator COMP3 becomes an L level, an output of the AND circuit AND1 becomes an L level, and an output of the inverter circuit INV4 becomes an H level.”; see [0068] of Chen ’604 “As a result, charging the capacitor C4 by the constant-current source Ichg is begun, the voltage VCS at the CS terminal begins to rise, and a soft start is begun.”), and enters a second state (soft end) of outputting the drive signal to gradually reduce the ON period of each of the first transistor and the second transistor (see [0067] of Chen ’604 “With a soft end control is exercised so that as the voltage VCS falls, a switching frequency of the oscillation circuit 22 will become higher.”), in response to the feedback voltage dropping below the second voltage (see [0070] of Chen ’604 “When the voltage VFB falls below the threshold voltage Vfbse, an output of the hysteresis comparator COMP3 becomes an H level, an output of the AND circuit AND1 becomes an H level, and an output of the inverter circuit INV4 becomes an L level.”; see [0070] of Chen ’604 “As a result, discharging the capacitor C4 by the constant-current source Idchg is begun and the voltage VCS at the CS terminal begins to fall.”).
Examiner’s Note: Figs. 2-4 and 10 of Chen ’604 show the control IC 12, the oscillation circuit 22, the charge and discharge circuit 26, and the burst operation that are used in the third embodiment of Fig. 12, which differs from the first embodiment in that the peak power limiting circuit 27 monitors the voltage of the auxiliary winding P2 (see [0077] of Chen ’604 “Components in FIGS. 12, 13, and 14 which are the same as or equivalent to those illustrated in FIGS. 1, 5, and 8, respectively, are marked with the same numerals and detailed descriptions of them will be omitted.”; see [0078] of Chen ’604 “With the switching power supply apparatus according to the third embodiment, on the other hand, peak power at burst operation time is monitored, as illustrated in FIG. 12, by a voltage across an auxiliary winding P2 of a transformer T1.”). Accordingly, the rejections based on Chen ’604 rely on the single third embodiment of Figs. 12-14.
Chen ’604 does not disclose a first adjustment circuit configured to adjust a level of the first voltage; and a drive signal output circuit configured to output a drive signal to operate the power supply circuit in a normal mode, in response to a state of a load of the power supply circuit entering a heavy-load state, and output the drive signal to operate the power supply circuit in a burst mode, in response to the state of the load entering a light-load state.
However, Chen ’888 teaches (see Fig. 1 and Fig. 2) a first adjustment circuit (burst-voltage setting circuit 113) configured to adjust a level of the first voltage (burst voltage VBST, which comparator 114 compares with feedback voltage VFB) (see [0018] of Chen ’888 “Burst-voltage setting circuit 113 electrically connects to setting pin BSTS, and detects the resistance of external resistor RST to generate burst voltage VBST.”; see [0019] of Chen ’888 “Comparator 114 compares feedback voltage VFB with burst voltage VBST.”); and a drive signal output circuit (ON-time generator 110, burst-mode controller 112, logic 116, and gate drivers 118 and 120) configured to output a drive signal (signals SH and SL) to operate the power supply circuit (LLC resonant converter 100) in a normal mode (non-burst mode), in response to a state of a load (load 104) of the power supply circuit entering a heavy-load state (see [0019] of Chen ’888 “When feedback voltage VFB exceeds burst voltage VBST, multiplexer 122 outputs feedback voltage VFB, and power controller 102 operates LLC resonant converter 100 in a non-burst mode, where only work time WK exists and break time BRK disappears.”; see [0015] of Chen ’888 “From another point of view, if output voltage VOUT is about the same as target voltage VTRGT, the lighter load 104 the lower feedback voltage VFB.”), and output the drive signal to operate the power supply circuit in a burst mode, in response to the state of the load entering a light-load state (see [0012] of Chen ’888 “According to embodiments of the invention, an LLC resonant converter operates in a burst mode when its load is light or non-existent.”; see [0019] of Chen ’888 “Simply speaking, when feedback voltage VFB is below burst voltage VBST, multiplexer 122 outputs burst voltage VBST, and power controller 102 operates LLC resonant converter 100 in a burst mode, where break time BRK and alternates with work time WK.”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the switching control circuit of Chen ’604 to include a first adjustment circuit configured to adjust a level of the first voltage; and a drive signal output circuit configured to output a drive signal to operate the power supply circuit in a normal mode, in response to a state of a load of the power supply circuit entering a heavy-load state, and output the drive signal to operate the power supply circuit in a burst mode, in response to the state of the load entering a light-load state, as taught by Chen ’888, because it can help allow the feedback voltage threshold, which determines the load at which the power supply circuit operates in the burst mode, to be selected for each application with an external resistor (see [0036] of Chen ’888 “A system engineer could select external resistor RST to determine the load threshold which determines the quantity of load 104 for LLC resonant converter 100 to operate in a burst mode.”), and help reduce switching losses by operating the power supply circuit in the burst mode when the load is light (see [0034] of Chen ’888 “The introduction of break time can reduce switching losses of high-side and low-side switches HS and LS, improving power conversion efficiency.”).
Regarding claim 4, Chen ’604 discloses (see Fig. 4 and Fig. 10) wherein the drive signal output circuit enters the first state and the second state when the power supply circuit operates in the burst mode (the soft start and the soft end are performed in the burst operation, in which the charge and discharge circuit 26 is enabled by the high-level burst operation signal bur_en; see [0056] of Chen ’604 “As a result, the charge and discharge circuit 26 enables charging and discharging operation and the peak power limiting circuit 27 enables outputting a forced turn-off signal off_trg_p.”; see [0067] of Chen ’604 “With the burst operation in the standby mode the oscillation circuit 22 is frequency-controlled by a voltage VCS at the CS terminal.”).
Regarding claim 5, Chen ’604 discloses (see Fig. 3, Fig. 12, Fig. 13, and Fig. 14) wherein the drive signal output circuit is further configured to operate in a third state (peak power limiting operation of the peak power limiting circuit 27) between the first state and the second state (see [0072] of Chen ’604 “In an effective region between the ineffective switching region of the soft start and the ineffective switching region of the soft end, the amount of energy transmitted from the primary side to the secondary side is large and the output voltage Vo gradually rises.”; see [0072] of Chen ’604 “Furthermore, if the amount of energy transmitted from the primary side to the secondary side is excessive in this effective region, then peak power is limited by the peak power limiting circuit 27.”), the third state being a state of outputting the drive signal to set the ON period of each of the first transistor and the second transistor according to a voltage of the auxiliary coil (voltage VPL, obtained by dividing the output voltage of the auxiliary winding P2, determines the forced turn-off signal off_trg_p that ends the ON period of each of the switching elements Qa and Qb; see [0080] of Chen ’604 “The output voltage of the auxiliary winding P2 is divided by a voltage division circuit made up of the resistors R3 and R4 and is supplied to the PL terminal of the control IC 12.”; see [0083] of Chen ’604 “When the voltage VPL falls below the high-side threshold voltage Vref_h, the comparator COMP4 outputs an H-level signal hi_off.”; see [0083] of Chen ’604 “The signal outputted from the one-shot circuit OS3 is outputted via an OR circuit OR2 and an AND circuit AND2 to an output terminal of the peak power limiting circuit 27 as a forced turn-off signal off_trg_p.”; see [0084] of Chen ’604 “On the other hand, when the voltage VPL exceeds the low-side threshold voltage Vref_l, the comparator COMP5 outputs an H-level signal lo_off.”), and the drive signal output circuit transitions from the first state to the third state, in response to the ON period of each of the first transistor and the second transistor determined according to the voltage of the auxiliary coil becoming shorter than the ON period of each of the first transistor and the second transistor in the first state (the forced turn-off signal off_trg_p and the output of the comparator COMP1 are both input to the OR circuit OR1, such that the ON period is ended by the forced turn-off signal off_trg_p whenever that signal occurs before the charging voltage Vos reaches the voltage VCS; see [0043] of Chen ’604 “An output terminal of the comparator COMP1 is connected to a first input terminal of an OR circuit OR1.”; see [0061] of Chen ’604 “On the other hand, with burst operation in the standby mode not only output signals of the comparator COMP1 and the hysteresis comparator COMP2 but also a forced turn-off signal off_trg_p from the peak power limiting circuit 27 is inputted to the set input terminal S of the RS flip-flop RS-FF1.”; see [0064] of Chen ’604 “However, before a charging voltage Vos of the capacitor Cos exceeds one of a voltage at the FB terminal and a voltage at the CS terminal which is lower than the other, the forced turn-off signal off_trg_p is inputted.”; see [0087] of Chen ’604 “When input power monitored at burst operation time in a standby mode exceeds a determined value, a forced turn-off signal is outputted earlier than a regular off-trigger signal to suppress peak power and reduce audible noise.”) (Examiner’s Note: Because the output of the comparator COMP1, which ends the ON period according to the voltage VCS, and the forced turn-off signal off_trg_p, which ends the ON period according to the voltage VPL of the auxiliary winding P2, are both applied to the set input terminal S of the RS flip-flop RS-FF1 through the OR circuit OR1, the ON period of each of the switching elements Qa and Qb is ended by whichever of the two signals occurs first. Accordingly, the ON period is set according to the voltage VPL of the auxiliary winding P2 once that ON period becomes shorter than the ON period set by the rising voltage VCS of the soft start, and the ON period is again set by the voltage VCS once the ON period set by the falling voltage VCS of the soft end becomes shorter than the ON period set according to the voltage VPL of the auxiliary winding P2. This transition behavior necessarily flows from the structure of the OR circuit OR1 and is therefore inherent in Chen ’604).
Regarding claim 6, Chen ’604 discloses (see Fig. 10 and Fig. 12) wherein the drive signal output circuit controls switching of the first transistor and the second transistor so as to have a switching operation period (period in which the switching elements Qa and Qb are switched in the burst operation) of transitioning from the first state to the second state through the third state (soft start, peak power limiting in the effective region, and soft end; see [0072] of Chen ’604 “In an effective region between the ineffective switching region of the soft start and the ineffective switching region of the soft end, the amount of energy transmitted from the primary side to the secondary side is large and the output voltage Vo gradually rises.”; see [0072] of Chen ’604 “Furthermore, if the amount of energy transmitted from the primary side to the secondary side is excessive in this effective region, then peak power is limited by the peak power limiting circuit 27.”), and a stop operation period (period in which switching of the switching elements Qa and Qb is stopped) of stopping the switching the first transistor and the second transistor (see [0070] of Chen ’604 “When the voltage VCS at the CS terminal becomes lower than the threshold voltage Vcsoff on the low potential side, an output of the hysteresis comparator COMP2 becomes an H level and switching of the switching elements Qa and Qb is stopped.”), when the power supply circuit operates in the burst mode (see [0066] of Chen ’604 “FIG. 10 illustrates operational waveforms in the burst operation in the standby mode.”).
Regarding claim 7, Chen ’604 discloses (see Fig. 10) wherein the stop operation period is included in a time period from completion of the second state to start of the first state (switching is stopped when the voltage VCS falls below the threshold voltage Vcsoff at the end of the soft end, and switching is begun again when the voltage VCS exceeds the threshold voltage Vcson in the next soft start; see [0070] of Chen ’604 “When the voltage VCS at the CS terminal becomes lower than the threshold voltage Vcsoff on the low potential side, an output of the hysteresis comparator COMP2 becomes an H level and switching of the switching elements Qa and Qb is stopped.”; see [0069] of Chen ’604 “When the voltage VCS at the CS terminal increases and exceeds the high-side threshold voltage Vcson generated inside the control IC 12, an output of the hysteresis comparator COMP2 becomes an L level. As a result, switching is begun.”).
Regarding claim 8, Chen ’604 discloses (see Fig. 3, Fig. 10, and Fig. 12) wherein the drive signal output circuit transitions from the third state to the second state, in response to the ON period of each of the first transistor and the second transistor in the second state becoming shorter than the ON period of each of the first transistor and the second transistor determined according to a voltage of the auxiliary coil (in the soft end, the voltage VCS falls, such that the ON period ended through the comparator COMP1 according to the voltage VCS becomes shorter than the ON period ended by the forced turn-off signal off_trg_p according to the voltage VPL of the auxiliary winding P2, both signals being input to the OR circuit OR1, as explained in the Examiner’s Note following claim 5; see [0043] of Chen ’604 “An output terminal of the comparator COMP1 is connected to a first input terminal of an OR circuit OR1.”; see [0043] of Chen ’604 “A second input terminal of the OR circuit OR1 is connected to a terminal which receives a forced turn-off signal off_trg_p from the peak power limiting circuit 27.”; see [0070] of Chen ’604 “As a result, discharging the capacitor C4 by the constant-current source Idchg is begun and the voltage VCS at the CS terminal begins to fall.”).
Regarding claim 12, Chen ’604 discloses (see Fig. 2 and Fig. 12) wherein the switching control circuit is an integrated circuit (control IC 12) (see [0036] of Chen ’604 “A collector terminal of a phototransistor of the photocoupler PC1 is connected to an FB terminal of a control integrated circuit (IC) 12.”).
Chen ’604 does not disclose wherein the switching control circuit is an integrated circuit including a first terminal to which a resistor is connected, and a constant current circuit configured to supply a predetermined current to the resistor, and the first adjustment circuit adjusts the level of the first voltage, based on a voltage of the resistor.
However, Chen ’888 teaches (see Fig. 1 and Fig. 2) wherein the switching control circuit is an integrated circuit (power controller 102) including a first terminal (setting pin BSTS) to which a resistor (external resistor RST) is connected (see [0014] of Chen ’888 “Power controller 102 according to embodiments of the invention is a packaged integrated circuit having, but not limited to have, power source pin VCC, feedback pin FB, setting pin BSTS, high-side drive pin HGATE, high-side ground pin HGND, low-side drive pin LGATE, and ground pin GND.”; see [0016] of Chen ’888 “Setting pin BSTS of power controller 102 is electrically connected to an external resistor RST, whose resistance for example is detected by power controller 102 to determine burst voltage VBST.”), and a constant current circuit (constant current source IS) configured to supply a predetermined current to the resistor (see [0018] of Chen ’888 “For example, burst-voltage setting circuit 113 has constant current source IS supplying a constant current flowing through external resistor RST, and burst voltage VBST is, but is not limited to be, the voltage at setting pin BSTS plus 0.2V, which is the minimum value of feedback voltage VFB.”), and the first adjustment circuit (burst-voltage setting circuit 113) adjusts the level of the first voltage (burst voltage VBST), based on a voltage of the resistor (voltage at setting pin BSTS) (see [0018] of Chen ’888 “Burst-voltage setting circuit 113 electrically connects to setting pin BSTS, and detects the resistance of external resistor RST to generate burst voltage VBST.”; see [0018] of Chen ’888 “For example, burst-voltage setting circuit 113 has constant current source IS supplying a constant current flowing through external resistor RST, and burst voltage VBST is, but is not limited to be, the voltage at setting pin BSTS plus 0.2V, which is the minimum value of feedback voltage VFB.”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the switching control circuit of Chen ’604 wherein the switching control circuit is an integrated circuit including a first terminal to which a resistor is connected, and a constant current circuit configured to supply a predetermined current to the resistor, and the first adjustment circuit adjusts the level of the first voltage, based on a voltage of the resistor, as taught by Chen ’888, because it can help allow the level of the first voltage to be selected with a single external resistor connected to the integrated circuit (see [0036] of Chen ’888 “A system engineer could select external resistor RST to determine the load threshold which determines the quantity of load 104 for LLC resonant converter 100 to operate in a burst mode.”).
Regarding claim 16, Chen ’604 discloses (see Fig. 12, Fig. 2, Fig. 3, Fig. 4, and Fig. 10) a power supply circuit (switching power supply apparatus of Fig. 12) configured to generate an output voltage (output DC voltage Vo) at a target level on a secondary side (see [0035] of Chen ’604 “The secondary windings S1 and S2, the diodes D3 and D4, and the output capacitor C10 make up a circuit which rectifies and smooths an AC voltage generated in the secondary windings S1 and S2 and which converts it to an output DC voltage Vo.”; see [0036] of Chen ’604 “The shunt regulator SR1 causes a current corresponding to the difference between a voltage obtained by dividing an output voltage Vo (voltage across the output capacitor C10) and an internal reference voltage to flow to the light-emitting diode of the photocoupler PC1.”) from an input voltage (input DC voltage Vi) thereof (see [0033] of Chen ’604 “An input DC voltage Vi is applied to the input capacitor C1.”), the power supply circuit comprising: a transformer (T1) including a primary coil (primary winding P1), a secondary coil (secondary windings S1 and S2), and an auxiliary coil (auxiliary winding P2) (see [0079] of Chen ’604 “With the switching power supply apparatus according to the third embodiment the transformer T1 includes the auxiliary winding P2.”); a first transistor (switching element Qa) and a second transistor (switching element Qb) that are configured to control a current of the primary coil (see [0053] of Chen ’604 “By on-off controlling the switching elements Qa and Qb, a resonance current of the resonance circuit is controlled.”); a first capacitor (resonance capacitor C6) forming a resonant circuit with the primary coil (see [0034] of Chen ’604 “A leakage inductance component between the primary winding P1 and secondary windings S1 and S2 of the transformer T1 and the resonance capacitor C6 make up a resonance circuit.”); and a switching control circuit (control IC 12, which on-off controls the switching elements Qa and Qb through the high-side drive circuit 24 and the low-side drive circuit 25; see [0053] of Chen ’604 “As a result, the high-side drive circuit outputs a signal VHO illustrated in FIG. 7 to the HO terminal to on-off control the switching element Qa. The low-side drive circuit 25 outputs a signal VLO illustrated in FIG. 7 to the LO terminal to on-off control the switching element Qb.”) configured to control switching of the first transistor and the second transistor, wherein the switching control circuit includes a comparator circuit (hysteresis comparator COMP3) configured to compare each of a first voltage (threshold voltage Vfbss) and a second voltage (threshold voltage Vfbse, which is shown in Fig. 10 below the threshold voltage Vfbss) lower than the first voltage, with a feedback voltage (voltage VFB at the FB terminal) corresponding to the output voltage (see [0046] of Chen ’604 “An inverting input terminal of the hysteresis comparator COMP3 is connected to the FB terminal of the control IC 12 and a non-inverting input terminal of the hysteresis comparator COMP3 is connected to a terminal which receives a threshold voltage Vfbss or Vfbse generated inside the control IC 12.”; see [0036] of Chen ’604 “A collector terminal of a phototransistor of the photocoupler PC1 is connected to an FB terminal of a control integrated circuit (IC) 12.”), and a drive signal output circuit (oscillation circuit 22, control circuit 23, high-side drive circuit 24, low-side drive circuit 25, and constant-current sources Ichg and Idchg of charge and discharge circuit 26) configured to output a drive signal (signals VHO and VLO) to operate the power supply circuit in a normal mode (see [0051] of Chen ’604 “First when the switching power supply apparatus operates in a normal mode, the control circuit 23 outputs a low(L)-level burst operation signal bur_en.”), and output the drive signal to operate the power supply circuit in a burst mode (burst operation in the standby mode, in which the load is light; see [0056] of Chen ’604 “With burst operation in the standby mode the control circuit 23 outputs a high(H)-level burst operation signal bur_en.”; see [0068] of Chen ’604 “A load is light in the standby mode.”); and the drive signal output circuit enters a first state (soft start) of outputting the drive signal to gradually increase an ON period of each of the first transistor and the second transistor (see [0067] of Chen ’604 “With a soft start control is exercised so that as the voltage VCS rises, a switching frequency of the oscillation circuit 22 will become lower.”), in response to the feedback voltage exceeding the first voltage (see [0068] of Chen ’604 “When the voltage VFB at the FB terminal exceeds the threshold voltage Vfbss, an output of the hysteresis comparator COMP3 becomes an L level, an output of the AND circuit AND1 becomes an L level, and an output of the inverter circuit INV4 becomes an H level.”; see [0068] of Chen ’604 “As a result, charging the capacitor C4 by the constant-current source Ichg is begun, the voltage VCS at the CS terminal begins to rise, and a soft start is begun.”), and enters a second state (soft end) of outputting the drive signal to gradually reduce the ON period of each of the first transistor and the second transistor (see [0067] of Chen ’604 “With a soft end control is exercised so that as the voltage VCS falls, a switching frequency of the oscillation circuit 22 will become higher.”), in response to the feedback voltage dropping below the second voltage (see [0070] of Chen ’604 “When the voltage VFB falls below the threshold voltage Vfbse, an output of the hysteresis comparator COMP3 becomes an H level, an output of the AND circuit AND1 becomes an H level, and an output of the inverter circuit INV4 becomes an L level.”; see [0070] of Chen ’604 “As a result, discharging the capacitor C4 by the constant-current source Idchg is begun and the voltage VCS at the CS terminal begins to fall.”).
Chen ’604 does not disclose a first adjustment circuit configured to adjust a level of the first voltage, and a drive signal output circuit configured to output a drive signal to operate the power supply circuit in a normal mode, in response to a state of a load of the power supply circuit entering a heavy-load state, and output the drive signal to operate the power supply circuit in a burst mode, in response to the state of the load entering a light-load state.
However, Chen ’888 teaches (see Fig. 1 and Fig. 2) a first adjustment circuit (burst-voltage setting circuit 113) configured to adjust a level of the first voltage (burst voltage VBST, which comparator 114 compares with feedback voltage VFB) (see [0018] of Chen ’888 “Burst-voltage setting circuit 113 electrically connects to setting pin BSTS, and detects the resistance of external resistor RST to generate burst voltage VBST.”; see [0019] of Chen ’888 “Comparator 114 compares feedback voltage VFB with burst voltage VBST.”), and a drive signal output circuit (ON-time generator 110, burst-mode controller 112, logic 116, and gate drivers 118 and 120) configured to output a drive signal (signals SH and SL) to operate the power supply circuit (LLC resonant converter 100) in a normal mode (non-burst mode), in response to a state of a load (load 104) of the power supply circuit entering a heavy-load state (see [0019] of Chen ’888 “When feedback voltage VFB exceeds burst voltage VBST, multiplexer 122 outputs feedback voltage VFB, and power controller 102 operates LLC resonant converter 100 in a non-burst mode, where only work time WK exists and break time BRK disappears.”; see [0015] of Chen ’888 “From another point of view, if output voltage VOUT is about the same as target voltage VTRGT, the lighter load 104 the lower feedback voltage VFB.”), and output the drive signal to operate the power supply circuit in a burst mode, in response to the state of the load entering a light-load state (see [0012] of Chen ’888 “According to embodiments of the invention, an LLC resonant converter operates in a burst mode when its load is light or non-existent.”; see [0019] of Chen ’888 “Simply speaking, when feedback voltage VFB is below burst voltage VBST, multiplexer 122 outputs burst voltage VBST, and power controller 102 operates LLC resonant converter 100 in a burst mode, where break time BRK and alternates with work time WK.”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the power supply circuit of Chen ’604 to include a first adjustment circuit configured to adjust a level of the first voltage, and a drive signal output circuit configured to output a drive signal to operate the power supply circuit in a normal mode, in response to a state of a load of the power supply circuit entering a heavy-load state, and output the drive signal to operate the power supply circuit in a burst mode, in response to the state of the load entering a light-load state, as taught by Chen ’888, because it can help allow the feedback voltage threshold, which determines the load at which the power supply circuit operates in the burst mode, to be selected for each application with an external resistor (see [0036] of Chen ’888 “A system engineer could select external resistor RST to determine the load threshold which determines the quantity of load 104 for LLC resonant converter 100 to operate in a burst mode.”), and help reduce switching losses by operating the power supply circuit in the burst mode when the load is light (see [0034] of Chen ’888 “The introduction of break time can reduce switching losses of high-side and low-side switches HS and LS, improving power conversion efficiency.”).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Chen ’604 in view of Chen ’888, and further in view of Lalithambika et al. (US Patent Application Publication US 2008/0143422 A1, hereinafter “Lalithambika”).
Regarding claim 9, Chen ’604 does not disclose further comprising: a setting circuit configured to receive first data indicating the level of the first voltage, wherein the first adjustment circuit adjusts the level of the first voltage, based on the first data.
However, Lalithambika teaches (see Fig. 1b and Fig. 2) a setting circuit (Programming Through Leads (PTL) block 110) configured to receive first data (serial data bits provided through the FB pin) indicating the level of the first voltage (a trimmed voltage threshold of the power supply controller integrated circuit 100) (see [0045] of Lalithambika “The FB pin provides data, clock and control signals for the PTL block 110 to enable programming and diagnostics.”; see [0007] of Lalithambika “The first shared connection enables a plurality of serial data bits to be provided to the IC for programming the trimming circuitry, and these are preferably stored in a memory such as a shift register so that the second shared connection can then be used to permanently program the stored data bits into the trimming circuitry substantially simultaneously, for example by blowing fuses or anti-fuses.”; see [0013] of Lalithambika “The programming may define one or more trimmed parameters and/or may define one or more functions of the IC, for example an under or over voltage threshold, a current limit, a switch frequency, a temperature limit (thermal shutdown function) and the like.”), wherein the first adjustment circuit (controller 104, which receives the programmed data) adjusts the level of the first voltage, based on the first data (see [0048] of Lalithambika “Continuing to refer to FIG. 1b, the programmed data in the fuses (or anti-fuses) is provided to the controller by a set of parallel outputs Q0-Qn from the PTL block 110 to the controller; this data is also able to be provided by the PTL block 110 in a serial form from an output Shiftn, for output using the power switch 102 for diagnostic purposes.”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the switching control circuit of Chen ’604 to further comprise a setting circuit configured to receive first data indicating the level of the first voltage, wherein the first adjustment circuit adjusts the level of the first voltage, based on the first data, as taught by Lalithambika, because it can help allow the level of the first voltage to be trimmed after the integrated circuit is packaged (see [0070] of Lalithambika “Among other things this enables parameters of the IC to be trimmed after packaging, which facilitates compensating for shifts in such parameters during packaging.”).
Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Chen ’604 in view of Chen ’888 and Lalithambika, and further in view of Texas Instruments (“Migrating to UCC25640x from UCC25630x,” Application Report SLUA966A, Texas Instruments, May 2019, revised December 2019, hereinafter “SLUA966A”).
Regarding claim 10, Chen ’604 does not disclose further comprising: a second adjustment circuit configured to adjust a level of the second voltage.
However, SLUA966A teaches (see Fig. 5) a second adjustment circuit (circuitry of the UCC25640x that programs the burst threshold ratio from the voltage at the BW pin) configured to adjust a level of the second voltage (burst mode entry threshold, set relative to the burst mode exit threshold by the BMT LOW/HIGH RATIO of Table 4) (see p. 7 of SLUA966A “BW serves as a dual purpose pin for the UCC25640x functioning as an output overvoltage detection pin as well as programming the threshold between burst mode entry threshold and burst mode exit threshold.”; see p. 7 of SLUA966A “A 54-µA current source is fed to the pin and the resulting voltage programs the burst threshold ratio during the start-up phase.”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the switching control circuit of Chen ’604 to further comprise a second adjustment circuit configured to adjust a level of the second voltage, as taught by SLUA966A, because it can help provide an adjustable hysteresis between the first voltage and the second voltage (see p. 2 of SLUA966A “User adjustable burst mode hysteresis”).
Regarding claim 11, Chen ’604 does not disclose wherein the setting circuit receives second data indicating the level of the second voltage, and the second adjustment circuit adjusts the level of the second voltage, based on the second data.
However, Lalithambika teaches (see Fig. 1b and Fig. 2) wherein the setting circuit (PTL block 110) receives second data (additional serial data bits, which are output as the parallel outputs Q0-Qn) indicating the level of the second voltage (a further one of the trimmed parameters) (see [0007] of Lalithambika “The first shared connection enables a plurality of serial data bits to be provided to the IC for programming the trimming circuitry, and these are preferably stored in a memory such as a shift register so that the second shared connection can then be used to permanently program the stored data bits into the trimming circuitry substantially simultaneously, for example by blowing fuses or anti-fuses.”; see [0070] of Lalithambika “Broadly speaking we have described techniques for using the low voltage pins of an integrated power supply controller for programming a trimming circuit to define one or more trimmed parameters or functions of the IC.”), and the second adjustment circuit (controller 104) adjusts the level of the second voltage, based on the second data (see [0048] of Lalithambika “Continuing to refer to FIG. 1b, the programmed data in the fuses (or anti-fuses) is provided to the controller by a set of parallel outputs Q0-Qn from the PTL block 110 to the controller; this data is also able to be provided by the PTL block 110 in a serial form from an output Shiftn, for output using the power switch 102 for diagnostic purposes.”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the switching control circuit of Chen ’604 wherein the setting circuit receives second data indicating the level of the second voltage, and the second adjustment circuit adjusts the level of the second voltage, based on the second data, as taught by Lalithambika, because it can help allow the level of the second voltage to be trimmed after the integrated circuit is packaged (see [0070] of Lalithambika “Among other things this enables parameters of the IC to be trimmed after packaging, which facilitates compensating for shifts in such parameters during packaging.”).
Claims 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Chen ’604 in view of Chen ’888, and further in view of SLUA966A.
Regarding claim 13, Chen ’604 does not disclose further comprising a second adjustment circuit configured to adjust a level of the second voltage.
However, SLUA966A teaches (see Fig. 5) a second adjustment circuit (circuitry of the UCC25640x that programs the burst threshold ratio from the voltage at the BW pin) configured to adjust a level of the second voltage (burst mode entry threshold, set relative to the burst mode exit threshold by the BMT LOW/HIGH RATIO of Table 4) (see p. 7 of SLUA966A “BW serves as a dual purpose pin for the UCC25640x functioning as an output overvoltage detection pin as well as programming the threshold between burst mode entry threshold and burst mode exit threshold.”; see p. 7 of SLUA966A “A 54-µA current source is fed to the pin and the resulting voltage programs the burst threshold ratio during the start-up phase.”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the switching control circuit of Chen ’604 to further comprise a second adjustment circuit configured to adjust a level of the second voltage, as taught by SLUA966A, because it can help provide an adjustable hysteresis between the first voltage and the second voltage (see p. 2 of SLUA966A “User adjustable burst mode hysteresis”).
Regarding claim 14, Chen ’604 does not disclose wherein the second adjustment circuit adjusts the level of the second voltage, based on a voltage of the resistor.
However, SLUA966A teaches (see Fig. 5 and Table 4) wherein the second adjustment circuit (circuitry of the UCC25640x that programs the burst threshold ratio) adjusts the level of the second voltage (burst mode entry threshold, which is set as the programmed ratio of the burst mode exit threshold), based on a voltage of the resistor (the burst mode exit threshold, to which the ratio is applied, is programmed through the external resistor divider of the resistors R14 and R15 at the LL/SS pin, and the ratio is programmed by the voltage produced by the 54-µA current source across the resistors R17 and R18 at the BW pin) (see p. 7 of SLUA966A “BMT LOW/HIGH RATIO”; see p. 8 of SLUA966A “BW upper resistor value is determined by setting the burst mode threshold entry and exit ratio to 0.6 (User Option 5) in the design calculator.”; see p. 6 of SLUA966A “Both the precharge voltage and the burst mode threshold are programmed through an external resistor divider connected from RVCC to LL/SS.”; see p. 8 of SLUA966A “LL/SS upper resistor value is determined by setting desired burst mode threshold for exit equal to 1.2 V in the design calculator.”; see p. 7 of SLUA966A “A 54-µA current source is fed to the pin and the resulting voltage programs the burst threshold ratio during the start-up phase.”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the switching control circuit of Chen ’604 wherein the second adjustment circuit adjusts the level of the second voltage, based on a voltage of the resistor, as taught by SLUA966A, because it can help set the second voltage as a selected ratio of the first voltage, so that the hysteresis between the first voltage and the second voltage remains user adjustable when the first voltage is set with the resistor (see p. 2 of SLUA966A “User adjustable burst mode hysteresis”).
Examiner’s Note: In the combination, the level of the first voltage is adjusted based on the voltage of the external resistor RST connected to the setting pin BSTS (see the rejection of claim 12). Because SLUA966A sets the burst mode entry threshold as a ratio of the burst mode exit threshold, the second voltage set as such a ratio of the first voltage changes with the voltage of the resistor RST. Accordingly, the second adjustment circuit adjusts the level of the second voltage based on the voltage of the same resistor recited in claim 12.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Chen ’604 in view of Chen ’888, and further in view of Kikuchi et al. (US Patent Application Publication US 2020/0169160 A1, hereinafter “Kikuchi”).
Regarding claim 15, Chen ’604 does not disclose further comprising a detection circuit configured to detect a resonant current flowing through the resonant circuit, wherein the drive signal output circuit outputs the drive signal, based on a result of detection of the detection circuit and the feedback voltage, when the power supply circuit is operating in the normal mode.
However, Kikuchi teaches (see Fig. 1, Fig. 2, and Fig. 16) a detection circuit (capacitor C3 and resistor R6) configured to detect a resonant current flowing through the resonant circuit (primary winding Np and resonant capacitor Cr) (see [0069] of Kikuchi “At the ILLC terminal, a resonant current detection signal VIS obtained by converting a resonant current into a voltage signal appears.”), wherein the drive signal output circuit (off-threshold value generation circuit 21, feedback current summing circuit 22, high-side comparator 24, low-side comparator 25, and switching controller 27) outputs the drive signal (gate driving signals GH and GL), based on a result of detection of the detection circuit (resonant current detection signal VIS) and the feedback voltage (feedback voltage Vfb) (see [0065] of Kikuchi “The high-side and low-side switching elements Q1 and Q2 are turned on and off complementarily by gate driving signals GH and GL respectively.”; see [0080] of Kikuchi “The off-threshold value generation circuit 21, based on the feedback voltage Vfb appearing at the FB terminal, generates a high-side off-threshold value VTHH and a low-side off-threshold value VTHL.”; see [0080] of Kikuchi “The feedback current summing circuit 22 generates a high-side off-threshold value VTHH′ by adding the resonant current detection signal VIS appearing at the ILLC terminal to the high-side off-threshold value VTHH, and generates a low-side off-threshold value VTHL′ by adding the resonant current detection signal VIS to the low-side off-threshold value VTHL.”; see [0083] of Kikuchi “With such a feedback configuration, the off-timing of the switching elements Q1 and Q2 is determined, and the output voltage Vout is controlled so as to remain equal to the target value.”), when the power supply circuit is operating in the normal mode (continuous switching operation under a heavy load; see [0160] of Kikuchi “FIG. 16 is a timing chart showing the waveforms of relevant signals when the load of the LLC resonant converter 52 is heavy.”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the switching control circuit of Chen ’604 to further comprise a detection circuit configured to detect a resonant current flowing through the resonant circuit, wherein the drive signal output circuit outputs the drive signal, based on a result of detection of the detection circuit and the feedback voltage, when the power supply circuit is operating in the normal mode, as taught by Kikuchi, because it can help enhance the load response of the power supply circuit (see [0083] of Kikuchi “In particular, in this embodiment, the feedback path includes information on the resonant current, and this enhances the load response of the LLC resonant converter 52 and makes phase compensation designing easy.”).
Allowable Subject Matter
Claims 2 and 3 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 2, none of the cited prior art alone or in combination disclose or teach the claimed inventions in which “wherein the drive signal output circuit is further configured to output the drive signal to operate the power supply circuit in the normal mode, in response to the feedback voltage reaching a third voltage, and output the drive signal to operate the power supply circuit in the burst mode, in response to the feedback voltage reaching a fourth voltage lower than the third voltage; and the first voltage is lower than the fourth voltage.”.
The closest prior art, Chen ’604, begins the soft start and the soft end when the feedback voltage VFB crosses the threshold voltages Vfbss and Vfbse (see [0068] of Chen ’604 “When the voltage VFB at the FB terminal exceeds the threshold voltage Vfbss, an output of the hysteresis comparator COMP3 becomes an L level, an output of the AND circuit AND1 becomes an L level, and an output of the inverter circuit INV4 becomes an H level.”; see [0070] of Chen ’604 “When the voltage VFB falls below the threshold voltage Vfbse, an output of the hysteresis comparator COMP3 becomes an H level, an output of the AND circuit AND1 becomes an H level, and an output of the inverter circuit INV4 becomes an L level.”), but selects the normal mode and the burst operation with the burst operation signal bur_en of the control circuit 23 (see [0056] of Chen ’604 “With burst operation in the standby mode the control circuit 23 outputs a high(H)-level burst operation signal bur_en.”), and does not transition between the modes at a third voltage and a fourth voltage of the feedback voltage. Chen ’888 switches between the burst mode and the non-burst mode at a single burst voltage VBST (see [0019] of Chen ’888 “Comparator 114 compares feedback voltage VFB with burst voltage VBST.”), and SLUA966A programs burst mode entry and exit thresholds (see p. 7 of SLUA966A “BW serves as a dual purpose pin for the UCC25640x functioning as an output overvoltage detection pin as well as programming the threshold between burst mode entry threshold and burst mode exit threshold.”), but neither teaches that the first voltage, at which the gradual increase of the ON period is started, is lower than the fourth voltage, at which the burst mode is entered.
Claim 3 is objected to due to its dependency on claim 2.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2020/0169176 A1 discloses a burst controller of a resonance converter that switches from continuous control to burst control when a load detection signal obtained by shunting and averaging a resonant current becomes smaller than a first threshold.
US 2008/0030178 A1 discloses a switching regulator having an adjustment circuit that enables a user to set a burst threshold level and a hysteresis of the switching regulator when the switching regulator operates in a burst mode.
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/MONICA LEWIS/ Supervisory Patent Examiner, Art Unit 2838
/JYE-JUNE LEE/Examiner, Art Unit 2838
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