DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/19/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4-10, 12-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hanna (US 20230259304), in view of Kim (US 20190303041), further in view of Yoon (US 20160070483).
Regarding Claim 1, Hanna teaches
A method, comprising: receiving, from an application, a request associated with a memory device; (Hanna [0016] the host system 105 may include an application configured for communicating with the memory system 110 or a device therein. [0010] In some memory system, such as a managed NAND system or other managed flash device systems, the bandwidth and speed of access operations, such as sequential read operations… to store the data in the pattern (e.g., as part of a sequential write operation))
issuing a first command to the memory device via a memory controller, (Hanna [0010] the memory system may store the data in a buffer of the memory system prior to programming the data across the memory devices in the pattern. That is, the data may first be “staged” at the buffer of the memory system)
determining that the memory device is ready based on the status; (Hanna [0047] To process a write command received from the host system 205, the memory system controller 215 may first determine if the buffer 225 has sufficient available space to store the data associated with the command.)
and issuing a second command to the memory device via a memory controller to fulfill the request. (Hanna [0049] If the buffer 225 has sufficient space to store the write data, the interface 220 subsequently receives from the host system 205 the data associated with the write command, the interface 220 may transfer the data to the buffer 225 for temporary storage using the data path 250)
Hanna does not teach
polling the memory device for a status of the memory device, the status associated with a readiness of the memory device for the request;
However, Kim teaches
polling the memory device for a status of the memory device, the status associated with a readiness of the memory device for the request; (Kim [0088] the write data is transferred from the host 2000 to the buffer 1206 through the host interface. The term “polling” may mean a scheme in which one device (or program or firmware) periodically checks the status of another device (or program or firmware) for the purpose of avoiding collisions or processing synchronization, and then performs data processing, such as transmission or reception of data, when the checked status satisfies a predetermined condition.)
Hanna and Kim are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Hanna and Kim to modify the Hanna‘s system for memory system with read/write data staged in buffer with Kim’s teaching of polling buffer status. The motivation for doing so would be to proceed when (Kim [0088]) checked status satisfies a predetermined condition.
Hanna-Kim does not teach wherein the first command includes a command to allocate space on a buffer of the memory device or to move data from the memory device to the buffer;
However, Yoon teaches wherein the first command includes a command to allocate space on a buffer of the memory device or to move data from the memory device to the buffer; (Yoon [0033] Access commands 110 that can be issued by the host-side memory controller 104 to the device-side memory controller 106 include an activate command and precharge command. Also, access commands 110 can include read and write commands. [0034] The activate command is issued to the device-side memory controller 106 to cause the memory access control logic 210 of the device-side memory controller 106 to retrieve data of a row of memory cells in the memory 102 into a buffer (not shown) of the memory 102. Once data is retrieved into the buffer of the memory 102, the data in the buffer can be the target of a read operation or a write operation from the device-side memory controller 106.)
Hanna, Kim and Yoon are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Hanna, Kim and Yoon to modify the Hanna-Kim‘s NAND with Yoon’s teaching decoupled memory controllers are provided for accessing data in a memory using buffer. The motivation for doing so would be to have (Yoon [0015]) manage the timings of memory commands issued to the memory to satisfy various timing parameters.
Regarding Claim 2, Hanna, Kim and Yoon teach
The method of claim 1, wherein the memory controller includes a low-power double data rate (LPDDR) memory controller. (Hanna [0017] The host system 105 may be coupled with the memory system 110 via at least one physical host interface. Examples of a physical host interface may include a Low Power Double Data Rate (LPDDR) interface)
Regarding Claim 4, Hanna, Kim and Yoon teach
The method of claim 1, wherein the request includes a write request. (Hanna [0006] a system that supports techniques to perform a write operation)
Regarding Claim 5, Hanna, Kim and Yoon teach
The method of claim 4, wherein the status of the memory device is based on availability of space in a buffer of the memory device. (Hanna [0047] To process a write command received from the host system 205, the memory system controller 215 may first determine if the buffer 225 has sufficient available space to store the data associated with the command.)
Regarding Claim 6, Hanna, Kim and Yoon teach
Hanna does not teach but Kim teaches reserving an amount of space in the buffer for the application. (Kim [0091] Until an available space is secured in the buffer 1206 through the above procedure, the first firmware FW1 may maintain the busy signal Busy in an activate state. When the flush of data is performed and the available space of the buffer 1206 is secured)
Hanna and Kim are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Hanna and Kim to modify the Hanna‘s system for memory system with read/write data staged in buffer with Kim’s teaching of polling buffer status. The motivation for doing so would be to proceed when (Kim [0088]) checked status satisfies a predetermined condition.
Regarding Claim 7, Hanna, Kim and Yoon teach
The method of claim 1, wherein the request includes a read request. (Hanna [0052] To process a read command received from the host system 205, the memory system controller 215 may again first determine if the buffer 225 has sufficient available space to store the data associated with the command.)
Regarding Claim 8, Hanna, Kim and Yoon teach
Hanna teaches data associated with the request in a buffer of the memory device (Hanna [0052] To process a read command received from the host system 205, the memory system controller 215 may again first determine if the buffer 225 has sufficient available space to store the data associated with the command.)
Hanna does not teach but Kim teaches wherein the status of the memory device is based on availability of (Kim [0088] The term “polling” may mean a scheme in which one device (or program or firmware) periodically checks the status of another device (or program or firmware) for the purpose of avoiding collisions or processing synchronization, and then performs data processing, such as transmission or reception of data, when the checked status satisfies a predetermined condition.)
Hanna and Kim are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Hanna and Kim to modify the Hanna‘s system for memory system with read/write data staged in buffer with Kim’s teaching of polling buffer status. The motivation for doing so would be to proceed when (Kim [0088]) checked status satisfies a predetermined condition.
Regarding Claim 9, Hanna teaches
A system, comprising: a host comprising: a memory controller; a processing circuit; and memory connected to the processing circuit, the memory storing instructions that, when executed by the processing circuit, causes performance of a method, (Hanna [0015] The system 100 may be included in a computing device that includes memory and a processing device.)
the method comprising: receiving, from an application, a request associated with a memory device; (Hanna [0016] the host system 105 may include an application configured for communicating with the memory system 110 or a device therein. [0010] In some memory system, such as a managed NAND system or other managed flash device systems, the bandwidth and speed of access operations, such as sequential read operations… to store the data in the pattern (e.g., as part of a sequential write operation))
issuing a first command to the memory device via a memory controller, (Hanna [0010] the memory system may store the data in a buffer of the memory system prior to programming the data across the memory devices in the pattern. That is, the data may first be “staged” at the buffer of the memory system)
determining that the memory device is ready based on the status; (Hanna [0047] To process a write command received from the host system 205, the memory system controller 215 may first determine if the buffer 225 has sufficient available space to store the data associated with the command.)
and issuing a second command to the memory device via a memory controller to fulfill the request. (Hanna [0049] If the buffer 225 has sufficient space to store the write data, the interface 220 subsequently receives from the host system 205 the data associated with the write command, the interface 220 may transfer the data to the buffer 225 for temporary storage using the data path 250)
Hanna does not teach
polling the memory device for a status of the memory device, the status associated with a readiness of the memory device for the request;
However, Kim teaches
polling the memory device for a status of the memory device, the status associated with a readiness of the memory device for the request; (Kim [0088] the write data is transferred from the host 2000 to the buffer 1206 through the host interface. The term “polling” may mean a scheme in which one device (or program or firmware) periodically checks the status of another device (or program or firmware) for the purpose of avoiding collisions or processing synchronization, and then performs data processing, such as transmission or reception of data, when the checked status satisfies a predetermined condition.)
Hanna and Kim are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Hanna and Kim to modify the Hanna‘s system for memory system with read/write data staged in buffer with Kim’s teaching of polling buffer status. The motivation for doing so would be to proceed when (Kim [0088]) checked status satisfies a predetermined condition.
Hanna-Kim does not teach wherein the first command includes a command to allocate space on a buffer of the memory device or to move data from the memory device to the buffer;
However, Yoon teaches wherein the first command includes a command to allocate space on a buffer of the memory device or to move data from the memory device to the buffer; (Yoon [0033] Access commands 110 that can be issued by the host-side memory controller 104 to the device-side memory controller 106 include an activate command and precharge command. Also, access commands 110 can include read and write commands. [0034] The activate command is issued to the device-side memory controller 106 to cause the memory access control logic 210 of the device-side memory controller 106 to retrieve data of a row of memory cells in the memory 102 into a buffer (not shown) of the memory 102. Once data is retrieved into the buffer of the memory 102, the data in the buffer can be the target of a read operation or a write operation from the device-side memory controller 106.)
Hanna, Kim and Yoon are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Hanna, Kim and Yoon to modify the Hanna-Kim‘s NAND with Yoon’s teaching decoupled memory controllers are provided for accessing data in a memory using buffer. The motivation for doing so would be to have (Yoon [0015]) manage the timings of memory commands issued to the memory to satisfy various timing parameters.
Regarding Claim 10, Hanna, Kim and Yoon teach
The system of claim 9, wherein the memory controller includes a low-power double data rate (LPDDR) memory controller. (Hanna [0017] The host system 105 may be coupled with the memory system 110 via at least one physical host interface. Examples of a physical host interface may include a Low Power Double Data Rate (LPDDR) interface)
Regarding Claim 12, Hanna, Kim and Yoon teach
The system of claim 9, wherein the request is associated with a write request. (Hanna [0006] a system that supports techniques to perform a write operation)
Regarding Claim 13, Hanna, Kim and Yoon teach
The system of claim 12, wherein the status of the memory device is based on availability of space in a buffer of the memory device. (Hanna [0047] To process a write command received from the host system 205, the memory system controller 215 may first determine if the buffer 225 has sufficient available space to store the data associated with the command.)
Regarding Claim 14, Hanna, Kim and Yoon teach
Hanna does not teach but Kim teaches reserving an amount of space in the buffer for the application. (Kim [0091] Until an available space is secured in the buffer 1206 through the above procedure, the first firmware FW1 may maintain the busy signal Busy in an activate state. When the flush of data is performed and the available space of the buffer 1206 is secured)
Hanna and Kim are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Hanna and Kim to modify the Hanna‘s system for memory system with read/write data staged in buffer with Kim’s teaching of polling buffer status. The motivation for doing so would be to proceed when (Kim [0088]) checked status satisfies a predetermined condition.
Regarding Claim 15, Hanna, Kim and Yoon teach
The method of claim 1, wherein the request is a read request. (Hanna [0052] To process a read command received from the host system 205, the memory system controller 215 may again first determine if the buffer 225 has sufficient available space to store the data associated with the command.)
Regarding Claim 16, Hanna, Kim and Yoon teach
Hanna teaches data associated with the request in a buffer of the memory device (Hanna [0052] To process a read command received from the host system 205, the memory system controller 215 may again first determine if the buffer 225 has sufficient available space to store the data associated with the command.)
Hanna does not teach but Kim teaches wherein the status of the memory device is based on availability of (Kim [0088] The term “polling” may mean a scheme in which one device (or program or firmware) periodically checks the status of another device (or program or firmware) for the purpose of avoiding collisions or processing synchronization, and then performs data processing, such as transmission or reception of data, when the checked status satisfies a predetermined condition.)
Hanna and Kim are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Hanna and Kim to modify the Hanna‘s system for memory system with read/write data staged in buffer with Kim’s teaching of polling buffer status. The motivation for doing so would be to proceed when (Kim [0088]) checked status satisfies a predetermined condition.
Claim(s) 3, 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hanna (US 20230259304), in view of Kim (US 20190303041), further in view of Yoon (US 20160070483), further in view of Chinnakkonda (US 20170160956).
Regarding Claim 3, Hanna, Kim and Yoon teach
Hanna teaches wherein the memory device includes a High Bandwidth Flash NAND memory (Hanna [0016] the host system 105 may include an application configured for communicating with the memory system 110 or a device therein. [0010] In some memory system, such as a managed NAND system)
and a front-end controller configured to control the High Bandwidth Flash NAND memory (Hanna [0037] The memory system 210 may additionally include an interface 220 for communication with the host system 205 and a buffer 225 for temporary storage of data being transferred between the host system 205 and the memory devices 240.) (i.e., interface 220 is the front-end controller/interface)
based on commands from the LPDDR memory controller. (Hanna [0017] The host system 105 may be coupled with the memory system 110 via at least one physical host interface. Examples of a physical host interface may include a Low Power Double Data Rate (LPDDR) interface)
Hanna-Kim- Yoon does not teach a High Bandwidth Flash NAND
However, Chinnakkonda teaches a High Bandwidth Flash NAND (Chinnakkonda [0012] providing high-bandwidth, non-volatile data storage for use with processor ICs arranged in stacked, high-density configurations, for example, in three-dimensional integrated circuit (3-D IC) structures [0013] the term “non-volatile memory” is used interchangeably herein with the term “flash memory”)
Hanna, Kim, Yoon and Chinnakkonda are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Hanna, Kim, Yoon and Chinnakkonda to modify the Hanna-Kim- Yoon’s NAND with Chinnakkonda‘s teaching high bandwidth flash memory. The motivation for doing so would be to have (Chinnakkonda [0012]) high-performance computing.
Regarding Claim 11, Hanna, Kim and Yoon teach
Hanna teaches wherein the memory device includes a High Bandwidth Flash NAND memory (Hanna [0016] the host system 105 may include an application configured for communicating with the memory system 110 or a device therein. [0010] In some memory system, such as a managed NAND system)
and a front-end controller configured to control the High Bandwidth Flash NAND memory (Hanna [0037] The memory system 210 may additionally include an interface 220 for communication with the host system 205 and a buffer 225 for temporary storage of data being transferred between the host system 205 and the memory devices 240.) (i.e., interface 220 is the front-end controller/interface)
based on commands from the LPDDR memory controller. (Hanna [0017] The host system 105 may be coupled with the memory system 110 via at least one physical host interface. Examples of a physical host interface may include a Low Power Double Data Rate (LPDDR) interface)
Hanna-Kim- Yoon does not teach a High Bandwidth Flash NAND
However, Chinnakkonda teaches a High Bandwidth Flash NAND (Chinnakkonda [0012] providing high-bandwidth, non-volatile data storage for use with processor ICs arranged in stacked, high-density configurations, for example, in three-dimensional integrated circuit (3-D IC) structures [0013] the term “non-volatile memory” is used interchangeably herein with the term “flash memory”)
Hanna, Kim, Yoon and Chinnakkonda are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Hanna, Kim, Yoon and Chinnakkonda to modify the Hanna-Kim- Yoon’s NAND with Chinnakkonda‘s teaching high bandwidth flash memory. The motivation for doing so would be to have (Chinnakkonda [0012]) high-performance computing.
Claim(s) 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hanna (US 20230259304), in view of Kim (US 20190303041), further in view of Chinnakkonda (US 20170160956), further in view of Yoon (US 20160070483).
Regarding Claim 17, Hanna teaches
A memory device, comprising: a High Bandwidth NAND (HBN); (Hanna [0016] the host system 105 may include an application configured for communicating with the memory system 110 or a device therein. [0010] In some memory system, such as a managed NAND system)
and a front-end controller configured to control access to the HBN, the front-end controller comprising: a buffer; (Hanna [0037] The memory system 210 may additionally include an interface 220 for communication with the host system 205 and a buffer 225 for temporary storage of data being transferred between the host system 205 and the memory devices 240.) (i.e., interface 220 is the front-end controller/interface)
a processing circuit; and memory connected to the processing circuit, the memory storing instructions that, when executed by the processing circuit, causes performance of a method, the method comprising: receiving a first command from a memory controller of a host device; (Hanna [0016] the host system 105 may include an application configured for communicating with the memory system 110 or a device therein. [0010] In some memory system, such as a managed NAND system or other managed flash device systems, the bandwidth and speed of access operations, such as sequential read operations… to store the data in the pattern (e.g., as part of a sequential write operation) … the memory system may store the data in a buffer of the memory system prior to programming the data across the memory devices in the pattern. That is, the data may first be “staged” at the buffer of the memory system))
determine that a status of the buffer satisfies a condition associated with the first command; (Hanna [0047] To process a write command received from the host system 205, the memory system controller 215 may first determine if the buffer 225 has sufficient available space to store the data associated with the command.)
receive a second command from the memory controller; and execute an action with respect to the buffer based on the second command. (Hanna [0049] If the buffer 225 has sufficient space to store the write data, the interface 220 subsequently receives from the host system 205 the data associated with the write command, the interface 220 may transfer the data to the buffer 225 for temporary storage using the data path 250)
Hanna does not teach
transmit the status of the buffer to the memory controller;
However, Kim teaches
transmit the status of the buffer to the memory controller; (Kim [0088] the write data is transferred from the host 2000 to the buffer 1206 through the host interface. The term “polling” may mean a scheme in which one device (or program or firmware) periodically checks the status of another device (or program or firmware) for the purpose of avoiding collisions or processing synchronization, and then performs data processing, such as transmission or reception of data, when the checked status satisfies a predetermined condition. [0090] the busy signal Busy may be activated to perform the internal operation of the memory controller …the first firmware FW1 checks the status of the buffer 1206, and then determines whether it is possible to store additional data in the buffer.)
Hanna and Kim are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Hanna and Kim to modify the Hanna‘s system for memory system with read/write data staged in buffer with Kim’s teaching of polling buffer status. The motivation for doing so would be to proceed when (Kim [0088]) checked status satisfies a predetermined condition.
Hanna-Kim teaches NAND but Hanna-Kim does not teach a High Bandwidth NAND (HBN)
However, Chinnakkonda teaches a High Bandwidth NAND (HBN) (Chinnakkonda [0012] providing high-bandwidth, non-volatile data storage for use with processor ICs arranged in stacked, high-density configurations, for example, in three-dimensional integrated circuit (3-D IC) structures [0013] the term “non-volatile memory” is used interchangeably herein with the term “flash memory”)
Hanna, Kim and Chinnakkonda are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Hanna, Kim and Chinnakkonda to modify the Hanna-Kim‘s NAND with Kim’s teaching of high bandwidth flash memory. The motivation for doing so would be to have (Chinnakkonda [0012]) high-performance computing.
Hanna-Kim-Chinnakkonda does not teach wherein the first command includes a command to allocate space on the buffer or to move data from the HBN to the buffer;
However, Yoon teaches wherein the first command includes a command to allocate space on a buffer of the memory device or to move data from the [memory device] to the buffer; (Yoon [0033] Access commands 110 that can be issued by the host-side memory controller 104 to the device-side memory controller 106 include an activate command and precharge command. Also, access commands 110 can include read and write commands. [0034] The activate command is issued to the device-side memory controller 106 to cause the memory access control logic 210 of the device-side memory controller 106 to retrieve data of a row of memory cells in the memory 102 into a buffer (not shown) of the memory 102. Once data is retrieved into the buffer of the memory 102, the data in the buffer can be the target of a read operation or a write operation from the device-side memory controller 106.)
Hanna, Kim, Chinnakkonda and Yoon are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Hanna, Kim, Chinnakkonda and Yoon to modify the Hanna-Kim- Chinnakkonda‘s NAND with Yoon’s teaching decoupled memory controllers are provided for accessing data in a memory using buffer. The motivation for doing so would be to have (Yoon [0015]) manage the timings of memory commands issued to the memory to satisfy various timing parameters.
Regarding Claim 18, Hanna, Kim, Chinnakkonda and Yoon teach
Hanna teaches wherein the second command is a read request for data stored in the HBN (Hanna [0052] To process a read command received from the host system 205, the memory system controller 215 may again first determine if the buffer 225 has sufficient available space to store the data associated with the command. [0053] if the buffer 225 has sufficient space to store the read data, the memory system controller 215 may cause the storage controller 230 to retrieve the data associated with the read command from a memory device 240 and store the data in the buffer 225 for temporary storage using the data path)
Hanna does not teach but Kim teaches and wherein the condition includes the data being in the buffer. (Kim [0088] The term “polling” may mean a scheme in which one device (or program or firmware) periodically checks the status of another device (or program or firmware) for the purpose of avoiding collisions or processing synchronization, and then performs data processing, such as transmission or reception of data, when the checked status satisfies a predetermined condition.)
Hanna and Kim are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Hanna and Kim to modify the Hanna‘s system for memory system with read/write data staged in buffer with Kim’s teaching of polling buffer status. The motivation for doing so would be to proceed when (Kim [0088]) checked status satisfies a predetermined condition.
Hanna-Kim does not teach but Chinnakkonda teaches HBN (Chinnakkonda [0012] providing high-bandwidth, non-volatile data storage for use with processor ICs arranged in stacked, high-density configurations, for example, in three-dimensional integrated circuit (3-D IC) structures [0013] the term “non-volatile memory” is used interchangeably herein with the term “flash memory”)
Hanna, Kim and Chinnakkonda are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Hanna, Kim and Chinnakkonda to modify the Hanna-Kim‘s NAND with Kim’s teaching of high bandwidth flash memory. The motivation for doing so would be to have (Chinnakkonda [0012]) high-performance computing.
Regarding Claim 19, Hanna, Kim, Chinnakkonda and Yoon teach
Hanna-Kim teaches wherein the second command is a write request for data to be stored in the HBN, and wherein the condition includes the buffer having enough space available for the data. (Hanna [0047] To process a write command received from the host system 205, the memory system controller 215 may first determine if the buffer 225 has sufficient available space to store the data associated with the command. [0049] If the buffer 225 has sufficient space to store the write data, the interface 220 subsequently receives from the host system 205 the data associated with the write command, the interface 220 may transfer the data to the buffer 225 for temporary storage using the data path 250)
Hanna-Kim does not teach but Chinnakkonda teaches HBN (Chinnakkonda [0012] providing high-bandwidth, non-volatile data storage for use with processor ICs arranged in stacked, high-density configurations, for example, in three-dimensional integrated circuit (3-D IC) structures [0013] the term “non-volatile memory” is used interchangeably herein with the term “flash memory”)
Hanna, Kim and Chinnakkonda are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Hanna, Kim and Chinnakkonda to modify the Hanna-Kim‘s NAND with Kim’s teaching of high bandwidth flash memory. The motivation for doing so would be to have (Chinnakkonda [0012]) high-performance computing.
Regarding Claim 20, Hanna, Kim, Chinnakkonda and Yoon teach
Hanna does not teach but Kim teaches reserving an amount of space in the buffer for the data. (Kim [0091] Until an available space is secured in the buffer 1206 through the above procedure, the first firmware FW1 may maintain the busy signal Busy in an activate state. When the flush of data is performed and the available space of the buffer 1206 is secured)
Hanna and Kim are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Hanna and Kim to modify the Hanna‘s system for memory system with read/write data staged in buffer with Kim’s teaching of polling buffer status. The motivation for doing so would be to proceed when (Kim [0088]) checked status satisfies a predetermined condition.
Response to Arguments
Applicant's arguments filed 05/29/2026 have been fully considered but they are not persuasive.
Applicant argues that the cited references do not disclose amended limitations. The Office disagrees.
The amended limitations are addressed in new rejection based on the amendment.
First, for claim 1, specifically, Hanna teaches store data in buffer for memory access,
Kim teaches polling memory device status associated with readiness of memory device for the request,
Yoon teaches host-side memory controller and device-side memory controller and access commands from host-side memory controller move data from the memory device to the buffer for read or write operation.
The combination of Hanna, Kim and Yoon discloses the limitations of claim 1.
Next, for claim 9, 17, Applicant argues as similar to claim 1.
Applicant’s argument for dependent claims 2-8, 10-16 and 187-20 are based on their respective base independent claim 1, 9 and 17, which are addressed above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/WEI MA/Examiner, Art Unit 2135
/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135
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