Prosecution Insights
Last updated: October 02, 2026
Application No. 19/042,110

PROGRAMMABLE SWITCHING REGULATOR

Non-Final OA §102§103
Filed
Jan 31, 2025
Priority
Mar 28, 2024 — IN 202411025333
Examiner
NGUYEN, PHIL K
Art Unit
Tech Center
Assignee
HAMILTON SUNDSTRAND Corporation
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
1y 0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
453 granted / 549 resolved
+22.5% vs TC avg
Moderate +14% lift
Without
With
+14.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
19 currently pending
Career history
567
Total Applications
across all art units

Statute-Specific Performance

§101
7.3%
-32.7% vs TC avg
§103
52.7%
+12.7% vs TC avg
§102
19.9%
-20.1% vs TC avg
§112
12.0%
-28.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 549 resolved cases

Office Action

§102 §103
DETAILED ACTION Claims 1 – 20 are pending. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Objections Claims 13 and 15 are objected to because of the following informalities: Claim 13 has a typo error because it is listed as claim 2. Claim 15 has a typo error because it is listed as claim 3. Appropriate correction is required. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-3,8,10, 12-16, 19 and 20 are rejected under AIA 35 U.S.C. 102(a)(1) as being anticipated by Barrenscheen (US 20160233775 A1). Regarding claim 1, Barrenscheen discloses a voltage regulator [Fig. 2, power supply system 200] comprising: a pulse width modulation controller [primary side controller 220] configured to control an output voltage of a power supply [0007: the primary-side controller includes a primary-side switching controller configured to regulate a power applied to a primary winding in a transformer during a first period, and an input interface coupled to the primary-side switching controller]; and a programmable device [secondary side controller 240] configured to monitor the output voltage of the power supply [0008: the secondary-side controller is adapted to monitor a parameter of a secondary-side power system, and to generate a switching indication based on the parameter of the secondary-side power system][0024: the secondary-side controller 240 receives a measurement signal 231 corresponding to a parameter (e.g., output voltage, output current, etc.) of the power system fed by secondary winding 230], wherein the programmable device is configured to assume control of the output voltage of the power supply based on a comparison by the programmable device of the output voltage of the power supply to one or more criteria [0024: The secondary-side controller 240 then performs at least some control-loop processing on the measurement signal 231 to generate a switching indication signal 241, which is forwarded to the primary-side controller 220 via the isolating signal path 250][abstract: The switching indication signal may be any control signaling instruction that prompts the primary-side controller to regulate and/or modify the power applied to the primary winding]. Regarding claim 2, Barrenscheen discloses the voltage regulator of claim 1, wherein the one or more criteria comprises a threshold voltage [0038,0041: voltage threshold]. Regarding claim 3, Barrenscheen discloses the voltage regulator of claim 1, wherein the one or more criteria comprises a threshold voltage stability [0035: steady voltage]. Regarding claim 8, Barrenscheen discloses the voltage regulator of claim 1, further comprising a current sensing device configured to provide a sensed current associated with providing the output voltage, wherein the programmable device is configured to generate or modify a pulse width modulation signal associated with controlling the output voltage of the power supply, based on the sensed current [abstract][0006-0010]. Regarding claim 10, Barrenscheen discloses the voltage regulator of claim 1, wherein the programmable device is configured to refrain from controlling the output voltage of the power supply based on the comparison by the programmable device of the output voltage of the power supply to the one or more criteria [abstract][0006-0010]. Regarding claim 12, Barrenscheen discloses the voltage regulator of claim 1, further comprising a transformer configured to generate the output voltage based on an input voltage received at the voltage regulator, wherein: the pulse width modulation controller is associated with a primary side of the transformer; and the programmable device is associated with a secondary side of the transformer [abstract][0006-0010]. Regarding claim 14, Barrenscheen discloses the apparatus of claim 13, further comprising a control device configured to control one or more functions of the apparatus, wherein the programmable device is comprised in a portion of the control device [abstract] [0006-0010]. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 4-7,11,17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Barrenscheen (US 20160233775 A1) and in view of HARI (US 20200021197 A1). Regarding claim 4, Barrenscheen does not disclose wherein in association with the programmable device assuming control of the output voltage of the power supply, the programmable device is configured to: generate a second pulse width modulation signal synchronized with a first pulse width modulation signal generated by the pulse width modulation controller; and control the output voltage of the power supply based on the second pulse width modulation signal. Hari discloses wherein in association with the programmable device assuming control of the output voltage of the power supply, the programmable device is configured to: generate a second pulse width modulation signal synchronized with a first pulse width modulation signal generated by the pulse width modulation controller; and control the output voltage of the power supply based on the second pulse width modulation signal [0033: the gate driver 410 is designed and constructed to drive the gate 126 (FIG. 3) of the secondary FET 122 (FIG. 3) with proper voltages to make the secondary FET 122 (FIG. 3) conductive and non-conductive as part of synchronous operation of the secondary side 104 (FIG. 3) of the power converter 100 (FIG. 3)]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Barrenscheen and Hari together because they both directed to use both sides to control the output voltage. Hari’s disclosing of synchronizing the pulse signals between both sides would allow Barrenscheen to increase the device’s integrity by avoiding switching discontinuities and maintaining substantially continuous converter operation. Regarding claim 5, Hari discloses the voltage regulator of claim 4, wherein the second pulse width modulation signal and the first pulse width modulation signal are synchronized according to frequency, duty cycle, or both [0033]. Regarding claim 6, Hari discloses the voltage regulator of claim 1, wherein in association with the programmable device assuming control of the output voltage of the power supply, the programmable device is configured to: output a control signal to the pulse width modulation controller, wherein the pulse width modulation controller is configured to refrain from controlling the output voltage of the power supply, based on the control signal [0021-0026: non conductive state]. Regarding claim 7, Hari discloses the voltage regulator of claim 6, wherein: the pulse width modulation controller controlling the output voltage of the power supply is associated with an active state of the pulse width modulation controller; and the pulse width modulation controller refraining from controlling the output voltage of the power supply is associated with a standby state of the pulse width modulation controller [0021-0026]. Regarding claim 11, Hari discloses the voltage regulator of claim 10, wherein: the programmable device controlling the output voltage of the power supply is associated with an active state of the programmable device; and the programmable device refraining from controlling the output voltage of the power supply is associated with a standby state of the programmable device [0021-0026]. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Barrenscheen (US 20160233775 A1) and in view of Rajesh (US 20210091654 A1). Regarding claim 9, Barrenscheen does not disclose an analog-to-digital conversion circuit configured to generate a digital representation of the sensed current, wherein the programmable device is configured to generate or modify the pulse width modulation signal based on the digital representation. Rajesh discloses an analog-to-digital conversion circuit configured to generate a digital representation of the sensed current, wherein the programmable device is configured to generate or modify the pulse width modulation signal based on the digital representation [0063: USB-PD subsystem 820 may include: one or more analog-to-digital convertors (ADCs) for converting various analog signals to digital signals; an error amplifier (ERROR AMP) for controlling the power source voltage applied to the VBUS line per a PD contract; a current sense amplifier (CSA) and an over-voltage protection (OVP) circuits for providing over-current and over-voltage protection on the VBUS line with configurable thresholds and response time]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Barrenscheen and Rajesh together because they both directed to use both sides to control the output voltage. Rajesh’s disclosing of an analog-to-digital conversion circuit configured to generate a digital representation of the sensed current, wherein the programmable device is configured to generate or modify the pulse width modulation signal based on the digital representation would allow Barrenscheen to increase the device’s integrity by conveniently generating or modifying the pulse width modulation signal based on the digital output. Regarding claim 13, this claim is rejected for the same reasons as set forth in claim 1. Regarding claims 15 – 20, these claims are rejected for the same reasons as set forth in claims 1-4,6,8 and 10 above. Conclusion Examiner's note: Examiner has cited particular paragraphs and columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner (see MPEP § 2123). Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHIL K NGUYEN whose telephone number is (571)270-3356. The examiner can normally be reached 9:30 a.m - 5 p.m. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached at (571)270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PHIL K NGUYEN/Primary Examiner, Art Unit 2176
Read full office action

Prosecution Timeline

Jan 31, 2025
Application Filed
Sep 10, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
97%
With Interview (+14.2%)
2y 8m (~1y 0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 549 resolved cases by this examiner. Grant probability derived from career allowance rate.

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