DETAILED ACTION
This Office action is in response to the application filed on 31 January 2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 6-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Da Jiao et. al (US2018/0145607A1; hereafter “Da”).
-Regarding claim 1:
Da discloses:
A method of implementing a space vector pulse width modulation scheme comprising: mapping switching states for an n-phase, where n is an integer, multi-level inverter (Fig. 1; 106 three phase , three level inverter) onto a two-dimensional hexagonal space vector diagram (Fig. 2; space vector diagram); identifying redundant vectors in the space vector diagram and removing redundant vectors associated with a common mode voltage current contribution of more than a predetermined threshold (paragraph 0029; “preferred subset of switching states used to control the inverter 106 may be determined by selecting the switching states corresponding to the lowest common mode voltages and excluding the switching states corresponding to
the highest common mode voltages. In certain embodiments, the switching states used within the controller 160 to control the inverter 106 may be selected using a threshold of…”); identifying a location in the space vector diagram (paragraph 0037; “in FIG. 2 and trigonometrically calculating how to create the
reference vector Vref using vectors adjacent to as would Vref' be appreciated by one of ordinary skill in the art in view of this disclosure.”) of a voltage reference vector; identifying a sector of the space vector diagram (paragraph 0049; “Active balance control under the present invention may be achieved by sampling Vref'’s position to determine the sector in which the reference vector is located, creating one or more sets of switching signals based on that sector,) defined by four vectors within which the voltage reference vector is located; and determining duty cycles and switching states associated with the four vectors to synthesise the voltage reference vector (Fig. 501, paragraph 0037; “Specifically, the trigonometric calculations may produce angle and magnitude values characterizing the relationship between the reference vector Vref and the three
adjacent vectors. These angle and magnitude values then may be used to determine the dwell time for each of the switching states corresponding with the three adjacent vectors. The dwell time is the duration for which a particular
state is applied by the controller. “, and paragraph 0049;” A second example of these steps may be applied to sector 201, where the adjacent vectors comprise PON, PNN, and P-type small vector POO after elimination of higher voltage vector ONN. Because POO is the only small vector in the set comprising the
vectors adjacent to sector 201, the set may be used to create P-type sequences including those shown in FIGS. 501A and 501B.”).
-Regarding claim 6:
Da discloses:
The method of claim 1, further comprising determining switching sequence associated with the four vectors to synthesise the voltage reference vector (Fig. 501, paragraph 0037; “Specifically, the trigonometric calculations may produce angle and magnitude values characterizing the relationship between the reference vector Vref and the three adjacent vectors. These angle and magnitude values then may be used to determine the dwell time for each of the switching states corresponding with the three adjacent vectors. The dwell time is the duration for which a particular state is applied by the controller. “, and paragraph 0049;” A second example of these steps may be applied to sector 201, where the adjacent vectors comprise PON, PNN, and P-type small vector POO after elimination of higher voltage vector ONN. Because POO is the only small vector in the set comprising the vectors adjacent to sector 201, the set may be used to create P-type sequences including those shown in FIGS. 501A and 501B.”).
-Regarding claim 7:
Da discloses:
The method of claim 6, further comprising: applying a sorting algorithm to select vectors to provide an optimum switching sequence that minimises CMV transitions (paragraph 0028; “According to aspects of the present disclosure, the
controller 160 may reduce the common mode voltage, and thereby reduce common mode leakage current, by operating the inverter 106 using a subset of the possible switching states.”).
-Regarding claim 8:
Da discloses:
The method of claim 1, where n is 3 (abstract; “system and methods for active voltage balance of capacitors connected to a DC power source and to a three-phase three-level inverter, implemented by a controller”).
-Regarding claim 9:
Da discloses:
The method of claim 1, where n is greater than 3 (paragraph 0021;” or to any other multi-phase implementation that would be appreciated by one of ordinary skill in the art in view of this disclosure.”).
-Regarding claim 10:
Da discloses:
A space vector modulator (paragraph 0034; “the controller 160 may control the inverter 106 using a subset of switching states in a space vector modulation algorithm.”) configured to perform the method of claim 1.
-Regarding claim 11:
Da discloses:
A power converter comprising: an input stage (Fig. 1A; 102); an inverter stage (Fig. 1A; 106); an output stage(Fig. 1A; 104); and a space vector modulator configured for provided PWM switching signals to the inverter(paragraph 0052; “Resequencing a sequence of switching states may eliminate an increase in inverter switching frequency created by substitution of an alternative switching state and enable implementation using a simple PWM algorithm.”), wherein the space vector modulator is configured to perform the method of claim 1.
-Regarding claim 12:
Da discloses:
The power converter of claim 11, wherein the inverter stage is a three-level inverter (abstract; “system and methods for active voltage balance of capacitors
connected to a DC power source and to a three-phase three-level inverter, implemented by a controller comprising a space vector diagram is disclosed.”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-5 are rejected under 35 U.S.C. 103 as being unpatentable over Da Jiao et. al (US2018/0145607A1; hereafter “Da”) in view of Cui Wang et. al (IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 36, NO. 6, JUNE 2021; hereafter “Cui”).
-Regarding claim 2:
Da discloses:
The method of claim 1, further comprisingduty cycles and switching states are determined for a voltage reference vector located in one of the zones (Fig. 501, paragraph 0037; “Specifically, the trigonometric calculations may produce angle and magnitude values characterizing the relationship between the reference vector Vref and the three adjacent vectors. These angle and magnitude values then may be used to determine the dwell time for each of the switching states corresponding with the three adjacent vectors. The dwell time is the duration for which a particular state is applied by the controller. “), and wherein the
However, Da does not disclose synthesizing voltage reference vector in triangular zones at SVM strategy for multilevel converter.
Cui, in the same field of endeavor, discloses:
: dividing the sector of the space vector diagram into two equal triangular zones; (Fig. 3)………determined duty cycles and switching states are used to synthesise a voltage reference vector at a corresponding location in the other zone (Fig. 4, equation 11, 12, and introduction; “directly define the three-phase voltages as three coordinate axes (3-D coordinates) and synthesize reference vectors with four space vectors closest to the reference vector.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device described in Da such that a commonly used SVM strategy described in Cui is applied to the three-phase, three level inverter. Doing so allows for improving implement the SVM strategy in power inverter.
-Regarding claim 3:
Da discloses:
The method of claim 2, wherein the step of identifying a sector identifies sectors defined in a horizontal direction with respect to the space vector diagram (Fig. 2).
-Regarding claim 4:
Da discloses:
The method of claim 2, wherein the step of identifying a sector identifies sectors defined in a vertical direction with respect to the space vector diagram (Fig. 2).
-Regarding claim 5:
Cui discloses:
The method of claim 2, wherein the step of identifying a sector identifies square sectors within the space vector diagram (Fig. 4).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEUNG HO CHOI whose telephone number is (571)272-8188. The examiner can normally be reached Monday-Thursday, 7:30 AM - 5:30 PM ET.
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/SEUNG HO CHOI/Examiner, Art Unit 2838
/CRYSTAL L HAMMOND/Supervisory Primary Examiner, Art Unit 2838
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