Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are presented for examination.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3-4, 10-11, 16-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3, and similarly claims 4, 10-11, 16-17, recites the limitation "each micro-operation". There is insufficient antecedent basis for this limitation in the claim. There are no micro-operations previously claimed, therefore it is unclear to which micro-operations “each” refers.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-8, 11-14, 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Spadini et al., US Patent 12,217,060 (hereinafter Spadini) in view of Han et al., US Patent Application Publication 2019/0163477 (hereinafter Han).
Regarding claim 1, Spadini teaches:
An integrated circuit comprising: an issue queue configured to: scan instructions in a scheduler for an instruction and a dependent instruction that is dependent to the instruction (see e.g. fig. 2, fusion detector circuitry 102, col. 5 lines 5-29); and issue a fuse instruction based on the instruction and the dependent instruction (see e.g. col. 5 lines 5-29, col. 12 line 64 – col. 13 line 15, a fused instruction is issued); and a mask unit configured to: fuse an execution of the instruction and the dependent instruction (see e.g. fig. 2, 5, col. 5 lines 5-29, fusion detector circuitry with MDR circuit).
Spadini fails to explicitly teach the instruction and dependent instruction are vector instructions.
Han teaches checking for a data dependency between vector instructions for combining instructions (see e.g. para. [0024], [0039-41]).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Spadini and Han such that the instruction and dependent instruction are vector instructions. The use of vectors would have allowed for increased parallelism to improve the performance of the system.
Regarding claim 4, Spadini in view of Han teaches or suggests:
The integrated circuit of claim 1, wherein the mask unit is further configured to: send results from execution of each micro-operation from the dependent vector instruction to an accumulator (see e.g. Spadini col. 19 line 49 – col. 20 line 9, portions of a constant value are accumulated in a destination register by each instruction of the fused instruction).
Regarding claim 5, Spadini in view of Han teaches or suggests:
The integrated circuit of claim 1, wherein to fuse the execution of the vector instruction and the dependent vector instruction, the mask unit is further configured to: perform a compare instruction; perform a logical instruction; and generate a partial result (see e.g. Spadini col. 14 line 1 – col. 15 line 2).
Regarding claim 6, Spadini in view of Han teaches or suggests:
The integrated circuit of claim 1, wherein the vector instruction is a compare instruction and the dependent vector instruction is a logical instruction (see e.g. Spadini col. 14 line 1 – col. 15 line 2).
Regarding claim 7, Spadini in view of Han teaches or suggests:
The integrated circuit of claim 1, further comprising: three registers to fuse the execution of the vector instruction and the dependent vector instruction (see e.g. Spadini col. 13 line 37 – col. 14 line 33, two source operand registers and one destination register).
Claims 8, 11-13 are rejected for reasons corresponding to those given above for claims 1, 4-6.
Claims 14, 17-20 are rejected for reasons corresponding to those given above for claims 1, 4-7.
Claims 2, 9, 15 are rejected under 35 U.S.C. 103 as being unpatentable over Spadini in view of Han, further in view of Karve et al., US Patent Application Publication 2019/0163488 (hereinafter Karve).
Regarding claim 2, Spadini in view of Han teaches or suggests:
The integrated circuit of claim 1.
Spadini in view of Han fails to explicitly teach wherein the issue queue is further configured to: clear the vector instruction and the dependent vector instruction from the issue queue.
Karve teaches clearing an instruction and a dependent instruction from an issue queue (see e.g. para. [0031]).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Spadini, Han, and Karve such that the issue queue is further configured to: clear the vector instruction and the dependent vector instruction from the issue queue. This would have ensured that the issue queue entry could be reused by a new instruction to improve future processing performance (see e.g. Karve para. [0029]).
Claim 9 is rejected for reasons corresponding to those given above for claim 2.
Claim 15 is rejected for reasons corresponding to those given above for claim 2.
Claims 3, 10, 16 are rejected under 35 U.S.C. 103 as being unpatentable over Spadini in view of Han, further in view of Ronen et al., US Patent Application Publication 2002/0087955 (hereinafter Ronen).
Regarding claim 3, Spadini in view of Han teaches or suggests:
The integrated circuit of claim 1.
Spadini in view of Han fails to explicitly teach wherein to fuse the execution of the vector instruction and the dependent vector instruction, the mask unit further configured to: write results from execution of each micro-operation decoded from the vector instruction of the fuse instruction to a mask accumulator; and execute micro-operations from the dependent vector instruction on the results in the mask accumulator as they become available.
Ronen teaches storing partial results of an instruction in a temporary (accumulator) register such that a dependent instruction can use results as they become available (see e.g. para. [0029]).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Spadini, Han, and Ronen such that to fuse the execution of the vector instruction and the dependent vector instruction, the mask unit further configured to: write results from execution of each micro-operation decoded from the vector instruction of the fuse instruction to a mask accumulator; and execute micro-operations from the dependent vector instruction on the results in the mask accumulator as they become available. This would have provided a benefit of increased efficiency by using fewer registers for the fused instruction (see e.g. Ronen para. [0029]).
Claim 10 is rejected for reasons corresponding to those given above for claim 3.
Claim 16 is rejected for reasons corresponding to those given above for claim 3.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN M LINDLOF whose telephone number is (571)270-1024. The examiner can normally be reached Mon-Tue 8:30-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached at 5712703995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOHN M LINDLOF/ Primary Examiner, Art Unit 2183
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