CTNF 19/042,760 CTNF 81222 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Objections 2. Claim 28 is objected to because of the following informalities: line 2 recites “transaction layer packet” which should be corrected to “transaction layer packet (TLP)”. Claim 34 is objected to because of the following informalities: line 2 recites “transaction layer packet” which should be corrected to “transaction layer packet (TLP)”. 07-29-01 AIA Claim 41 is objected to because of the following informalities: line 3 recites “transaction layer packet” which should be corrected to “transaction layer packet (TLP)” . Appropriate correction is required. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA 4. Claim s 21 – 24, 32, 34 – 38, 41, and 42 are rejected under 35 U.S.C. 103 as being unpatentable over Sankaran et al. (US Publication Number 2020/0004703, hereinafter “Sankaran”) in view of Lesartre et al. (US Publication Number 2020/0356497, hereinafter “Lesartre”) . 5. As per claims 21 and 36, Sankaran teaches an apparatus and system comprising: a first device (1005, figure 10); and a second device (1025, figure 10) coupled to the first device by an interconnect (via interconnect 1006, figure 10), wherein the second device comprises a port (ports 1005 to 1015 and 1017/1021, figure 10) to couple the second device to the interconnect (paragraph 268 coupling), wherein the port comprises: protocol circuitry to implement a Peripheral Component Interconnect Express (PCIe)-based link on the interconnect (PCIe based, paragraph 267), wherein the protocol circuitry is to: identify a memory transaction to transmit from the first device to the second device on the link (memory transaction handling, paragraphs 271- 274); and receive a completion for the memory transaction on the link from the first device (successful completion, paragraphs 91/102/160). Sankaran does not appear to explicitly disclose select an unordered virtual channel for use with the memory transaction, wherein the unordered virtual channel is to be selected from a plurality of different virtual channels for the link, ordering of transactions on the unordered virtual channel is defined to be requester-managed, and completions are to be received for read and write transactions on the unordered virtual channel; send the memory transaction on the link, wherein the transaction is sent to identify that the unordered virtual channel applies to the transaction. However, Lesartre discloses select an unordered virtual channel (VC, paragraph 53) for use with the memory transaction (unordered transaction, paragraph 75), wherein the unordered virtual channel is to be selected from a plurality of different virtual channels for the link (paragraph 63), ordering of transactions on the unordered virtual channel is defined to be requester-managed (ordering relationship with transactions, paragraph 70), and completions are to be received for read and write transactions on the unordered virtual channel (completion handling, paragraph 75); send the memory transaction on the link, wherein the transaction is sent to identify that the unordered virtual channel applies to the transaction (unordered transaction class for VC, paragraph 75). Sankaran and Lesartre are analogous art because they are from the same field of endeavor virtual channel handling. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Sankaran and Lesartre before him or her, to modify the structure of Sankaran to include the ordering mechanism of Lesartre because it would enhance the VM functionality. One of ordinary skill would be motivated to make such modification in order to enhance packet handling (paragraph 1). Therefore, it would have been obvious to combine Lesartre with Sankaran to obtain the invention as specified in the instant claims. 6. As per claims 34 and 41, Sankaran teaches a method and non-transitory machine-readable storage medium comprising: receiving, at a first device (1005, figure 10), a transaction layer packet (paragraph 272, TLP) from a second device (1025, figure 1) on a link (link 1006, figure 10), wherein the link couples the first device to a second device and is compliant with a Peripheral Component Interconnect Express (PCIe) based protocol (PCIe, paragraph 271); performing a write to a memory element based on the memory write request (memory transaction handling, paragraphs 271- 274, successful completion, paragraphs 91/102/160). Sankaran does not appear to explicitly disclose a memory write request and indicates an unordered virtual channel, wherein the unordered virtual channel is one of a plurality of virtual channels defined for the link; and sending a completion based on memory write request being received on the unordered virtual channel. However, Lesartre discloses a memory write request and indicates an unordered virtual channel (VC, paragraph 53, unordered transaction, paragraph 75), wherein the unordered virtual channel is one of a plurality of virtual channels defined for the link (plurality of VCs, paragraphs 53 and 57); and sending a completion based on memory write request being received on the unordered virtual channel (completion handling, paragraph 75). Sankaran and Lesartre are analogous art because they are from the same field of endeavor virtual channel handling. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Sankaran and Lesartre before him or her, to modify the structure of Sankaran to include the ordering mechanism of Lesartre because it would enhance the VM functionality. One of ordinary skill would be motivated to make such modification in order to enhance packet handling (paragraph 1). Therefore, it would have been obvious to combine Lesartre with Sankaran to obtain the invention as specified in the instant claims. 7. Sankaran modified by the teachings of Lesartre as seen in claim 21 above, as per claim 22, Lesartre teaches an apparatus, wherein the memory transaction comprises a memory write and the completion is received for the memory write transaction on the unordered virtual channel (completion handling, paragraph 75). 8. Sankaran modified by the teachings of Lesartre as seen in claim 21 above, as per claims 23, 35, and 42, Sankaran teaches an apparatus, method, and medium, wherein another one of the plurality of virtual channels is based on a PCIe producer/consumer ordering model (paragraphs 94 and 210). 9. Sankaran modified by the teachings of Lesartre as seen in claim 21 above, as per claim 24, Lesartre teaches an apparatus, further comprising ordering management logic to define and manage ordering of transactions to be transmitted from the first device on the unordered virtual channel of the link (ordering relationship with transactions, paragraph 70). 10. Sankaran modified by the teachings of Lesartre as seen in claim 21 above, as per claim 32, Sankaran teaches an apparatus, wherein the PCIe-based link is based on a PCIe 6 protocol (paragraph 261). 11. Sankaran modified by the teachings of Lesartre as seen in claim 21 above, as per claim 37, Sankaran teaches an apparatus, wherein the link allows multiple alternative paths for data transfer between the first device and the second device (plurality of paths between 1005/1025, figure 10, paragraph 289). 12. Sankaran modified by the teachings of Lesartre as seen in claim 21 above, as per claim 38, Sankaran teaches an apparatus, further comprising a switch device (1020, figure 10) positioned between the first device and the second device, wherein the switch device supports the unordered virtual channel (paragraph 269) . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 13. Claim s 25 – 31, 33, 39, and 40 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion 07-96 AIA 14. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Hyatt/Reddy/Daniel/Freking/Banerjee have teachings of order/unordered VC TLP handling . Any inquiry concerning this communication or earlier communications from the examiner should be directed to AURANGZEB HASSAN whose telephone number is (571)272-8625. The examiner can normally be reached 7 AM to 3 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached at 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. AH /HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184 Application/Control Number: 19/042,760 Page 2 Art Unit: 2184 Application/Control Number: 19/042,760 Page 3 Art Unit: 2184 Application/Control Number: 19/042,760 Page 4 Art Unit: 2184 Application/Control Number: 19/042,760 Page 5 Art Unit: 2184 Application/Control Number: 19/042,760 Page 6 Art Unit: 2184 Application/Control Number: 19/042,760 Page 7 Art Unit: 2184 Application/Control Number: 19/042,760 Page 8 Art Unit: 2184
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