DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. Claims 1-20 are pending.
Claim Rejections - 35 USC § 112
3. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
4. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 11 and 18: The term “generate a counter value that represents a time distance between a frame slot and a packet start” in claims 1, 11 and 18 is a relative term which renders the claim indefinite. The term “generate a counter value that represents a time distance between a frame slot and a packet start” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. There is no description on how to determine what is the start of the packet and what time slot of a frame the packet begins from to measure or detect what is the actual distance of time for transmission of the packet on a repeater channel.
Claims 1, 11 and 18: The terms “frame slot” and “packet slot” are vague and unclear and leaves the Examiner in doubt as to the meaning of the technical features to which they refer, thereby rendering the definition of the subject-matter of said claim unclear.
Claim 3: The term “the timer is further configured to measure a time duration from when the packet start is detected to when the frame slot is transmitted on the repeater channel.” Seems contradicting to the features presented in the description par. [0041]: “the receiver (RX) 104 monitors time distance from the starting point of the latency-sensitive slot in a frame until a packet start is detected at the repeater input”, which defines the time duration in reversed action sequence, thereby rendering the definition of the subject-matter of said claim unclear.
Claims 2, 4-10, 12-17 and 19-20 are further rejected based on their dependency of claims 1, 11 and 18.
Claim Rejections - 35 USC § 102
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
6. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
7. Claims 1-9, 18 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by McGowan (US Patent No. 10,095,653 B2 hereinafter “McGowan”).
Referring to claim 1, McGowan discloses a repeater (McGowan – Fig. 4, retimer 406) comprising:
a timer (McGowan – Fig. 4, time count 432) configured to generate a counter value (McGowan – Col. 9, lines 57-59 disclose “Clock 430 (e.g., core clock) in transmitter clock domain may be used to increment a counter 432 (e.g., which may roll back to zero).”) that represents a time distance between a frame slot (McGowan – Col. 9, lines 59-62 disclose “ a block of data is input into retimer 406 (e.g., schematically illustrated as a transaction). Block of data may include a timestamp (e.g., isochronous timestamp (ITS)).”) and a packet start (McGowan – Col. 10, lines 9-22 disclose “Elastic buffer 424 may accumulate an entire data block and then start passing the data block to the controller 420 via the synchronizer 418 … The controller 420 may then compare (e.g., via the subtractor circuit 434) the additional timestamp 448 (e.g., in the transmitter clock domain) to the current time counter 432 (e.g., in the transmitter clock domain) to determine the amount of delay the data block experienced while in the elastic buffer 424.”); and
a modem configured to transmit output data containing the counter value over a repeater channel (McGowan – Col. 10, lines 22-33 disclose “This delta time output from the subtractor circuit (and optionally with any constant delays 438 associated with the retimer circuit) may be added (e.g., via adder circuit 436) to determine the total delay (e.g., retimer delay and link delay (1)) in the retimer 406. This total delay may then be added (e.g., via adder circuit 440) to the timestamp 446 to produce a timestamp 456 that includes the total delay of propagating through the retimer (and link). Data block and timestamp 456 (e.g., corrected isochronous timestamp (ITS)) may then be passed to a transmitter (e.g., 422) for transmittal, for example, to a downstream device 404.”).
Referring to claim 2, McGowan discloses the repeater of claim 1, wherein a time calculated from the counter value is elapsed at a receiver to achieve a deterministic and fixed propagation delay before starting data retransmission (McGowan – Fig. 5: link delay (1) + retimer delay + link delay (2)).
Referring to claim 3, McGowan discloses repeater of claim 1, wherein the timer is further configured to measure a time duration from when the packet start is detected to when the frame slot is transmitted on the repeater channel (McGowan – Col. 9, lines 59-60 disclose “a block of data is input into retimer 406”; Col. 10, lines 9-11 disclose “Elastic buffer 424 may accumulate an entire data block and then start passing the data block to the controller 420.”).
Referring to claim 4, McGowan discloses the repeater of claim 1, further comprising a packet management unit configured to start a counter of the timer when a start-of-packet is detected, and wherein the counter value of the counter represents the time distance between the frame slot of the repeater channel and the packet start (McGowan – Col. 9, lines 57-58 disclose “Clock 430 (e.g., core clock) in transmitter clock domain may be used to increment a counter 432.”; Col. 9, lines 59-62 disclose “ a block of data is input into retimer 406 (e.g., schematically illustrated as a transaction). Block of data may include a timestamp (e.g., isochronous timestamp (ITS)).”; Col. 10, lines 9-22 disclose “Elastic buffer 424 may accumulate an entire data block and then start passing the data block to the controller 420 via the synchronizer 418 … The controller 420 may then compare (e.g., via the subtractor circuit 434) the additional timestamp 448 (e.g., in the transmitter clock domain) to the current time counter 432 (e.g., in the transmitter clock domain) to determine the amount of delay the data block experienced while in the elastic buffer 424.”).
Referring to claim 5, McGowan discloses the repeater of claim 4, wherein the timer is further configured to recycle the counter each time a slot start signal is received (McGowan – Col. 3, lines 44-52 disclose “a header or block identifier (e.g., 4 bits) is prepended to a group of symbols (for example, 16 symbols, e.g., 128 bits) to create a data block (e.g., a 132 bit data block, which may be referred to as 128b/132b encoding). In certain embodiments, a packet generally refers to a section of data and control bytes (e.g., symbols), for example, a 4-bit block identifier (e.g., header or framing symbol) and a 16 byte payload of data. In certain embodiments, a packet is multiple data blocks.”).
Referring to claim 6, McGowan discloses the repeater of claim 4, wherein the timer is further configured to freeze the counter value when the packet start is detected by the packet management unit (McGowan – Col. 10, lines 17-22 disclose “The controller 420 may then compare (e.g., via the subtractor circuit 434) the additional timestamp 448 (e.g., in the transmitter clock domain) to the current time counter 432 (e.g., in the transmitter clock domain) to determine the amount of delay the data block experienced while in the elastic buffer 424.”).
Referring to claim 7, McGowan discloses the repeater of claim 6, wherein the packet management unit is further configured to trigger a start of packet (SoP) unit when the packet start is detected (McGowan – Col. 10, lines 27-33 disclose “This total delay may then be added (e.g., via adder circuit 440) to the timestamp 446 to produce a timestamp 456 that includes the total delay of propagating through the retimer (and link). Data block and timestamp 456 (e.g., corrected isochronous timestamp (ITS)) may then be passed to a transmitter (e.g., 422) for transmittal, for example, to a downstream device 404.”).
Referring to claim 8, McGowan discloses the repeater of claim 7, wherein the SoP unit is configured to generate an SOP extended symbol that comprises an SOP identification (ID) and the counter value (McGowan – Col. 10, lines 27-33 disclose “This total delay may then be added (e.g., via adder circuit 440) to the timestamp 446 to produce a timestamp 456 that includes the total delay of propagating through the retimer (and link). Data block and timestamp 456 (e.g., corrected isochronous timestamp (ITS)) may then be passed to a transmitter (e.g., 422) for transmittal, for example, to a downstream device 404.”; Col. 3, lines 44-52 disclose “a header or block identifier (e.g., 4 bits) is prepended to a group of symbols (for example, 16 symbols, e.g., 128 bits) to create a data block (e.g., a 132 bit data block, which may be referred to as 128b/132b encoding). In certain embodiments, a packet generally refers to a section of data and control bytes (e.g., symbols), for example, a 4-bit block identifier (e.g., header or framing symbol) and a 16 byte payload of data. In certain embodiments, a packet is multiple data blocks.”).
Referring to claim 9, McGowan discloses the repeater of claim 1, further comprising a physical layer configured to receive input data from a data source with a latency requirement (McGowan – Col. 5, lines 33-39 disclose “a circuit 200 including an upstream device 202 coupled to a downstream device 204 through a retimer 206 according to embodiments of the disclosure. Depicted upstream device 202 (e.g., bus host) includes a transmitter 202A (e.g., as part of a transceiver circuit (physical layer (PHY)) and may also include a receiver.”), and wherein the counter value represents the time distance between the frame slot of the repeater channel and the packet start of the input data (McGowan – Col. 9, lines 57-58 disclose “Clock 430 (e.g., core clock) in transmitter clock domain may be used to increment a counter 432.”; Col. 9, lines 59-62 disclose “ a block of data is input into retimer 406 (e.g., schematically illustrated as a transaction). Block of data may include a timestamp (e.g., isochronous timestamp (ITS)).”; Col. 10, lines 9-22 disclose “Elastic buffer 424 may accumulate an entire data block and then start passing the data block to the controller 420 via the synchronizer 418 … The controller 420 may then compare (e.g., via the subtractor circuit 434) the additional timestamp 448 (e.g., in the transmitter clock domain) to the current time counter 432 (e.g., in the transmitter clock domain) to determine the amount of delay the data block experienced while in the elastic buffer 424.”).
Referring to claim 18, note the rejections of claim 1 above. The Instant Claim recites substantially same limitations as the above-rejected and is therefore rejected under same prior-art teachings.
Referring to claim 20, note the rejections of claim 4 above. The Instant Claim recites substantially same limitations as the above-rejected and is therefore rejected under same prior-art teachings.
Claim Rejections - 35 USC § 103
8. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
9. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over McGowan in view of Srivastava (US Pub. No. 2018/0189222 A1 hereinafter “Srivastava”).
Referring to claim 10, McGowan discloses the repeater of claim 1, however, fails to explicitly disclose wherein the repeater comprises an embedded Universal Serial Bus (eUSB) repeater.
Srivastava discloses the repeater comprises an embedded Universal Serial Bus (eUSB) repeater (Srivastava – Fig. 1A shows embedded Universal Serial Bus 2 (eUSB2) repeater 130.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Srivastava’s teachings with McGowan’s techniques for the benefit of providing reduced pin counts and associated costs in systems having multiple lane serial bus devices (Srivastava – Par. [0027]).
Referring to claim 11, McGowan discloses an Universal Serial Bus (USB) repeater (McGowan – Col. 1, lines 10-11 disclose “a Universal Serial Bus (USB) retimer circuit.”) comprising:
a timer (McGowan – Fig. 4, time count 432) configured to generate a counter value (McGowan – Col. 9, lines 57-59 disclose “Clock 430 (e.g., core clock) in transmitter clock domain may be used to increment a counter 432 (e.g., which may roll back to zero).”) that represents a time distance between a frame slot (McGowan – Col. 9, lines 59-62 disclose “ a block of data is input into retimer 406 (e.g., schematically illustrated as a transaction). Block of data may include a timestamp (e.g., isochronous timestamp (ITS)).”) and a packet start (McGowan – Col. 10, lines 9-22 disclose “Elastic buffer 424 may accumulate an entire data block and then start passing the data block to the controller 420 via the synchronizer 418 … The controller 420 may then compare (e.g., via the subtractor circuit 434) the additional timestamp 448 (e.g., in the transmitter clock domain) to the current time counter 432 (e.g., in the transmitter clock domain) to determine the amount of delay the data block experienced while in the elastic buffer 424.”);
a framer configured to generate a plurality of frames based on the counter value (McGowan – Col. 20, lines 63-65 disclose “an 8b/10b transmission code is employed, where ten-bit symbols are transmitted/received. Here, special symbols are used to frame a packet with frames 1223.”); and
a modem configured to transmit the frames over a repeater channel (McGowan – Col. 10, lines 22-33 disclose “This delta time output from the subtractor circuit (and optionally with any constant delays 438 associated with the retimer circuit) may be added (e.g., via adder circuit 436) to determine the total delay (e.g., retimer delay and link delay (1)) in the retimer 406. This total delay may then be added (e.g., via adder circuit 440) to the timestamp 446 to produce a timestamp 456 that includes the total delay of propagating through the retimer (and link). Data block and timestamp 456 (e.g., corrected isochronous timestamp (ITS)) may then be passed to a transmitter (e.g., 422) for transmittal, for example, to a downstream device 404.”).
McGowan fails to explicitly disclose an embedded Universal Serial Bus (eUSB) repeater.
Srivastava discloses an embedded Universal Serial Bus (eUSB) repeater (Srivastava – Fig. 1A shows embedded Universal Serial Bus 2 (eUSB2) repeater 130.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Srivastava’s teachings with McGowan’s techniques for the benefit of providing reduced pin counts and associated costs in systems having multiple lane serial bus devices (Srivastava – Par. [0027]).
Referring to claim 12, McGowan and Srivastava disclose the eUSB repeater of claim 11, further comprising a packet management unit configured to start a counter of the timer when a start-of-packet is detected (Srivastava – Par. [0037] discloses “Port router 210 includes squelch circuit 212, wake circuit 214, port address assignment circuit 216, start-of-packet (SOP)/end-of-packet (EOP) circuit 218 and port routing circuit 270.”)., and wherein the counter value of the counter represents the time distance between the frame slot of the repeater channel and the packet start (McGowan – Col. 9, lines 57-58 disclose “Clock 430 (e.g., core clock) in transmitter clock domain may be used to increment a counter 432.”; Col. 9, lines 59-62 disclose “ a block of data is input into retimer 406 (e.g., schematically illustrated as a transaction). Block of data may include a timestamp (e.g., isochronous timestamp (ITS)).”; Col. 10, lines 9-22 disclose “Elastic buffer 424 may accumulate an entire data block and then start passing the data block to the controller 420 via the synchronizer 418 … The controller 420 may then compare (e.g., via the subtractor circuit 434) the additional timestamp 448 (e.g., in the transmitter clock domain) to the current time counter 432 (e.g., in the transmitter clock domain) to determine the amount of delay the data block experienced while in the elastic buffer 424.”).
Referring to claim 13, McGowan and Srivastava disclose the eUSB repeater of claim 12, wherein the timer is further configured to recycle the counter each time a slot start signal is received (McGowan – Col. 3, lines 44-52 disclose “a header or block identifier (e.g., 4 bits) is prepended to a group of symbols (for example, 16 symbols, e.g., 128 bits) to create a data block (e.g., a 132 bit data block, which may be referred to as 128b/132b encoding). In certain embodiments, a packet generally refers to a section of data and control bytes (e.g., symbols), for example, a 4-bit block identifier (e.g., header or framing symbol) and a 16 byte payload of data. In certain embodiments, a packet is multiple data blocks.”).
Referring to claim 14, McGowan and Srivastava disclose the eUSB repeater of claim 12, wherein the timer is further configured to freeze the counter value when the packet start is detected by the packet management unit (McGowan – Col. 10, lines 17-22 disclose “The controller 420 may then compare (e.g., via the subtractor circuit 434) the additional timestamp 448 (e.g., in the transmitter clock domain) to the current time counter 432 (e.g., in the transmitter clock domain) to determine the amount of delay the data block experienced while in the elastic buffer 424.”).
Referring to claim 15, McGowan and Srivastava disclose the eUSB repeater of claim 14, wherein the packet management unit is further configured to trigger a start of packet (SoP) unit when the packet start is detected (McGowan – Col. 10, lines 27-33 disclose “This total delay may then be added (e.g., via adder circuit 440) to the timestamp 446 to produce a timestamp 456 that includes the total delay of propagating through the retimer (and link). Data block and timestamp 456 (e.g., corrected isochronous timestamp (ITS)) may then be passed to a transmitter (e.g., 422) for transmittal, for example, to a downstream device 404.”).
Referring to claim 16, McGowan and Srivastava disclose the eUSB repeater of claim 15, wherein the SoP unit is configured to generate an SOP extended symbol that comprises an SOP identification (ID) and the counter value (McGowan – Col. 10, lines 27-33 disclose “This total delay may then be added (e.g., via adder circuit 440) to the timestamp 446 to produce a timestamp 456 that includes the total delay of propagating through the retimer (and link). Data block and timestamp 456 (e.g., corrected isochronous timestamp (ITS)) may then be passed to a transmitter (e.g., 422) for transmittal, for example, to a downstream device 404.”; Col. 3, lines 44-52 disclose “a header or block identifier (e.g., 4 bits) is prepended to a group of symbols (for example, 16 symbols, e.g., 128 bits) to create a data block (e.g., a 132 bit data block, which may be referred to as 128b/132b encoding). In certain embodiments, a packet generally refers to a section of data and control bytes (e.g., symbols), for example, a 4-bit block identifier (e.g., header or framing symbol) and a 16 byte payload of data. In certain embodiments, a packet is multiple data blocks.”).
Referring to claim 17, McGowan and Srivastava disclose the eUSB repeater of claim 11, further comprising a physical layer configured to receive input data from a data source with a latency requirement (McGowan – Col. 5, lines 33-39 disclose “a circuit 200 including an upstream device 202 coupled to a downstream device 204 through a retimer 206 according to embodiments of the disclosure. Depicted upstream device 202 (e.g., bus host) includes a transmitter 202A (e.g., as part of a transceiver circuit (physical layer (PHY)) and may also include a receiver.”).
Referring to claim 19, McGowan and Srivastava disclose the method of claim 18, further comprising generating a plurality of frames based on the counter value (McGowan – Col. 20, lines 63-65 disclose “an 8b/10b transmission code is employed, where ten-bit symbols are transmitted/received. Here, special symbols are used to frame a packet with frames 1223.”), wherein transmitting the output data containing the counter value over the repeater channel comprises transmitting the frames over the repeater channel (McGowan – Col. 10, lines 22-33 disclose “This delta time output from the subtractor circuit (and optionally with any constant delays 438 associated with the retimer circuit) may be added (e.g., via adder circuit 436) to determine the total delay (e.g., retimer delay and link delay (1)) in the retimer 406. This total delay may then be added (e.g., via adder circuit 440) to the timestamp 446 to produce a timestamp 456 that includes the total delay of propagating through the retimer (and link). Data block and timestamp 456 (e.g., corrected isochronous timestamp (ITS)) may then be passed to a transmitter (e.g., 422) for transmittal, for example, to a downstream device 404.”).
Conclusion
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R.I .Ill(c).
In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAYTON LEWIS-TAYLOR whose telephone number is (571) 2707754. The examiner can normally be reached on Monday through Thursday, 8AM TO 4PM, EASTERN TIME.
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/Dayton Lewis-Taylor/
Examiner, Art Unit 2181
Prosecution Insights