Prosecution Insights
Last updated: May 29, 2026
Application No. 19/042,943

Data Identity Based Caching in a Network of Computational Nodes

Non-Final OA §102§103
Filed
Jan 31, 2025
Priority
Feb 01, 2024 — provisional 63/548,837
Examiner
DUDEK JR, EDWARD J
Art Unit
2132
Tech Center
2100 — Computer Architecture & Software
Assignee
Tenstorrent Usa Inc.
OA Round
1 (Non-Final)
89%
Grant Probability
Favorable
1-2
OA Rounds
1y 0m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
993 granted / 1112 resolved
+34.3% vs TC avg
Moderate +5% lift
Without
With
+5.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
15 currently pending
Career history
1137
Total Applications
across all art units

Statute-Specific Performance

§101
2.3%
-37.7% vs TC avg
§103
66.6%
+26.6% vs TC avg
§102
16.0%
-24.0% vs TC avg
§112
8.0%
-32.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1112 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This Office Action is responsive to the application filed 31 January 2025. Claims 1-20 are pending and have been presented for examination. Claim Interpretation The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph: An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked. As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph: (A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function; (B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and (C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function. Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function. Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function. Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1, 2, 4, 5, 9, 10, 12, 13 and 17-19 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by MEIRI (U.S. Patent Application Publication #2021/0034538). 1. MEIRI discloses A system comprising: a set of computational nodes (see [0035]: information processing system that includes host devices); an interconnect fabric that networks the set of computational nodes (see [0059]: full mesh network); and a set of caches wherein the caches in the set of caches are uniquely associated with the computational nodes in the set of computational nodes and store data in the caches in the set of caches based on an identity of the data (see [0109]: read caches that store data, the A2H and H2D tables provide an identity of the data in the cache and associate the data with a node). 2. The system of claim 1, wherein the caches in the set of caches store data based on an identity of the data in that: each computational node is configured to, when storing data in memory, distinguish read-only data from other data and store the read-only data in the set of caches based on the distinction that the data is read-only data (see [0110]-[0111]: data available to be read is fetched from the cache, other data is requested from the data module). 4. The system of claim 1, wherein the caches in the set of caches store data based on an identity of the data in that: the system further comprises a set of address ranges from an address space wherein the caches in the set of caches are uniquely associated with address ranges in the set of address ranges (see [0125]: content based signatures are associated with an address range); and each computational node is configured to, when storing data in memory, determine an identity of the data and store the data in an address range from the set of address ranges that is associated with the identity (see [0126]: each control module maintains a cache and is responsible for a portion of the address space of the slices). 5. The system of claim 4, wherein: the data is output data of a first computational node in the set of computational nodes (see [0038]: read and write to the content addressable storage system); and the address range refers to a cache that is part of a second computational node in the set of computational nodes, wherein the data is used as an input to the second computational node (see [0137]: first module receives a second content based signature from a second module and updates a second data page with the new page data). 9. MEIRI discloses A method, in which each step is conducted by a set of computational nodes (see [0035]: information processing system that includes host devices) that are networked by an interconnect fabric (see [0059]: full mesh network), comprising: determining an identity of a unit of data (see [0069]: metadata page characterizes a different set of user data pages which include LUN identifiers, offsets and content based signatures); and storing the unit of data in a set of caches, wherein the caches in the set of caches are uniquely associated with the computational nodes in the set of computational nodes, based on the identity of the unit of data (see [0109]: read caches that store data, the A2H and H2D tables provide an identity of the data in the cache and associate the data with a node). 10. The method of claim 9, wherein: determining the identity of the unit of data comprises distinguishing read-only data from other data (see [0110]-[0111]: data available to be read is fetched from the cache, other data is requested from the data module); and storing the unit of data comprises storing the read-only data in the set of caches based on the distinction that the unit of data is read-only data (see [0010]: data to be read is stored in a cache, this is read-only data as there are no writes to the read cache). 12. The method of claim 9, further comprising: uniquely associating the caches in the set of caches with address ranges in a set of address ranges, the set of address ranges being from an address space (see [0125]: content based signatures are associated with an address range); wherein storing the unit of data comprises storing the unit of data in an address range from the set of address ranges that is associated with the identity of the unit of data (see [0126]: each control module maintains a cache and is responsible for a portion of the address space of the slices). 13. The method of claim 12, wherein: the unit of data is output data of a first computational node in the set of computational nodes (see [0038]: read and write to the content addressable storage system); and the address range refers to a cache that is part of a second computational node in the set of computational nodes, wherein the unit of data is used as an input to the second computational node (see [0137]: first module receives a second content based signature from a second module and updates a second data page with the new page data). 17. MEIRI discloses A system, comprising: means for determining an identity of a unit of data (see [0069]: metadata page characterizes a different set of user data pages which include LUN identifiers, offsets and content based signatures); and means for storing the unit of data in a set of caches, wherein the caches in the set of caches are uniquely associated with computational nodes in a set of computational nodes, based on the identity of the unit of data (see [0109]: read caches that store data, the A2H and H2D tables provide an identity of the data in the cache and associate the data with a node). 18. The system of claim 17, wherein: the means for determining the identity of the unit of data comprises means for distinguishing read-only data from other data (see [0110]-[0111]: data available to be read is fetched from the cache, other data is requested from the data module); and the means for storing the unit of data comprises means for storing the read-only data in the set of caches based on the distinction that the unit of data is read-only data (see [0010]: data to be read is stored in a cache, this is read-only data as there are no writes to the read cache). 19. The system of claim 17, further comprising: means for uniquely associating the caches in the set of caches with address ranges in a set of address ranges, the set of address ranges being from an address space (see [0125]: content based signatures are associated with an address range); wherein the means for storing the unit of data comprises means for storing the unit of data in an address range from the set of address ranges that is associated with the identity of the unit of data (see [0126]: each control module maintains a cache and is responsible for a portion of the address space of the slices). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over MEIRI (U.S. Patent Application Publication #2021/0034538) in view of FALCO (U.S. Patent Application Publication #2022/0027052). 3. The system of claim 2 (see MEIRI above), further comprising: compiled instructions, for a complex computation to be executed by the set of computational nodes, that mark the data as read-only after a portion of the complex computation has been executed (see FALCO below). FALCO discloses the following limitations that are not disclosed by MEIRI: compiled instructions, for a complex computation to be executed by the set of computational nodes (see [0046]: applications reading and writing to and from the data grid; applications are compiled instructions), that mark the data as read-only after a portion of the complex computation has been executed (see [0059]: during execution, the node can turn on a lock and allow read/write requests to change data, the node can switch back to read-only when the number of read-write requests decreases). Executing instructions using data in the cache avoids expensive requests to back end data sources (see [0046]). Marking the data as read-only when a portion of the computation has been executed reduces overhead associated with data access (see [0060]). It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify MEIRI to execute instructions and mark data as read-only, as disclosed by FALCO. One of ordinary skill in the art would have been motivated to make such a modification to avoid expensive requests to back-end sources and reduce overhead associated with data access, as taught by FALCO. MEIRI and FALCO are analogous/in the same field of endeavor as both references are directed to caching data for nodes. Claim(s) 8 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over MEIRI (U.S. Patent Application Publication #2021/0034538) in view of WALKER (U.S. Patent Application Publication #2021/0056031). 8. The system of claim 1 (see MEIRI above), further comprising: a memory controller (see MEIRI [0077]: distributed storage controller); and a third level cache that is: (i) shared by the computational nodes in the set of computational nodes (see WALKER below); and (ii) directly administrated by the memory controller (see MEIRI [0077]: distributed storage controller directly manages the cache memory; [0109]-[0119]: control manages contain the cache memory that is managed by the distributed storage controller); wherein a caching policy of the set of computational nodes routes all cache writes to the third level cache (see WALKER below). WALKER discloses the following limitations that are not disclosed by MEIRI: a third level cache that is: (i) shared by the computational nodes in the set of computational nodes (see [0042]: three levels of caches; [0045]: L3 cache is a global cache and shared by all processor cores); wherein a caching policy of the set of computational nodes routes all cache writes to the third level cache (see [0047]: entries in the L1 and L2 cache are written to the L3 cache when initiating entry to the powered down state). Implementing a third level cache shared by all the nodes allows the system to preserve data in the event of a powered down state (see [0047]). It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify MEIRI to implement a third level cache, as disclosed by WALKER. One of ordinary skill in the art would have been motivated to make such a modification to preserve data in the event of a powered down state, as taught by WALKER. MEIRI and WALKER are analogous/in the same field of endeavor as both references are directed to caching data. 16. The method of claim 9 (see MEIRI above), further comprising: routing all cache writes to a third level cache, wherein the third level cache is: (i) shared by the computational nodes in the set of computational nodes (see WALKER below); and (ii) directly administrated by a memory controller (see MEIRI [0077]: distributed storage controller directly manages the cache memory; [0109]-[0119]: control manages contain the cache memory that is managed by the distributed storage controller). WALKER discloses the following limitations that are not taught by MEIRI: routing all cache writes to a third level cache (see [0047]: entries in the L1 and L2 cache are written to the L3 cache when initiating entry to the powered down state), wherein the third level cache is: (i) shared by the computational nodes in the set of computational nodes (see [0042]: three levels of caches; [0045]: L3 cache is a global cache and shared by all processor cores). Implementing a third level cache shared by all the nodes allows the system to preserve data in the event of a powered down state (see [0047]). It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify MEIRI to implement a third level cache, as disclosed by WALKER. One of ordinary skill in the art would have been motivated to make such a modification to preserve data in the event of a powered down state, as taught by WALKER. MEIRI and WALKER are analogous/in the same field of endeavor as both references are directed to caching data. Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over MEIRI (U.S. Patent Application Publication #2021/0034538) in view of COWPERTHWAITE (U.S. Patent Application Publication #2023/0297440). 15. The method of claim 9 (see MEIRI above), wherein the unit of data is trained data of an artificial intelligence model (see COWPERTHWAITE below). COWPERTHWAITE discloses the following limitations that are not disclosed by MEIRI: wherein the unit of data is trained data of an artificial intelligence model (see [0197]: learning model to adjust weights and train a neural network, these weights would be the trained data). Deep neural networks can learn features based on statistical structure and be specialized for a specific task (see [0196]). It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify MEIRI to use trained data of an artificial intelligence model, as disclosed by COWPERTHWAITE. One of ordinary skill in the art would have been motivated to make such a modification to be able to learn features and be specialized for a specific task, as taught by COWPERTHWAITE. MEIRI and COWPERTHWAITE are analogous/in the same field of endeavor as both references are directed to computational nodes. Allowable Subject Matter Claims 6, 7, 11, 14 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The state of the art fails to anticipate, or render obvious, “… the caches in the set of caches store data based on an identity of the data in that: the set of computational nodes are configured to execute a complex computation; and each computational node is configured to, when storing data in memory, determine an identity of the data, determine if a value of the data is fixed for a remainder of the complex computation, and store the data in the cache memory based on the determination that the value is fixed for the remainder of the complex computation.” The state of the art fails to anticipate, or render obvious, “… determining that the unit of data is read-only data based on a variable of the unit of data appearing in a single assign statement in a source code.” Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. SUZUKI - [2026/0079831]: discloses a cache refill operation with a flag to determine if the address of the read request indicates refill data having a fixed value. [0162]-[0168] BAJIC [2022/0318144] discloses a computation node with multiple cache memories, each cache is configured based on the data structure stored in the cache. [Abstract] Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD J DUDEK JR whose telephone number is (571)270-1030. The examiner can normally be reached Monday - Friday, 8:00A-4:00P. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain T Alam can be reached at 571-272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /EDWARD J DUDEK JR/Primary Examiner, Art Unit 2132
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Prosecution Timeline

Jan 31, 2025
Application Filed
Apr 02, 2026
Non-Final Rejection mailed — §102, §103
Apr 15, 2026
Response Filed

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Prosecution Projections

1-2
Expected OA Rounds
89%
Grant Probability
94%
With Interview (+5.1%)
2y 4m (~1y 0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1112 resolved cases by this examiner. Grant probability derived from career allowance rate.

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